CN108198815B - Semiconductor device, method for manufacturing the same, and electronic equipment including the same - Google Patents

Abstract

A semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are disclosed. According to an embodiment, a semiconductor device includes: a substrate; the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction; a gate stack formed around a periphery of the channel region; a first contact to the second source/drain region over the second source/drain region, wherein a first contact perimeter is substantially aligned with a second source/drain region perimeter.

Description

Semiconductor device, method for manufacturing the same, and electronic equipment including the same

technical field

The present disclosure relates to the field of semiconductors, and in particular, to a vertical type semiconductor device, a method of manufacturing the same, and an electronic device including such a semiconductor device.

Background technique

In a horizontal type device such as a metal oxide semiconductor field effect transistor (MOSFET), the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, reducing the area occupied by the horizontal type device generally requires the area occupied by the source, drain and gate to be reduced, resulting in poor device performance (for example, increased power consumption and resistance). The area cannot be further reduced. In contrast, in a vertical type device, the source, gate and drain are arranged in a direction approximately perpendicular to the substrate surface. Therefore, the area occupied by the vertical device is easier to shrink than the horizontal device.

SUMMARY OF THE INVENTION

In view of this, an object of the present disclosure is, at least in part, to provide a vertical type semiconductor device with improved performance, a method of manufacturing the same, and an electronic device including such a semiconductor device.

According to one aspect of the present disclosure, there is provided a semiconductor device comprising: a substrate; a vertical active region formed on the substrate, including a first source/drain region, a channel region and a first source/drain region, a channel region and a first source/drain region arranged in sequence along a vertical direction Two source/drain regions; a gate stack formed around the periphery of the channel region; a first contact portion above the second source/drain region to the second source/drain region, wherein the periphery of the first contact portion and the second source/drain region The zone perimeters are substantially aligned.

According to one aspect of the present disclosure, a semiconductor device is provided, which includes: a substrate; a vertical active region formed on the substrate, including a first source/drain region and a channel region sequentially arranged along a vertical direction and a second source/drain region; a gate stack formed around the periphery of the channel region; isolation walls formed over the gate stack and on the sidewalls of the active region; self-contained walls formed over the gate stack and on the sidewalls of the isolation walls Align metal contacts.

According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising: disposing an active region material layer on a substrate; disposing a hard mask layer on the active region material layer, the hard mask layer comprising: in the first part defining the active area; using the hard mask layer as a mask, patterning the active area material layer to define the vertical active area; forming an interlayer dielectric layer on the substrate and flattening it process to expose the hard mask layer; selectively etch the hard mask layer to remove the hard mask layer, thereby leaving first trenches corresponding to the vertical active regions in the interlayer dielectric layer; A groove is filled with conductive material to form the first contact portion.

According to another aspect of the present disclosure, there is provided an electronic apparatus including an integrated circuit formed from the above-described semiconductor device.

According to an embodiment of the present disclosure, the periphery of the first contact is substantially aligned with the periphery of the second source/drain region, thereby increasing the integration density of the device and reducing masking steps, thereby reducing the manufacturing cost. Aligning the contacts and the contact pillars increases the integration density and reduces the difficulty of forming the contacts. It is thereby possible to form metal contacts with high aspect ratios (avoiding the difficulty of etching the contact holes using eg plasma etching and refilling the contact holes with a material such as metal), and due to the reduction of photolithography steps The risk of lithographic misalignment is reduced, further increasing the integration density. In addition, since double patterning is not employed, the manufacturing cost is reduced.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

1 to 14 show schematic diagrams of a process for manufacturing a semiconductor device according to an embodiment of the present disclosure;

15 to 21 are schematic diagrams showing a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure;

22 to 29 are schematic diagrams showing a flow of manufacturing a semiconductor device according to yet another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numbers refer to the same or similar parts.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. element. In addition, if a layer/element is "on" another layer/element in one orientation, then when the orientation is reversed, the layer/element may be "under" the other layer/element.

A vertical type semiconductor device according to an embodiment of the present disclosure may include a first source/drain layer, a channel layer and a second source/drain layer sequentially stacked on a substrate. The layers can be adjacent to each other, and of course other semiconductor layers, such as leakage suppression layers and/or on-state current enhancement layers (semiconductor layers with larger or smaller band gaps than adjacent layers) may also be present in between. Source/drain regions of the device may be formed in the first source/drain layer and the second source/drain layer, and channel regions of the device may be formed in the channel layer. According to an embodiment of the present disclosure, such a semiconductor device may be a conventional field effect transistor (FET). In the case of a FET, the first source/drain layer and the second source/drain layer (or, in other words, the source/drain regions on either side of the channel layer) may have doping of the same conductivity type (eg, n-type or p-type) miscellaneous. A conductive channel can be formed through the channel region between the source/drain regions located at both ends of the channel region. Alternatively, such a semiconductor device may be a tunneling FET. In the case of a tunnel FET, the first source/drain layer and the second source/drain layer (or, in other words, the source/drain regions on either side of the channel layer) may have different conductivity types (eg, n-type and p-type, respectively) type) doping. In this case, charged particles, such as electrons, can tunnel from the source region through the channel region into the drain region, thereby forming a conduction path between the source and drain regions. Although the conduction mechanisms in conventional FETs and tunnel FETs are not the same, they both exhibit electrical properties that can control conduction between source/drain regions through the gate. Therefore, the terms "source/drain layer (source/drain region)" and "channel layer (channel region)" are collectively described for conventional FETs and follow-through FETs, although the usual meanings do not exist in tunneling FETs on the "channel".

A gate stack may be formed around the periphery of the channel layer. Thus, the gate length can be determined by the thickness of the channel layer itself, rather than relying on time-consuming etch as in the conventional technique. The channel layer can be formed, for example, by epitaxial growth, so that its thickness can be well controlled. Therefore, the gate length can be well controlled. The outer periphery of the channel layer may be recessed inward with respect to the outer periphery of the first and second source/drain layers. In this way, the formed gate stack can be embedded in the recess of the channel layer relative to the first and second source/drain layers. Preferably, the range of the gate stack in the stacking direction (vertical direction, for example substantially perpendicular to the surface of the substrate) of the first source/drain layer, the channel layer and the second source/drain layer is within the range where the recess is in the range in the direction. Thus, the overlap with the source/drain regions can be reduced or even avoided, helping to reduce the parasitic capacitance between the gate and the source/drain.

The channel layer may be composed of a single crystal semiconductor material such as single crystal silicon or silicon germanium (SiGe) to improve device performance. Of course, the first and second source/drain layers can also be made of single crystal semiconductor material. In this case, the single crystal semiconductor material of the channel layer and the single crystal semiconductor material of the source/drain layers may be eutectic. The electron or hole mobility of the single crystal semiconductor material of the channel layer may be greater than the electron or hole mobility of the first and second source/drain layers. In addition, the forbidden band widths of the first and second source/drain layers may be larger than that of the single crystal semiconductor material of the channel layer.

According to an embodiment of the present disclosure, the single crystal semiconductor material of the channel layer and the first and second source/drain layers may have the same crystal structure. In this case, the lattice constants of the first and second source/drain layers without strain may be greater than the lattice constants of the single crystal semiconductor material of the channel layer without strain. Thus, the carrier mobility of the single crystal semiconductor material of the channel layer may be greater than its carrier mobility without strain, or the effective mass of the carriers of the single crystal semiconductor material of the channel layer may be less than that in the The effective mass of carriers without strain, or the concentration of lighter carriers of the channel layer single crystal semiconductor material, may be greater than its concentration without strain. Alternatively, the unstrained lattice constants of the first and second source/drain layers may be smaller than the unstrained lattice constants of the single crystal semiconductor material of the channel layer. Thus, when the <110> direction of the channel layer single crystal semiconductor material is parallel to the current density vector between the source and drain, the electron mobility of the channel layer single crystal semiconductor material is greater than its electron mobility without strain , or the effective mass of the electrons of the single crystal semiconductor material of the channel layer is less than that of the electrons in the absence of strain.

According to an embodiment of the present disclosure, the doping to the source/drain regions may partially enter the channel layer near the ends of the first source/drain layer and the second source/drain layer. Thus, doping distribution is formed at the end of the channel layer close to the first source/drain layer and the second source/drain layer, which helps to reduce the resistance between the source/drain region and the channel region when the device is turned on , thereby improving device performance.

According to an embodiment of the present disclosure, the channel layer may include a different semiconductor material than the first and second source/drain layers. In this way, it is advantageous to process the channel layer, such as selective etching, so as to be recessed relative to the first and second source/drain layers. In addition, the first source/drain layer and the second source/drain layer may include the same semiconductor material.

For example, the first source/drain layer may be the semiconductor substrate itself. In this case, the channel layer may be a semiconductor layer epitaxially grown on the substrate, and the second source/drain layer may be a semiconductor layer epitaxially grown on the channel layer. Alternatively, the first source/drain layer may be a semiconductor layer epitaxially grown on the substrate. In this case, the channel layer may be a semiconductor layer epitaxially grown on the first source/drain layer, and the second source/drain layer may be a semiconductor layer epitaxially grown on the channel layer.

According to embodiments of the present disclosure, stress liner layers may also be provided on the surfaces of the first source/drain layer and the second source/drain layer. For n-type devices, the stressed liner can be compressively stressed to create tensile stress in the channel layer; for p-type devices, the stressed liner can be tensile stressed to create compressive stress in the channel layer. Therefore, the device performance can be further improved.

According to an embodiment of the present disclosure, the outer periphery of the first contact portion substantially coincides with the outer periphery of the second source/drain region; or the semiconductor device may further include a metal-semiconductor compound layer formed on the surface of the second source/drain region, The outer periphery of the first contact portion substantially coincides with the outer periphery of the metal-semiconductor compound layer formed on the surface of the second source/drain region.

According to an embodiment of the present disclosure, the first source/drain region includes a laterally extending portion that can extend beyond the active region portion thereover, and the device further includes: above the laterally extending portion of the first source/drain region to the first source/drain region A second contact portion of the drain region, the second contact portion may include a first portion and a second portion sequentially stacked on the substrate and vertically aligned with each other, the first portion may include a low resistance semiconductor material and/or Metal-semiconductor compounds. The second portion of the second contact portion may include the same material as the first contact portion and substantially the same thickness in the vertical direction as the first contact portion, and the first portion of the second contact portion may include semiconductor material and/or metal Semiconductor compound material. The first portion of the second contact includes elements in the semiconductor material that are at least partially the same as those in the first source/drain region or the channel region or part of the semiconductor element in the second source/drain region.

According to an embodiment of the present disclosure, the first contact portion and or the second contact portion includes metals Cu, Co, W, Ru, combinations thereof, and the like.

According to an embodiment of the present disclosure, the second contact portion may further include a metal layer surrounding the peripheries of the first portion and the second portion, and the metal layer may include metals Cu, Co, W, Ru, or a combination of any of them.

According to an embodiment of the present disclosure, the device may further include a third contact to the gate conductor layer in the gate stack. Wherein, the third contact portion and the gate conductor layer may be integral; or the third contact portion includes the same material as the first contact portion.

According to an embodiment of the present disclosure, the present application further discloses a semiconductor device, which includes: a substrate; a vertical active region formed on the substrate, including first source/drain regions arranged in sequence along a vertical direction, channel region and second source/drain regions; gate stack formed around the perimeter of the channel region; isolation walls formed over the gate stack and on the sidewalls of the active region; over the gate stack and on the sidewalls of the isolation walls Formed self-aligned metal contacts.

According to an embodiment of the present disclosure, the device may further include a third contact formed over the self-aligned metal contact and substantially self-aligned with the self-aligned metal contact; and may further include over the gate stack and on the isolation wall A conformally formed diffusion barrier layer may be included over the sidewalls of the diffusion barrier layer; a conformally formed metal contact layer may be included over the diffusion barrier layer; and a conformally formed thin dielectric layer may be included over the sidewalls of the metal contact layer. In addition, the device may further include a self-aligned metal contact formed by the diffusion barrier layer and the metal contact layer; a third contact formed on the self-aligned metal contact and substantially self-aligned with the self-aligned metal contact . The self-aligned metal contact and/or the third contact may comprise metals Cu, Co, W, Ru, combinations thereof, and the like.

Such a semiconductor device can be manufactured, for example, as follows. Specifically, a stack of first source/drain layers, channel layers and second source/drain layers may be provided on the substrate. As mentioned above, the first source/drain layer may be provided by the substrate itself or by epitaxial growth on the substrate. Next, a channel layer may be epitaxially grown on the first source/drain layer, and a second source/drain layer may be epitaxially grown on the channel layer. During epitaxial growth, the thickness of the grown channel layer can be controlled. Due to the separate epitaxial growth, at least some adjacent layers may have clear crystallographic interfaces. In addition, the layers may be individually doped differently, so that at least some adjacent layers may have a doping concentration interface between them.

For the stacked first source/drain layer, channel layer and second source/drain layer, an active region may be defined therein. For example, they can be selectively etched sequentially into a desired shape. Typically, the active region may be columnar (e.g., cylindrical). In order to facilitate connection of the source/drain regions formed in the first source/drain layer in the subsequent process, the etching of the first source/drain layer may only target the upper part of the first source/drain layer, so that the first source/drain layer The lower part may extend beyond the periphery of its upper part. Then, a gate stack may be formed around the periphery of the channel layer.

In addition, the outer periphery of the channel layer may be recessed inwardly with respect to the outer periphery of the first and second source/drain layers so as to define a space for accommodating the gate stack. For example, this can be achieved by selective etching. In this case, the gate stack can be embedded in the recess.

Source/drain regions may be formed in the first and second source/drain layers. For example, this can be achieved by doping the first and second source/drain layers. For example, ion implantation, plasma doping, or in-situ doping during growth of the first and second source/drain layers may be performed. According to an advantageous embodiment, sacrificial gates may be formed in the recesses formed in the periphery of the channel layer relative to the periphery of the first and second source/drain layers, and then on the surfaces of the first and second source/drain layers A dopant source layer is formed, and the dopant in the dopant source layer is brought into the active region through the first and second source/drain layers by, for example, annealing. The sacrificial gate prevents dopants in the dopant source layer from directly entering the channel layer. However, part of the dopants may enter the channel layer through the first and second source/drain layers near the ends of the first source/drain layer and the second source/drain layer.

The present disclosure may be presented in various forms, some examples of which are described below.

1 to 14 illustrate flowcharts of fabricating semiconductor devices according to embodiments of the present disclosure.

As shown in FIG. 1, a substrate 1001 is provided. The substrate 1001 may be various forms of substrates, including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, and the like. In the following description, for the convenience of description, a bulk Si substrate is used as an example for description.

On the substrate 1001, a channel layer 1003, another semiconductor layer 1005, and a hard mask layer 1031 may be sequentially formed by, for example, epitaxial growth. For example, the channel layer 1003 may include a semiconductor material different from the substrate 1001 and the semiconductor layer 1005, such as SiGe (the atomic percentage of Ge may be about 10-40%), with a thickness of about 10-100 nm; the semiconductor layer 1005 may include a The bottom 1001 is the same semiconductor material as Si, with a thickness of about 20-50 nm. The hard mask layer 1031 may include nitride such as silicon nitride with a thickness of about 30-100 nm. Of course, the present disclosure is not limited thereto. For example, the channel layer 1003 may include the same constituent composition as the substrate 1001 or the semiconductor layer 1005, but a semiconductor material with a different composition content (eg, both SiGe, but with a different atomic percentage of Ge), as long as the channel layer 1003 has etch selectivity with respect to the overlying substrate 1001 and the overlying semiconductor layer 1005.

Next, the active region of the device can be defined. For example, this can be done as follows. Specifically, as shown in Figs. 2(a) and 2(b) (Fig. 2(a) is a cross-sectional view and Fig. 2(b) is a top view, in which the AA' line shows the cut-off position of the cross-section), the A photoresist (not shown) is formed on the stack of the substrate 1001, the channel layer 1003, the semiconductor layer 1005 and the hard mask layer 1031 shown in FIG. 1, and the photoresist is patterned by photolithography (exposure and development). are two desired shapes (in this example, it is roughly circular, other shapes, such as rectangles can also be used), and the patterned photoresist is used as a mask, and the hard mask layer 1031 and the semiconductor layer 1005 are sequentially applied. , the channel layer 1003 and the substrate 1001 are selectively etched such as reactive ion etching (RIE). Etching proceeds into the substrate 1001, but not at the bottom surface of the substrate 1001. Thus, the hard mask layer 1031, the semiconductor layer 1005, the channel layer 1003, and the upper portion of the substrate 1001 after etching form two pillars (in this example, cylindrical). Correspondingly, the hard mask layer 1031, the semiconductor layer 1005 and the channel layer 1003 are respectively formed as two parts of the first hard mask layer 1031-1, the second hard mask layer 1031-2 and the first semiconductor layer 1005-1 , a second semiconductor layer 1005-2, a first channel layer 1003-1, and a second channel layer 1003-2. Since the patterning of the active region material layer is stopped before proceeding to the bottom surface of the active region material layer, the active region material layer is patterned to correspond to the first hard mask layer 1031-1 serving as an active region The first stack (ie, the left pillar) and the second stack (ie, the right pillar) corresponding to the second hard mask layer 1031-2, and the first stack and the second stack are connected together at the bottom. The RIE can be performed, for example, in a direction generally perpendicular to the substrate surface, so that the first stack and the second stack are also generally perpendicular to the substrate surface. Afterwards, the photoresist can be removed.

A first isolation layer such as a shallow trench isolation layer 1033 may be formed around the first stack (active region) and the second stack to achieve electrical isolation. For example, as shown in FIG. 2(a), trenches may be patterned on the structure, oxide deposited, and etched back to the position of the upper surface of the bottom of the substrate 1001 to form the first isolation layer 1033. The deposited oxide may be planarized, such as chemical mechanical polishing (CMP) or sputtering, prior to etch back. Here, the top surface of the first isolation layer 1033 may be close to the interface between the channel layer 1003 and the substrate 1001.

Then, as shown in FIG. 3, the periphery of the first channel layer 1003-1 may be recessed with respect to the periphery of the substrate 1001 and the first semiconductor layer 1005-1 (in this example, along a direction substantially parallel to the surface of the substrate is concave in the lateral direction). For example, this can be achieved by further selectively etching the channel layer 1003-1 with respect to the substrate 1001 and the first semiconductor layer 1005-1. For example, selective etching can be performed using Atomic Layer Etch or Digital Etch. For example, first capping by, for example, depositing over the right pillar (consisting of the second hard mask layer 1031-2, the second semiconductor layer 1005-2, the second channel layer 1003-2, and a portion of the substrate 1001) A layer of oxynitride, followed by, for example, thermal treatment, oxidizes another portion of the substrate 1001, the surfaces of the first hard mask layer 1031-1, the first channel layer 1003-1, and the first semiconductor layer 1005-1, and then Remove their respective surface oxide layers. In the case where the first channel layer 1003-1 is SiGe and the substrate 1001 and the first semiconductor layer 1005-1 are Si, the oxidation rate of SiGe is higher than that of Si, and the oxide on SiGe is easier to remove. The oxidation-removal steps can be repeated to achieve the desired recess. Compared to selective etching, this method can better control the degree of concave.

In this way, the active region of the semiconductor device (the etched substrate 1001, especially the upper part, the first channel layer 1003-1 and the first semiconductor layer 1005-1, as shown on the left side of FIG. 3 , is defined cylinder). In this example, the active regions are substantially columnar. In the active region, the upper portion of the substrate 1001 and the outer periphery of the first semiconductor layer 1005-1 are substantially aligned, and the outer periphery of the first channel layer 1003-1 is relatively concave. The upper and lower sidewalls of the concave are defined by interfaces between the first channel layer 1003-1 and the first semiconductor layer 1005-1 and the first channel layer 1003-1 and the substrate 1001, respectively.

Of course, the shape of the active region is not limited to this, and other shapes may be formed according to the layout. For example, in a top view, the active region may be oval, square, rectangular, or the like.

In a recess formed with respect to the upper portion of the substrate 1001 and the outer periphery of the first semiconductor layer 1005-1 of the first channel layer 1003-1, a gate stack will be formed subsequently. In order to prevent subsequent processing from affecting the channel layer 1003 or leaving unnecessary materials in the recess to affect the formation of subsequent gate stacks, a material layer can be filled in the recess to occupy the space of the gate stack (thus, This layer of material may be referred to as a "sacrificial gate"). This can be accomplished, for example, by depositing oxynitride on the structure shown in Figure 3, followed by an etchback such as RIE on the deposited oxynitride. RIE can be performed in a direction approximately perpendicular to the substrate surface to remove excess oxynitride, and at the same time remove the oxynitride formed on the right pillar by the previous process, so that the oxynitride can remain only in the recess, forming a sacrificial Grid 1007, as shown in FIG. 4 . In this case, the sacrificial gate 1007 may substantially fill the aforementioned recess.

Next, source/drain regions may be formed in the substrate 1001 and the first semiconductor layer 1005-1. This can be formed by doping the substrate 1001 and the first semiconductor layer 1005-1. For example, this can be done as follows.

Specifically, as shown in FIG. 5 , a dopant source layer 1009 may be formed on the structure shown in FIG. 4 . For example, the dopant source layer 1009 may comprise an oxide such as silicon oxide, in which the dopant is contained. For n-type devices, n-type dopants may be included; for p-type devices, p-type dopants may be included. Here, the dopant source layer 1009 may be a thin film so that it may be substantially conformally deposited on the surface of the structure shown in FIG. 4 by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Next, as shown in FIG. 6, the dopant contained in the dopant source layer 1009 can be brought into the active region and the left pillar as the second stack by, for example, annealing, thereby forming a doped region therein, As shown in the shaded area in the figure. More specifically, one of the source/drain regions 1011-1 may be formed in the substrate 1001, and the other source/drain region 1011-2 may be formed in the first semiconductor layer 1005-1. In addition, the dopant also enters a portion of the substrate 1001, the second channel layer 1003-2, and the second semiconductor layer 1005-2 that constitute the second stack. And as can be seen from Fig. 6, the dopant source layer 1009 includes a portion extending along the horizontal surface of the substrate 1001, so that the doped region formed in the substrate 1001 extends beyond the periphery of the columnar body. The first and second stacks, which are pillars, are conductively connected together at the bottom by horizontal extensions of the doped substrate 1001, after which the dopant source layer 1009 can be removed.

In addition, despite the existence of the sacrificial gate 1007, dopants can also enter the first channel layer 1003-1 via the substrate 1001 and the first semiconductor layer 1005-1, so that the A certain doping distribution is formed at the upper and lower ends, as shown by the elliptical dotted circle in the figure. This doping profile can reduce the resistance between the source and drain regions when the device is turned on, thereby improving device performance.

In the above examples, the source/drain regions are formed by driving in dopants from the dopant source layer into the active regions, but the present disclosure is not limited thereto. For example, the source/drain regions may be formed by ion implantation, plasma doping (eg, conformal doping along the surface of the structure in FIG. 4 ). Alternatively, in the process described above in connection with FIG. 1, a well region may be formed in substrate 1001, followed by growing channel layer 1003 thereon, followed by in situ doping on semiconductor layer 1005 grown on channel layer 1003 miscellaneous. While growing the channel layer 1003, it can also be doped in-situ in order to adjust the threshold voltage ( _Vt ) of the device.

Additionally, to reduce contact resistance, the source/drain layers and the second stack may also be silicided. As shown in FIG. 7(a), for example, a layer of NiPt (or Co or Ti) may be deposited on the structure shown in FIG. 6, for example, with a Pt content of about 2-10% and a thickness of about 2-10 nm, And annealed at a temperature of about 200-900°C, the NiPt reacts with Si (in the source/drain layer) or SiGe (in 1003-2) to generate metal-semiconductor compounds such as SiNiPt or SiGeNiPt. After that, the unreacted residual NiPt can be removed.

It is worth noting that, since the second stack (ie, the right pillar) is not used as an active area, but only as a conductive path, in another embodiment, as shown in FIG. 7(b), it is possible to make NiPt deposited on the second stack (i.e., the right pillar) reacts sufficiently with Si and SiGe, with the finer right pillar, a portion of the substrate and the semiconductor in the second semiconductor layer 1005-2 Materials such as doped silicon and silicon germanium in the second channel layer 1006-2 can react sufficiently with NiPt (or Co or Ti) deposited on the right pillar to fully generate metal semiconductor compounds (including metal silicides) and/or metal silicon germanide), thereby forming a monolithic metal semiconductor compound. After that, the unreacted residual NiPt can be removed.

A second isolation layer may be formed over the substrate and the shallow trench isolation layer. Specifically, as shown in FIG. 8 , oxide is deposited over the substrate 1001 and the shallow trench isolation layer 1033 and etched back to The position of the interface between the channel layers 1003 - 1 and 1003 - 2 and the substrate 1001 (ie, the interface between the SiGe layer and the Si layer) to form the second isolation layer 1013 . The deposited oxide may be planarized, such as chemical mechanical polishing (CMP) or sputtering, prior to etch back.

A gate dielectric layer and a gate conductor layer may be formed in the recess. Specifically, as shown in FIG. 9 , the sacrificial gate 1007 may be removed on the structure shown in FIG. 8 , the gate dielectric layer 1015 and the gate conductor layer 1017 may be sequentially deposited, and the deposited gate conductor layer 1017 may be etched back. Make it flush with the top surfaces of hard mask layers 1031-1 and 1031-2. For example, the gate dielectric layer 1015 may include a high-K gate dielectric such as HfO ₂ ; the gate conductor layer 1017 may include a metal gate conductor. In addition, between the gate dielectric layer 1015 and the gate conductor layer 1017, a work function adjustment layer may also be formed, and the function adjustment layer may include a threshold voltage Vt adjustment metal. Before forming the gate dielectric layer 1015, an interface layer such as oxide may also be formed.

In this way, the gate dielectric layer 1015 and the gate conductor layer 1017 can be embedded in the recess, and the top surfaces of the gate dielectric layer 1015 and the gate conductor layer 1017 are flush with the top surfaces of the hard mask layers 1031-1 and 1031-2.

The gate conductor layer may be patterned to form a gate stack, specifically, as shown in FIG. 10 , photoresist may be coated on the structure shown in FIG. 9 , and the photoresist may be patterned to form a photoresist layer 1039, and then using the photoresist 1039 as a mask, the gate conductor layer 1017 is selectively etched such as RIE. In this way, the rest of the gate conductor layer 1017 is etched to be no higher than and preferably lower than the channel layer 1003-1, except for the portion of the gate conductor layer 1017 that remains within the recess and the portion blocked by the photoresist 1019. , the top surface of 1003-2.

Then, as shown in FIG. 11, the photoresist layer 1039 is removed, the photoresist is coated again, and the photoresist is patterned to form the photoresist layer 1019, and then the photoresist 1019 is used as a mask, and the remaining The gate conductor layer 1017 is again subjected to selective etching such as RIE. In this way, the rest of the gate conductor layer 1017 is etched away except for the portion of the gate conductor layer 1017 that remains in the recess and the portion shielded by the photoresist 1039 . Thus, the gate conductor layer is formed only around the first stack as the active region, and there is no gate conductor layer around the second stack. At this time, the gate conductor layer 1017 and the gate dielectric layer 1015 form a gate stack. The gate stack can be used as a gate contact.

Then, as shown in FIG. 12 , an interlayer dielectric layer 1021 may be formed on the structure shown in FIG. 11 . Specifically, for example, an oxide may be deposited and planarized such as CMP to form an interlayer dielectric layer 1021, which is planarized to be aligned with the top surfaces of the hard mask layers 1031-1, 1031-2 flush.

Then, in FIG. 13, the hard mask layers 1031-1, 1031-2 may be selectively etched to form first and second grooves T1 and T2 in the interlayer dielectric layer 1021. Then, as shown in FIG. 14, a contact metal may be deposited thereover and planarized, such as by CMP, to the top surface of the interlayer dielectric layer 1021, thereby forming self-contained metal in the first and second grooves T1 and T2. Aligned first metal contact 1023-1 and second metal contact 1023-2, first metal contact 1023-1 and or second metal contact 1023-2 may each contain metals Cu, Co, W, Ru and combinations thereof.

As shown in FIG. 14, the first metal contact 1023-1 is aligned with the source/drain region (which is formed by the first semiconductor layer 1005-1) above the first channel layer 1003-1, specifically, the first metal The periphery of the contact portion 1023-1 is substantially aligned with the periphery of the first semiconductor layer 1005-1, and further, the periphery of the first metal contact portion 1023-1 is substantially coincident with the periphery of the first semiconductor layer 1005-1. Also, the first metal contact 1023-1 may serve as a contact for the source/drain region (which is formed by the first semiconductor layer 1005-1). The second metal contact 1023-2 and the conductive second stack are vertically aligned with each other and may together function as source/drain regions (which are formed by a portion of the substrate 1001) under the first channel layer 1003-1 formed) contacts. As previously mentioned, the conductive second stack may comprise a low resistance semiconductor material, in particular, may comprise doped semiconductor materials such as doped silicon and doped germanium and/or metal semiconductor compound materials. The metal-semiconductor compound material includes a metal silicide material and/or a metal silicon germanide material. Obviously, according to the aforementioned embodiments, the conductive second stack can also be entirely of metal-semiconductor compound material. And the second metal contact portion 1023-2 may include the same material as the first metal contact portion 1023-1.

Thus, FIG. 14 illustrates a vertical semiconductor device in accordance with an embodiment of the present invention in which conductive contacts with a high aspect ratio are formed using self-aligned metal contacts and conductive stacked pillars, thereby increasing the The integration density is reduced and the difficulty of forming the contacts is avoided (eg, the process difficulty of etching the contact holes using plasma etching and refilling the contact holes with a material such as metal is avoided). At the same time, masking steps are also reduced, thereby reducing manufacturing costs.

15 to 21 are schematic diagrams illustrating a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Since the first half of the process of fabricating a semiconductor device according to another embodiment of the present disclosure is the same as the first half of the process of fabricating a semiconductor device of the previous embodiment (refer to the relevant description part of FIGS. 1-9 in particular), for the sake of brevity , and will not be repeated here.

As shown in FIG. 15 , on the structure of FIG. 9 , the gate conductor layer 1017 is etched such as RIE, so that the gate conductor layer 1017 is etched not higher than and preferably lower than the channel layers 1003-1 and 1003-2 the top surface. Oxide spacers are then formed on the sidewalls of the first stack and the second stack.

As shown in Figure 16, a diffusion barrier layer and a contact metal layer may be sequentially formed over the structure shown in Figure 15. Specifically, first, a diffusion barrier layer 1043 is conformally deposited over the structure shown in FIG. 15 , and the diffusion barrier layer 1043 may include a metal including TiN, TaN, or Ti, etc., with a thickness of 1 to 10 nm. A contact metal layer 1045 is then conformally deposited over the diffusion barrier layer 1043. The contact metal layer 1045 may include metals Cu, Co, W, Ru and combinations thereof, etc., and the thickness of the contact metal layer 1045 is 5-20 nm.

Next, selective etching such as the RIE contact metal layer, etching the diffusion barrier layer, etching the oxide spacer, and etching such as the RIE gate conductor layer may be performed sequentially. For example, this can be done as follows. Specifically, as shown in Figs. 17, 18(a) and 18(b) (Fig. 18(a) is a cross-sectional view and Fig. 18(b) is a top view, in which the AA' line shows the cut-off position of the cross-section), A photoresist may be formed on the contact metal layer 1045, and the photoresist 1019' may be patterned by photolithography to expose portions where contact holes are to be formed. Then, using the patterned photoresist 1203 as a mask, the contact metal layer 1045 is selectively etched such as RIE, the diffusion barrier layer 1043 is selectively etched, the oxide partition wall is selectively etched, and Selective etching such as RIE is performed on the gate conductor layer 1017 . Here, the etching may stop on the gate dielectric layer 1015 and the hard mask layers 1031-1, 1031-2 on the upper surface of the substrate 1001. Here, the rest of the gate conductor layer 1017 is etched away except for the portion of the gate conductor layer 1017 left in the recess and the portion blocked by the photoresist 1019'. The rest of the contact metal layer 1045, the diffusion barrier layer 1043, and the oxide spacers are etched away except for the portion blocked by the photoresist 1019'. Another embodiment is to first perform selective etching on the contact metal layer 1045, such as RIE, stop on the diffusion barrier layer 1043, and then perform selective etching on the diffusion barrier layer 1043 and the gate conductor layer 1017 (eg, RIE, selectively The metal isolation wall formed by the contact metal layer 1045 is left), and then the photoresist 1019' is used to block and etch, and only the part of the metal isolation wall that needs to form the upper metal contact is retained. The metal sidewall includes metal Cu, Co, W, Ru and the like.

Then, as shown in FIG. 19 , an interlayer dielectric layer 1021 may be formed on the structure shown in FIG. 11 . Specifically, for example, the photoresist shown in FIG. 11 may be removed, followed by conformal deposition of a thin dielectric layer 1047, and selective etching away of the top surfaces of the hardmask layers 1031-1, 1031-2. Thin dielectric layer 1047 portion. A thin dielectric layer 1047 may serve as a protective and/or diffusion barrier layer, may include a nitride material, and be 2 to 20 nm thick. Oxide is then deposited and planarized, such as by CMP, to form an interlayer dielectric layer 1021, which is planarized to be flush with the top surfaces of the hard mask layers 1031-1, 1031-2. The thickness of the interlayer dielectric layer 1021 is 40 to 200 nm.

Then, as shown in FIG. 20 , the first groove T1 , the second groove T2 , and the third groove T3 may be formed on the structure shown in FIG. 19 . Specifically, the hard mask layers 1031-1, 1031-2 and the thin dielectric layer 1047 formed of a nitride material and the contact metal layer 1045 and the diffusion barrier layer 1043 formed of a metal material can be selectively etched such as RIE to the same depth to form the first groove T1, the second groove T2 and the third groove T3 in the interlayer dielectric layer 1021

Then, as shown in FIG. 21, a contact metal may be deposited thereover and planarized, such as by CMP, to the top surface of the interlayer dielectric layer 1021, thereby forming a Aligned first metal contact 1023-1, second metal contact 1023-2, and third metal contact 1023-3, first metal contact 1023-1, second metal contact 1023-2, and third metal contact Each of the metal contacts 1023-3 may include metals Cu, Co, W, Ru, combinations thereof, and the like.

The first metal contact 1023-1 may serve as a contact for the source/drain region (which is formed by the first semiconductor layer 1005-1). The second metal contact 1023-2 and the conductive second stack are vertically aligned with each other, and may together function as source/drain regions under the first channel layer 1003-1 (which are formed by the substrate 1001). part of the contact part formed). The third metal portion 1023-3 may function as a gate contact together with the contact metal layer 1045, the diffusion barrier layer 1043, and the gate conductor layer 1017 located thereunder. The first metal contact part 1023-1, the second metal contact part 1023-2 and the third metal contact part 1023-3 may be formed of the same material.

Thus, FIG. 21 shows a vertical type semiconductor device according to another embodiment of the present invention. The difference from the previous embodiment is that the third metal contact 1023-3 is used instead of only the gate conductor layer 1017 to form the gate contact.

In a further embodiment, in order to increase the electrical conductivity, i.e., to reduce the contact resistance of each contact, a process step of forming a conductive metal is added to the aforementioned process. Specifically, FIGS. 22 to 29 show schematic diagrams of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

Since the first half of the process of manufacturing the semiconductor device according to another embodiment of the present disclosure is the same as the first half of the process of manufacturing the semiconductor device of the previous embodiment (refer to the relevant description part of FIGS. 1 to 7( a ) or 7( b ) for details ) are the same, so for the sake of brevity, they are not repeated here.

As shown in Fig. 22, a metal layer material including W, Co or Ru is deposited on the structure shown in Fig. 7(a). Then, a barrier/STI oxide etch stop layer (not shown) is deposited as required. The metal layer material is patterned using the photoresist 1042 and the metal not covered by the photoresist 1042 is etched away, thereby forming the patterned metal layer 1041. Metal layer 1041 serves as a metal line or metal contact.

In Figure 23, similar to the steps shown in Figure 8, the photoresist is removed, oxide is deposited over the substrate 1001 and the shallow trench isolation layer 1033, and etched back to the channel layer 1003-1 and 1003 - 2 and the position of the interface between the substrate 1001 (ie, the interface between the SiGe layer and the Si layer) to form the second isolation layer 1013 . The deposited oxide may be planarized such as chemical mechanical polishing (CMP) or sputtering prior to etch back.

In FIG. 24(a), similar to the steps shown in FIG. 9, a gate dielectric layer and a gate conductor layer may be formed in the recess. Specifically, as shown in FIG. 24( a ), the sacrificial gate 1007 may be removed on the structure shown in FIG. 23 , the gate dielectric layer 1015 and the gate conductor layer 1017 may be deposited in sequence, and the deposited gate conductor layer 1017 may be processed Etch back so that it is flush with the top surfaces of hard mask layers 1031-1 and 1031-2. At the same time, the portion of the metal layer 1041 above the hard mask layer 1031-2 is also removed. For example, the gate dielectric layer 1015 may include a high-K gate dielectric such as HfO ₂ ; the gate conductor layer 1017 may include a metal gate conductor. In addition, between the gate dielectric layer 1015 and the gate conductor layer 1017, a work function adjustment layer may also be formed, and the function adjustment layer may include a threshold voltage Vt adjustment metal. Before forming the gate dielectric layer 1015, an interface layer such as oxide may also be formed.

In this way, the gate dielectric layer 1015 and the gate conductor layer 1017 can be embedded in the recess, and the top surfaces of the gate dielectric layer 1015 and the gate conductor layer 1017 are flush with the top surfaces of the hard mask layers 1031-1 and 1031-2.

In FIG. 24(b), on the basis of the structure shown in FIG. 24(a), a further portion is etched to recess the nitride and metal layers 1041, and then nitride is deposited to form a nitride cap layer 1031-2 (consistent with the material of the hard mask layer 1031-2, which may also be referred to as the hard mask layer 1031-2), thereby better achieving electrical isolation.

In FIG. 25, similar to the steps shown in FIG. 10, the gate conductor layer may be patterned to form a gate stack. Specifically, as shown in FIG. 25, the structure shown in FIG. 24(b) may be coated with Cover with photoresist, pattern the photoresist to form a photoresist layer 1039, and then use the photoresist 1039 as a mask to perform selective etching on the gate conductor layer 1017 such as RIE. In this way, the rest of the gate conductor layer 1017 is etched to be no higher than and preferably lower than the channel layer 1003-1, except for the portion left in the recess and the portion blocked by the photoresist 1019. , the top of the 1003-2.

Then, as shown in FIG. 26, the photoresist layer 1039 is removed, the photoresist is coated again, and the photoresist is patterned to form the photoresist layer 1019, and then the remaining photoresist 1019 is used as a mask. The gate conductor layer 1017 is again subjected to selective etching such as RIE. In this way, the rest of the gate conductor layer 1017 is etched away except for the portion of the gate conductor layer 1017 that remains in the recess and the portion shielded by the photoresist 1039 . Thus, the gate conductor layer is formed only around the first stack as the active region, and there is no gate conductor layer around the second stack. At this time, the gate conductor layer 1017 and the gate dielectric layer 1015 form a gate stack. The gate stack can be used as a gate contact.

Then, as shown in FIG. 27 , an interlayer dielectric layer 1021 may be formed on the structure shown in FIG. 26 . Specifically, for example, an oxide may be deposited and planarized such as CMP to form an interlayer dielectric layer 1021, which is planarized to be aligned with the top surfaces of the hard mask layers 1031-1, 1031-2 flush.

Then, in FIG. 28, the hard mask layers 1031-1, 1031-2 may be selectively etched to form first and second grooves T1 and T2 in the interlayer dielectric layer 1021. Then, as shown in FIG. 29, a contact metal may be deposited thereover and planarized, such as by CMP, to the top surface of the interlayer dielectric layer 1021, thereby forming self-contained metal in the first and second grooves T1 and T2. Aligned first metal contact 1023-1 and second metal contact 1023-2. Since the metal layer 1041 is pre-formed in the second groove, it is helpful to realize better conductive contact of the second contact portion and increase the conductivity.

The semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices, as well as other devices (e.g., other forms of transistors, etc.), integrated circuits (ICs) may be formed, and electronic devices constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above-described semiconductor device. The electronic device may also include components such as a display screen cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit. Such electronic devices are, for example, smartphones, computers, tablet computers (PCs), artificial intelligence, wearable devices, power banks, and the like.

According to an embodiment of the present disclosure, a method of fabricating a system on a chip (SoC) is also provided. The method may include the above-described method of fabricating a semiconductor device. Specifically, a variety of devices can be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.

In the above description, the technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures of the various embodiments cannot be used in combination to advantage.

Embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (25)

1. A semiconductor device, comprising:

a substrate;

the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction;

a gate stack formed around a periphery of the channel region;

a first contact to the second source/drain region over the second source/drain region, wherein a first contact periphery is aligned with a second source/drain region periphery;

wherein the first contact is self-aligned to the second source/drain region;

wherein the first source/drain region includes a laterally extending portion that extends beyond a portion of the active region above it,

the semiconductor device further includes: a second contact to the first source/drain region over the laterally extending portion of the first source/drain region,

wherein the second contact portion includes a first portion and a second portion which are sequentially stacked on the substrate and are aligned with each other in a vertical direction,

wherein the first portion comprises a low resistance semiconductor material and/or a metal semiconductor compound.

2. The semiconductor device of claim 1,

the outer periphery of the first contact part is overlapped with the outer periphery of the second source/drain region; or

The semiconductor device further includes a metal semiconductor compound layer formed on a surface of the second source/drain region, wherein an outer periphery of the first contact portion coincides with an outer periphery of the metal semiconductor compound layer formed on the surface of the second source/drain region.

3. The semiconductor device of claim 1, wherein the first contact and/or the second contact comprise a metal Cu, Co, W, Ru, and combinations thereof.

4. The semiconductor device of claim 1,

the second portion of the second contact includes the same material as the first contact and has the same thickness in the vertical direction as the first contact, and the first portion of the second contact includes a semiconductor material and/or a metal-semiconductor compound material.

5. The semiconductor device of claim 4,

the first portion of the second contact comprises at least partially the same element in the semiconductor material as a portion of the semiconductor element in the first or second source/drain region.

6. The semiconductor device of claim 1, the second contact further comprising a metal layer surrounding a periphery of the first portion and the second portion.

7. The semiconductor device of claim 6, wherein the metal layer surrounding the outer perimeter of the first and second portions of the second contact comprises a metal Cu, Co, W, Ru, or a combination of any of the foregoing.

8. The semiconductor device of claim 1, further comprising:

a third contact to a gate conductor layer in the gate stack.

9. The semiconductor device of claim 8,

the third contact is integral with the gate conductor layer; or

The third contact portion includes the same material as the first contact portion.

10. A semiconductor device, comprising:

a substrate;

the vertical active region is formed on the substrate and comprises a first source/drain region, a channel region and a second source/drain region which are sequentially arranged along the vertical direction;

a gate stack formed around a periphery of the channel region;

a spacer formed over the gate stack and on a sidewall of the active region;

self-aligned metal contacts are formed over the gate stacks and on the sidewall of the isolation walls.

11. The semiconductor device of claim 10, further comprising a third contact formed over the self-aligned metal contact that is self-aligned to the self-aligned metal contact.

12. The semiconductor device of claim 11, further comprising a diffusion barrier layer conformally formed over the gate stack and on sidewalls of the isolation walls;

a metal contact layer formed conformally over the diffusion barrier layer;

a thin dielectric layer conformally formed on the sidewalls of the metal contact layer;

a self-aligned metal contact formed from the diffusion barrier layer and the metal contact layer;

a third contact formed on the self-aligned metal contact and self-aligned to the self-aligned metal contact.

13. The semiconductor device of claim 10 or 11, wherein the self-aligned metal contact and/or the third contact comprise the metals Cu, Co, W, Ru, and combinations of any of them.

14. A method of manufacturing a semiconductor device, comprising:

a source region material layer is arranged on the substrate;

providing a hard mask layer on the active area material layer, the hard mask layer including a first portion for defining an active area;

patterning the active region material layer with the hard mask layer as a mask to define a vertical active region;

forming an interlayer dielectric layer on the substrate, and carrying out planarization treatment on the interlayer dielectric layer to expose the hard mask layer;

selectively etching the hard mask layer to remove the hard mask layer, thereby leaving a first trench in the inter-level dielectric layer corresponding to the vertical active region;

filling the first groove with conductive material, and forming a first contact part by self-alignment

Wherein the hard mask layer further comprises a second portion separate from the first portion,

while patterning the active area material layer, the patterning of the active area material layer is stopped before proceeding to the bottom surface of the active area material layer, whereupon the active area material layer is patterned into a first stack corresponding to a first portion of the hard mask layer, which serves as an active area, and a second stack corresponding to a second portion of the hard mask layer, and the first stack and the second stack are connected together at the bottom,

after selectively etching the hard mask layer, a second trench corresponding to the second stack is left in the interlayer dielectric layer,

when the first groove is filled with the conductive material, the conductive material is also filled into the second groove, thereby forming the second contact portion.

15. The method of claim 14, further comprising:

forming a barrier layer at the periphery of a portion of the first stack where a channel region is to be formed;

forming a dopant source layer on a surface of the first stack and the second stack;

dopants in the dopant source layer are driven into the lower and upper end portions of the first stack to form first and second source/drain regions, respectively, and into the entire second stack.

16. The method of claim 15, further comprising:

a metal-semiconductor compound layer is formed on a surface of the first stack and the second stack in the presence of the barrier layer.

17. The method of claim 15, wherein,

the active region material layer comprises a first source/drain layer, a channel layer and a second source/drain layer which are sequentially stacked,

forming the barrier layer includes:

selectively etching the channel layer such that an outer periphery of the channel layer is recessed with respect to outer peripheries of the first and second source/drain layers;

the barrier layer is formed in a recess formed in an outer periphery of the channel layer with respect to outer peripheries of the first and second source/drain layers.

18. The method of any of claims 14 to 16, further comprising:

forming an isolation layer on a substrate, the isolation layer exposing a portion of the active region that serves as a channel region;

a gate stack is formed on the isolation layer around an outer periphery of a portion of the active region that serves as a channel region.

19. The method of claim 17, further comprising:

forming an isolation layer on a substrate, the isolation layer exposing a portion of the active region that serves as a channel region;

a gate stack is formed on the isolation layer around an outer periphery of a portion of the active region that serves as a channel region.

20. The method of claim 19, wherein forming a gate stack comprises:

removing the barrier layer;

sequentially forming a gate dielectric layer and a gate conductor layer on the isolation layer;

planarizing the gate conductor layer to expose the hard mask layer;

covering a portion of the gate conductor layer with a first masking layer separate from the first stack;

etching back the gate conductor layer in the presence of the first masking layer such that a top surface of the etched-back portion of the gate conductor layer is lower than a top surface of the channel layer;

covering a portion of the gate conductor layer with a second masking layer overlapping the first stack, wherein the second masking layer completely covers the portion of the gate conductor layer covered by the first masking layer;

the gate conductor layer is etched back in the presence of the second masking layer, wherein the etching back is performed to a bottom surface of the gate conductor layer.

21. The method of claim 19, wherein forming a gate stack comprises:

removing the barrier layer;

sequentially forming a gate dielectric layer and a gate conductor layer on the isolation layer;

etching back the gate conductor layer so that the top surface of the portion of the gate conductor layer outside the recess is lower than the top surface of the channel layer;

forming dielectric side walls on the side walls of the first stack and the second stack;

forming a conductive material layer;

covering a portion of the layer of conductive material with a masking layer that overlaps the first stack;

the layer of conductive material and the gate conductor layer are etched back in the presence of the masking layer, wherein the etching back is performed to a bottom surface of the gate conductor layer.

22. The method of claim 21, wherein,

upon selective etching of the hard mask layer, the layer of conductive material is also removed, leaving a third trench in the inter-level dielectric layer,

when the first groove is filled with the conductive material, the conductive material is also filled in the third groove, thereby forming a third contact portion.

23. An electronic device comprising an integrated circuit formed by the semiconductor device according to any one of claims 1 to 13.

24. The electronic device of claim 23, further comprising: a display cooperating with the integrated circuit and a wireless transceiver cooperating with the integrated circuit.

25. The electronic device of claim 24, comprising a smartphone, a computer, a tablet, an artificial intelligence, a wearable device, or a mobile power source.

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