CN108074811A - Fin formula field effect transistor and forming method thereof - Google Patents

Abstract

A fin field effect transistor and its forming method, the forming method comprising: providing a substrate with a plurality of discrete fins on the substrate; forming a dummy gate structure across the fins, the dummy The gate structure covers part of the top and sidewall surfaces of the fin; ion implantation is performed on the fin located below the dummy gate structure; after the ion implantation, the dummy gate structure is removed; after the dummy gate structure is removed, a straddle is formed. A gate structure of the fin, the gate structure covering part of the top and sidewall surfaces of the fin.

Description

Fin field effect transistor and method of forming the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a fin field effect transistor and a forming method thereof.

Background technique

In semiconductor manufacturing, with the development of VLSI, the feature size of integrated circuits continues to decrease. In order to adapt to the reduction of feature size, the channel length of MOSFET devices is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the control ability of the gate to the channel becomes worse, and the gate voltage pinches off the channel. The difficulty is also increasing, making the phenomenon of subthreshold leakage (subthreshold leakage), the so-called short-channel effect (SCE: short-channel effects) more likely to occur.

Therefore, in order to better adapt to the reduction of feature size, the semiconductor process has gradually begun to transition from planar MOSFET transistors to three-dimensional three-dimensional transistors with higher power efficiency, such as Fin Field Effect Transistors (FinFETs). The gate of the FinFET can control the ultra-thin body (fin) from at least two sides. Compared with planar MOSFET devices, the control ability of the gate to the channel is stronger, so that the short channel effect can be well suppressed.

However, the electrical performance of the fin field effect transistor formed in the prior art still needs to be improved.

Contents of the invention

The problem to be solved by the present invention is to provide a fin field effect transistor and its forming method, so as to improve the electrical performance of the fin field effect transistor.

In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, comprising: providing a substrate having a plurality of discrete fins; forming a dummy gate structure across the fins, The dummy gate structure covers part of the top and sidewall surfaces of the fins; ion implantation is performed on the fins below the dummy gate structure; after the ion implantation, the dummy gate structure is removed; after the dummy gate structure is removed, A gate structure is formed across the fin, the gate structure covering a portion of the top and sidewall surfaces of the fin.

Optionally, the step of performing ion implantation on the fin includes: performing ion implantation on the fin along a direction perpendicular to the surface of the substrate.

Optionally, the step of performing ion implantation on the fin is ion implantation for adjusting the threshold voltage of the fin field effect transistor.

Optionally, the fin field effect transistor is an N-type transistor, and in the step of performing ion implantation, B ion implantation is performed on the fin; or, the fin field effect transistor is a P-type transistor, so In the step of performing ion implantation, perform P ion or As ion implantation on the fin.

Optionally, the step of performing ion implantation on the fin portion includes: performing multiple ion implantation on the fin portion, and the multiple ion implantation is to perform ion implantation on different positions of the fin portion perpendicular to the direction of the substrate surface. injection.

Optionally, the forming method further includes: after providing the substrate and before forming the dummy gate structure, forming an isolation layer on the substrate between the fins, wherein the fins higher than the top surface of the isolation layer are The first part of the fin; the step of performing ion implantation on the fin includes: performing the first ion implantation on the top of the first part of the fin, and performing the second ion implantation on the bottom of the first part of the fin.

Optionally, the step of performing the first ion implantation includes: performing the first ion implantation at a place 100-300 Angstroms lower than the top surface of the first part of the fin; the step of performing the second ion implantation includes: The second ion implantation is performed on the first part of the fin at 100-300 Angstroms on the top surface of the isolation layer.

Optionally, the fin field effect transistor is an N-type transistor, the ion source of the first ion implantation is BF ₂ , the energy range is 2-35keV, and the dose range is 1.0E13-5.0E14atm/cm ² ; the The ion source of the second ion implantation is B, the energy range is 1-15keV, and the dose range is 1.0E13-5.0E14atm/cm ² .

Optionally, the fin field effect transistor is a P-type transistor, the ion source of the first ion implantation is P, the energy range is 2-25keV, and the dose range is 1.0E13-5.0E14atm/cm ² ; The ion source of the two-ion implantation is As, the energy range is 5-40keV, and the dose range is 1.0E13-5.0E14atm/cm ² .

Optionally, the forming method further includes: after forming the dummy gate structure and before performing ion implantation, forming source-drain doped regions in the fins on both sides of the dummy gate structure.

Optionally, the forming method further includes: after forming the dummy gate structure and before forming the source-drain doped region, performing lightly doped ion implantation on the fins on both sides of the dummy gate structure to form light a doped region; performing a first annealing process on the lightly doped region.

Optionally, the first annealing process is nitrogen annealing, spike annealing or laser annealing.

Optionally, the forming method further includes: after performing ion implantation on the fin and before removing the dummy gate structure, performing a second annealing process to activate the source-drain doped region and the fin below the dummy gate structure ions in .

Optionally, the step of performing the second annealing process includes: performing the second annealing process by one or more of spike annealing and laser annealing.

Optionally, the second annealing process is spike annealing, and the process temperature of the spike annealing is 950-1100° C.; or, the second annealing process is laser annealing, and the process temperature of the laser annealing is 1150-1300° C. ℃.

Correspondingly, the present invention also provides a fin field effect transistor, comprising: a substrate with a plurality of discrete fins; a dummy gate structure across the fins, the dummy gate structure covering Part of the top and sidewall surfaces of the fin; wherein, there are dopant ions in the fin below the dummy gate structure, and the dopant ions are formed by performing ion implantation on the fin below the dummy gate structure form.

Optionally, the dopant ions are used to adjust the threshold voltage of the FinFET.

Optionally, the fin field effect transistor is an N-type transistor, and the dopant ions are B ions; or, the fin field effect transistor is a P-type transistor, and the dopant ions are P ions or As ions .

Optionally, the dopant ions are formed by performing multiple ion implantations on the fins; wherein, the multiple ion implantations are performed on different positions of the fins in a direction perpendicular to the substrate surface Ion Implantation.

Optionally, the FinFET further includes: an isolation layer located on the substrate between adjacent fins, wherein the fin higher than the top surface of the isolation layer is a first part of the fin; The doping ions are formed by performing a first ion implantation on the top of the first part of the fin, and performing a second ion implantation on the bottom of the first part of the fin.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming a fin field effect transistor provided by the present invention, after the dummy gate structure across the fin is formed, ion implantation is performed on the fin below the dummy gate structure, because the dummy gate structure covers the fin part of the top and sidewall surfaces, so during the ion implantation process of the fins below the dummy gate structure, the dummy gate structure can protect the fins on the one hand, reducing the impact of the fins on ion implantation and Damage suffered in other semiconductor processes; on the other hand, the dummy gate structure can also reduce the outward diffusion of dopant ions in the fin through lattice defects such as interstitial atoms and vacancies, thereby reducing the diffusion of dopant ions in the fin. dose loss, and the dummy gate structure can also reduce fin damage caused by ion implantation, thereby improving the electrical performance of the FinFET.

In addition, in the process of performing ion implantation on the fin, ion implantation will also be performed on the dummy gate structure. Since the dummy gate structure has the same dopant ions as the fin, the gap between the inside of the fin and the outside of the fin is reduced. The difference in concentration of dopant ions reduces the outward diffusion of dopant ions in the fin, thereby reducing the dose loss of dopant ions in the fin; and the dopant ions in the dummy gate structure will also diffuse into the fin , so as to increase the concentration of dopant ions in the fin portion, thereby improving the electrical performance of the fin field effect transistor.

In an optional solution, ion implantation is performed on the fin along a direction perpendicular to the surface of the substrate, which can avoid the shadow effect (shadow effect) caused by the protruding fin and prevent effective and accurate ion implantation on the fin. Implantation, thereby improving the electrical performance of the transistor.

In an optional solution, multiple ion implantations are performed on the fin, and the multiple ion implantations are performed on different positions of the fin perpendicular to the surface of the substrate. Through multiple ion implantation, the amount of ion implantation in the fin can be increased, thereby increasing the concentration of dopant ions, thereby reducing the problem of difficulty in adjusting the threshold voltage of the transistor caused by the dose loss of dopant ions, and improving the efficiency of the transistor. Electrical properties of transistors. In addition, since the multiple ion implantations are performed on different positions of the fin portion perpendicular to the substrate surface, the uniformity of the distribution of dopant ions in the fin portion can be improved, so that the transistor can be better adjusted by doping ions. The threshold voltage of the transistor improves the electrical performance of the transistor.

In an optional solution, after the dummy gate structure is formed, source and drain doped regions are formed in the fins on both sides of the dummy gate structure, and then ion implantation is performed on the fins, and then a second annealing process is performed, so as to Activating the ion implantation and the ions in the source and drain doping regions. However, the existing technical solution is to perform an annealing process on the source-drain doped region after forming the source-drain doped region, then perform ion implantation on the fin, and then perform an annealing process on the fin. deal with. Compared with the existing technical solution, the present invention reduces one annealing process, thereby reducing the thermal budget of transistor manufacturing, saving energy, simplifying the process flow, and further reducing the manufacturing cost of the transistor. In addition, the technical solution of the present invention reduces the thermal budget of the transistor, and less thermal budget is difficult to cause degradation of device performance, thereby improving the electrical performance and stability of the transistor.

The present invention provides a Fin Field Effect Transistor, the Fin Field Effect Transistor has dopant ions in the fin below the dummy gate structure, and the dopant ions are obtained by conducting the fin located under the dummy gate structure formed by ion implantation; therefore, on the one hand, the dummy gate structure can protect the fins during the formation of the dopant ions, reducing the possibility of damage to the fins; on the other hand, the dummy gate The structure can reduce the probability of outward diffusion of dopant ions in the fin through lattice defects such as interstitial atoms and vacancies, thereby reducing the dose loss of dopant ions in the fin, thereby improving the fin field effect Electrical properties of transistors.

Description of drawings

1 to 4 are structural schematic diagrams corresponding to each step of a fin field effect transistor forming method;

5 to 15 are structural schematic diagrams corresponding to each step of an embodiment of the method for forming a fin field effect transistor according to the present invention.

Detailed ways

It can be seen from the background art that the electrical performance of the fin field effect transistor formed in the prior art still needs to be improved. Combined with the manufacturing method of the prior art, the reasons for the poor electrical performance of the fin field effect transistor are analyzed.

Referring to FIG. 1 to FIG. 4 , there are shown schematic structural diagrams corresponding to each step of a method for forming a fin field effect transistor.

Referring to FIG. 1 , a substrate 10 having a plurality of discrete fins 11 thereon is provided. The step of providing the substrate 10 includes: providing a substrate (not shown); forming a hard mask layer 12 on the substrate; using the hard mask layer 12 as a mask, etching the substrate to form a substrate A bottom 10 and a plurality of discrete fins 11 located on the substrate 10 .

Referring to FIG. 2 , an isolation layer 13 is formed on the substrate 10 between the fins 11 , the top surface of the isolation layer 13 is lower than the top surface of the fins 11 .

Referring to FIG. 3, the hard mask layer 12 (refer to FIG. 2) is removed.

Referring to FIG. 4 , a sacrificial layer 14 is formed on the sidewall and top surface of the fin portion 11 ; ion implantation 15 is performed on the fin portion 11 .

In the prior art method for forming a fin field effect transistor, a sacrificial layer 14 is formed on the sidewall and top surface of the fin portion 11 , and then ion implantation 15 is performed on the fin portion 11 . The sacrificial layer 14 can protect the fins in the step of ion implantation 15, thereby reducing the damage of the fins 11. However, the sacrificial layer 14 usually has lattice defects such as interstitial atoms and vacancies, which will cause fins The dopant ions in 11 diffuse through the interstitial atoms, vacancies and other lattice defects, resulting in a dose loss of the dopant ions in the fin 11 , which in turn leads to poor electrical performance of the formed FinFET.

In order to solve the technical problem, the present invention provides a method for forming a fin field effect transistor, comprising: providing a substrate with a plurality of discrete fins; forming a dummy gate across the fins structure, the dummy gate structure covers part of the top and sidewall surfaces of the fin; ion implantation is performed on the fin located below the dummy gate structure; after the ion implantation, the dummy gate structure is removed; the dummy gate structure is removed Afterwards, a gate structure is formed across the fin, and the gate structure covers part of the top and sidewall surfaces of the fin.

In the present invention, after forming the dummy gate structure across the fin, ion implantation is performed on the fin below the dummy gate structure. Since the dummy gate structure covers part of the top and side wall surfaces of the fin, the During the ion implantation process of the fins under the dummy gate structure, the dummy gate structure can protect the fins on the one hand and reduce the damage to the fins during ion implantation and other semiconductor processes; on the other hand , the dummy gate structure can also reduce the outward diffusion of dopant ions in the fin through lattice defects such as interstitial atoms and vacancies, thereby reducing the dose loss (dose loss) of dopant ions in the fin, while the dummy gate structure It can also reduce the fin damage caused by ion implantation, thereby improving the electrical performance of the fin field effect transistor.

In addition, in the process of performing ion implantation on the fin, ion implantation will also be performed on the dummy gate structure. Since the dummy gate structure has the same dopant ions as the fin, the gap between the inside of the fin and the outside of the fin is reduced. The difference in concentration of dopant ions reduces the outward diffusion of dopant ions in the fin, thereby reducing the dose loss of dopant ions in the fin; and the dopant ions in the dummy gate structure will also diffuse into the fin , so as to increase the concentration of dopant ions in the fin portion, thereby improving the electrical performance of the fin field effect transistor.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

5 to 15 are schematic structural diagrams corresponding to each step of an embodiment of a method for forming a fin field effect transistor. In this embodiment, it is taken that the formed FinFET is a PMOS device as an example. However, it should be noted that the forming method of the present invention can also be used in other semiconductor devices such as NMOS and CMOS.

Referring to FIGS. 5 and 6 , a substrate 100 having a plurality of discrete fins 110 thereon is provided.

The substrate 100 is used to provide an operating platform for subsequent semiconductor processes. In this embodiment, the substrate 100 only includes a region for forming a P-type device.

In other embodiments, the substrate may include only regions for forming N-type devices; or the substrate may include N-type device regions for forming N-type devices and P-type devices for forming P-type devices. A device region, the N-type device region is adjacent to or separated from the P-type device region.

Specifically, the step of forming the substrate 100 and the fin portion 110 includes: providing a base (not shown), forming a first hard mask layer 120 on the base; using the first hard mask layer 120 as mask, etch the initial base to form several discrete protrusions; the protrusions are fins 110 , and the etched base serves as the substrate 100 .

The material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; The material of the fin portion 110 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the substrate 100 is a silicon substrate, and the material of the fins 110 is silicon.

It should be noted that, in this embodiment, the forming method further includes: after forming the fin portion 110 on the substrate 100 , on the substrate 100 between the sidewall of the fin portion 110 and the fin portion 110 A linear oxide layer (not shown) is formed.

Since the fin portion 110 is formed by etching the initial substrate, the fin portion 110 usually has protruding corners and has defects on the surface. In this embodiment, the fin portion 110 is oxidized to form a linear oxide layer. During the oxidation process, since the protruding corner portion of the fin portion 110 has a larger specific surface area, it is easier to be oxidized. After the linear oxide layer is subsequently removed, Not only the defect layer on the surface of the fin 110 is removed, but also the protruding corners are removed, so that the surface of the fin 110 is smooth, the quality of the lattice is improved, and the discharge problem at the tip of the fin 110 is reduced. Moreover, the formed linear oxide layer is also beneficial to improve the interface performance between the subsequently formed isolation layer and the fin portion 110 .

In this embodiment, since the material of the fin portion 110 is silicon, the material of the correspondingly formed linear oxide layer is silicon oxide.

It should be noted that, referring to FIG. 6 , the forming method further includes: after providing the substrate 100 , forming an isolation layer 130 on the substrate 100 between the fins 110 , wherein the top surface of the isolation layer 130 is higher than The fin 110 is the first partial fin 111 .

The isolation layer 130 is used for electrical isolation between adjacent fins 110 . In this embodiment, the material of the isolation layer 130 is silicon oxide. In other embodiments, the material of the isolation layer can be silicon nitride, silicon oxynitride, low K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or ultra-low K dielectric material (dielectric constant less than 2.5 ).

Specifically, the step of forming the isolation layer 130 includes: forming an isolation material layer (not shown) on the substrate 100, the isolation material layer is filled between adjacent fins, and the top of the isolation material layer The surface is higher than the top surface of the fin; part of the thickness of the top of the isolation material layer is removed, exposing part of the sidewall of the fin to form the isolation layer 130 .

It should be noted that after forming the isolation material layer and before removing part of the thickness of the top of the isolation material layer, the forming method further includes planarizing the top surface of the isolation material layer to improve the planarization for the subsequent semiconductor process. operating surface. Specifically, chemical mechanical grinding may be used to planarize the top surface of the isolation material layer.

It should be noted that the surface of the first mask layer 120 serves as a stop position in the planarization process, and protects the fins in the planarization process, so that the fins have good top surface properties.

It should be noted that, in the process of removing part of the thickness of the top of the isolation material layer to expose part of the sidewall of the fin to form the isolation layer, part of the linear oxide layer on the side of the fin is also removed, so that the remaining linear oxide layer The top surface of is flush with the top surface of the isolation layer 130.

Referring to FIG. 7 to FIG. 9 , schematic views perpendicular to the extending direction of the fin portion 110 are shown. A dummy gate structure is formed across the fin portion 110 , the dummy gate structure covers part of the top and sidewall surfaces of the fin portion 110 .

During the subsequent ion implantation process of the fin 110, the dummy gate structure can protect the fin 110 on the one hand and reduce the damage to the fin 110 during ion implantation and other semiconductor processes; on the other hand, The dummy gate structure can also reduce the outward diffusion of dopant ions in the fin portion 110 through lattice defects such as interstitial atoms and vacancies, thereby reducing the dose loss (dose loss) of the dopant ions in the fin portion 110, while the dummy gate The structure can also reduce subsequent damage to the fin portion 110 caused by ion implantation, thereby improving the electrical performance of the FinFET.

In addition, during the subsequent ion implantation process of the fin portion 110 , ion implantation will also be performed on the dummy gate structure, since the dummy gate structure has the same dopant ions as the fin portion 110 , thereby reducing the internal density of the fin portion 110 The concentration difference between the dopant ions outside the fin portion 110 reduces the outward diffusion of the dopant ions in the fin portion 110, thereby reducing the dose loss of the dopant ions in the fin portion 110; and the dopant ions in the dummy gate structure also It will diffuse into the fin portion 110 , thereby increasing the concentration of dopant ions in the fin portion 110 , thereby improving the electrical performance of the FinFET.

It should be noted that, referring to FIG. 7 , the forming method further includes: before the step of forming a dummy gate structure on the substrate 100, removing the first hard mask layer 120 (as shown in FIG. 6 ) to expose the top surface of the fin portion 110 .

In this embodiment, the dummy gate structure includes a dummy gate dielectric layer 140 and a dummy gate electrode layer 150 .

Specifically, the step of forming the dummy gate structure includes: forming a dummy gate dielectric layer 140 covering the fin portion 110; forming the dummy gate electrode layer 150 on the dummy gate dielectric layer 140, the dummy gate electrode The layer 150 spans the fin portion 110 and covers part of the surface of the dummy gate dielectric layer 140 on the sidewall and top of the fin portion 110 .

The material of the dummy gate dielectric layer 140 is silicon oxide. In this embodiment, the dummy gate dielectric layer 140 is formed on the sidewall and top surface of the fin portion 110 by an in-situ water vapor generation process.

The material of the dummy gate electrode layer 150 is polysilicon. Specifically, the step of forming the dummy gate electrode layer 150 includes: forming a dummy gate material layer on the substrate 100 and the dummy gate dielectric layer 140; planarizing the dummy gate material layer, and A second hard mask layer 160 is formed on the surface of the dummy gate material layer, and the second hard mask layer 160 is used to define the position and size of the dummy gate electrode layer 150; with the second hard mask layer 160 As a mask, the dummy gate material layer is etched until the surface of the substrate 100 and the dummy gate dielectric layer 140 are exposed to form the dummy gate electrode layer 150 .

It should be noted that, referring to FIG. 8 , the forming method further includes: after forming the dummy gate structure, performing lightly doped ion implantation on the fins 110 on both sides of the dummy gate structure to form lightly doped regions 170 ; performing a first annealing process 180 on the lightly doped region 170 .

The role of the lightly doped ion implantation is to form a shallow junction to suppress channel leakage current, and reduce the electric field distribution of the subsequently formed source and drain doped regions in the channel to overcome the hot carrier effect.

In this embodiment, since the transistor to be formed is a PMOS device, the ions implanted with lightly doped ions are P-type ions. Specifically, the ion implanted by the lightly doped ion is B, the energy range of the ion implantation is 1-6keV, and the dose range is 1.0E14atom/cm ² -2.0E15atom/cm ² .

It should be noted that the first annealing process 180 has a repairing effect on the dummy gate dielectric layer 140 on the fin 110, and can reduce lattice defects such as interstitial atoms and vacancies in the dummy gate dielectric layer 140, thereby reducing the number of fins 110. The dopant ions in the dummy gate dielectric layer 140 diffuse outward through lattice defects such as interstitial atoms and vacancies, which reduces the dose loss of the dopant ions in the fin portion 110, thereby improving the electrical performance of the FinFET.

In this embodiment, the first annealing treatment 180 is performed by nitrogen annealing, and the process time of the nitrogen annealing is 950-1100° C. In other embodiments, the first annealing treatment may also be performed by means of spike annealing or laser annealing.

It should be noted that, referring to FIG. 9 , the forming method further includes: after forming the doped source and drain regions, forming doped source and drain regions 190 in the fins 110 on both sides of the dummy gate structure.

The step of forming the source-drain doped region 190 includes: forming grooves in the fins 110 on both sides of the dummy gate structure; forming a stress layer in the groove, and performing original doping to form an initial source-drain doped region; performing ion doping on the initial source-drain doped region to form a source-drain doped region 190 .

In this embodiment, the transistor to be formed is a P-type device. Correspondingly, the stress layer is a "Σ" stress layer, and the material of the "Σ" stress layer is SiGe, SiB or SiGeB. The "Σ" stress layer The "shaped stress layer provides compressive stress for the channel region of the P-type device, thereby improving the carrier mobility of the P-type device.

In other embodiments, the transistor to be formed can also be an N-type device. Correspondingly, the formed stress layer is a "U"-shaped stress layer, and the material of the "U"-shaped stress layer is SiC, SiP or SiCP The "U"-shaped stress layer provides tensile stress for the channel region of the N-type device, thereby improving the carrier mobility of the N-type device.

In this embodiment, the stress layer is formed by an epitaxial growth process, and in-situ doping is performed on the stress layer during the process of epitaxial growth of the stress layer to form an initial source-drain doped region.

The ion doping of the initial source-drain doped region can heavily dope the surface of the initial source-drain doped region, thereby reducing the Schottky barrier, that is to say, reducing the transport barrier of carriers, thereby reducing the transistor contact resistance.

Referring to FIG. 10 to FIG. 13 , ion implantation is performed on the fin portion 110 located below the dummy gate structure.

It should be noted that, referring to FIG. 10 , in this embodiment, before performing ion implantation, a dielectric layer 200 is further formed on the substrate 100 between the fins 110 , and the dielectric layer 200 exposes the dummy gate structure.

The dielectric layer 200 is used to realize electrical isolation between different device layers. The material of the dielectric layer 200 includes silicon oxide, silicon nitride silicon oxynitride, low-K dielectric material or ultra-low-K dielectric material.

The step of forming the dielectric layer 200 includes: forming a dielectric material layer covering the substrate 100, the dummy gate structure and the source-drain doped region 190, the top surface of the dielectric material layer is higher than the dummy gate structure. the top surface of the gate structure; planarizing the dielectric material layer until the top surface of the dummy gate structure is exposed.

It should be noted that the second hard mask layer 160 (refer to FIG. 9 ) is removed during the planarization process.

Specifically, the dielectric material layer can be formed by means of fluid chemical vapor deposition (FCVD); and the dielectric material layer can be planarized by means of a chemical mechanical mask.

Referring to FIG. 11 and FIG. 12 , FIG. 11 and FIG. 12 are schematic structural views perpendicular to the extending direction of the fins on the basis of FIG. 10 .

In this embodiment, the step of performing ion implantation on the fin includes: performing at least one ion implantation on the fin by means of ion implantation. In this embodiment, multiple ion implantations are performed on the fin, and the multiple ion implantations are performed on different positions of the fin perpendicular to the surface of the substrate 100 .

By performing at least one ion implantation on the fin portion, the amount of ion implantation in the fin portion can be increased, thereby increasing the concentration of dopant ions, thereby reducing the problem that it is difficult to better adjust the threshold voltage of the transistor due to the loss of dopant ion dose , improving the electrical performance of the transistor. In addition, since the multiple ion implantations are performed on different positions of the fin portion perpendicular to the substrate surface, the uniformity of the distribution of dopant ions in the fin portion can be improved, thereby better adjusting the The threshold voltage of the transistor improves the electrical performance of the transistor.

Specifically, by performing ion implantation on the fin along the direction perpendicular to the surface of the substrate 100, the shadow effect (shadow effect) caused by the protruding fin can be avoided, preventing effective and accurate ion implantation of the fin. , thereby improving the electrical performance of the transistor. In other embodiments, the fins may also be doped in a direction with a smaller angle (less than 5°) with the normal line of the substrate surface, which can also reduce the occurrence probability of ion implantation shadow effects.

In this embodiment, the ion implantation step is ion implantation for adjusting the threshold voltage of the fin field effect transistor, therefore, the ion doping the fin portion is opposite to the type of the transistor to be formed.

Specifically, a first ion implantation 210 is performed on the top of the first part of the fin portion 111 (refer to FIG. 11 ). In this embodiment, the step of performing the first ion implantation 210 includes: performing the first ion implantation 210 at a place 100-300 angstroms lower than the top surface of the first part of the fin 111 .

Since the transistor to be formed in this embodiment is a P-type transistor, the fin portion 110 is implanted with P ions or As ions. Specifically, the ion source of the first ion implantation 210 is P, the energy range is 2-25keV, and the dose range is 1.0E13-5.0E14atm/cm ² .

A second ion implantation 220 is performed on the bottom of the first partial fin portion 111 (refer to FIG. 12 ). In this embodiment, the step of performing the second ion implantation 220 includes: performing the second ion implantation 220 at a place 100-300 angstroms higher than the top surface of the isolation layer 130 .

Specifically, the ion source of the second ion implantation 220 is As, the energy range is 5-40keV, and the dose range is 1.0E13-5.0E14atm/cm ² .

In other embodiments, the transistor to be formed may be an N-type transistor, so B ion implantation is performed on the fin. Specifically, the ion source of the first ion implantation is BF ₂ , the energy range is 2-35keV, and the dose range is 1.0E13-5.0E14atm/cm ² ; the ion source of the second ion implantation is B, and the energy range is 1-15keV, the dose range is 1.0E13-5.0E14atm/cm ² .

In other embodiments, the transistor to be formed may also include an N-type device region and a P-type device region. Correspondingly, the fins of the N-type device region and the P-type device region are respectively subjected to first ion implantation and second For ion implantation, the specific process parameters are as described above, and will not be repeated here.

It should be noted that, referring to FIG. 13 , the forming method further includes: after performing ion implantation on the fin portion, performing a second annealing process 230 to activate the ion implantation and ions in the source and drain doped regions.

In this embodiment, after forming the source and drain doped regions and performing ion implantation on the fin, a second annealing process 230 is performed to activate the ion implantation and the ions in the source and drain doped regions. However, the existing technical solution is to perform an annealing process on the source-drain doped region after forming the source-drain doped region, then perform ion implantation on the fin, and then perform an annealing process on the fin. deal with. Compared with the existing technical solution, the technical solution of this embodiment reduces one annealing process, thereby reducing the thermal budget of transistor manufacturing, saving energy, and simplifying the process flow, thereby reducing the manufacturing cost of the transistor. In addition, the technical solution of this embodiment improves the electrical performance and stability of the transistor because the thermal budget of the transistor is reduced, and a small thermal budget is unlikely to cause degradation of device performance.

The step of performing the second annealing process 230 includes: performing the second annealing process 230 by one or more of spike annealing and laser annealing.

The annealing temperature of the second annealing process 230 should neither be too low nor too high. If the annealing temperature of the second annealing process 230 is too low, it is difficult to activate the ions in the ion implantation and source-drain doped regions; if the annealing temperature of the second annealing process 230 is too high, it will cause the The dopant ions in the fins have too strong diffusion ability, which easily causes the dose loss of the dopant ions in the fins, resulting in poor electrical performance of the transistor.

Therefore, in this embodiment, the second annealing process 230 is performed by means of spike annealing, and the process temperature of the peak annealing is 950-1100°C; or the second annealing process is performed by means of laser annealing . Specifically, the process temperature of the laser annealing is 1150-1300°C.

Referring to FIG. 14 , a schematic view along the extending direction of the fin is shown. After the ion implantation, the dummy gate structure is removed.

Specifically, the step of removing the dummy gate structure includes: removing the dummy gate structure, and forming an opening 240 in the dielectric layer 200 .

The opening 240 provides a space for the subsequent formation of the gate structure.

In this embodiment, the substrate 100 is used to form a core device; correspondingly, the step of removing the dummy gate structure includes: etching and removing the dummy gate electrode layer 150 (as shown in FIG. 10 ) and the dummy gate dielectric layer 140 (as shown in FIG. 10 ), and an opening 240 exposing the fin portion 110 is formed in the dielectric layer 200 .

In other embodiments, the substrate can also be used to form peripheral devices (for example: input/output devices), correspondingly, in the step of removing the dummy gate structure, only the dummy gate electrode layer is removed, and in the An opening exposing the dummy gate dielectric layer is formed in the dielectric layer, and the dummy gate dielectric layer is a part of the peripheral device gate dielectric layer.

It should be noted that, in this embodiment, during the ion implantation process of the fin portion 110, ion implantation is also performed on the dummy gate structure, but since the dose of the ion implantation is relatively small, the The ion implantation does not increase the difficulty of removing the dummy gate structure, and has good compatibility with the removal process of the dummy gate structure in the prior art.

In this embodiment, the dummy gate structure is etched and removed by using a dry etching process. In other embodiments, the dummy gate structure may also be etched and removed by using a wet etching process or a combination of a dry etching process and a wet etching process.

Referring to FIG. 15 , after removing the dummy gate structure, a gate structure across the fin 110 is formed, and the gate structure covers part of the top and sidewall surfaces of the fin 110 . Correspondingly, a gate structure 250 is formed in the opening 240 (refer to FIG. 14 ).

In this embodiment, the gate structure 250 is a metal gate structure. Specifically, the step of forming the metal gate structure includes: forming a gate dielectric film (not shown) on the bottom and side walls of the opening 240, and the gate dielectric film also covers the top of the dielectric layer 200; A work function film (not shown) is formed on the gate dielectric film; after the work function film is formed, a metal film (not shown) filling the opening 240 is formed, and the top of the metal film is higher than the dielectric layer 200; grinding and removing the metal film higher than the top of the dielectric layer 200 to form a metal layer 260; and grinding and removing the work function film and gate dielectric film higher than the top of the dielectric layer 200 to form a and the gate dielectric layer 270 on the sidewall, and the work function layer 280 on the gate dielectric layer 270 .

In this embodiment, the fin field effect transistor to be formed is a PMOS device, correspondingly, the work function layer 280 is a P-type work function material, and the work function range of the P-type work function material is 5.1ev to 5.5ev, for example , 5.2ev, 5.3ev or 5.4ev. The work function layer 280 is a single layer structure or a stacked layer structure, and the material of the work function layer includes one or more of Ta, TiN, TaN, TaSiN and TiSiN. In this embodiment, the material of the work function layer 280 is TiN.

In other embodiments, the fin field effect transistor to be formed can also be an NMOS device, the work function layer is an N-type work function material, and the work function of the N-type work function material ranges from 3.9ev to 4.5ev, for example, 4ev , 4.1ev or 4.3ev. The work function layer is a single-layer structure or a stacked layer structure, and the material of the work function layer includes one or more of TiAl, TaAlN, TiAlN, MoN, TaCN and AlN.

The material of the gate dielectric layer 270 is a high-k gate dielectric material, wherein the high-k gate dielectric material refers to a gate dielectric material with a relative permittivity greater than that of silicon oxide, and the high-k gate dielectric material can be HfO _2. HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO ₂ or Al ₂ O ₃ . In this embodiment, the material of the gate dielectric layer 270 is HfO ₂ .

In this embodiment, the material of the metal layer 260 is W. In other embodiments, the material of the metal layer may also be Al, Cu, Ag, Au, Pt, Ni or Ti.

In other embodiments, the substrate can also be used to form peripheral devices (for example: input/output devices), and in the step of removing the dummy gate structure, the dummy gate dielectric layer at the bottom of the opening is retained; correspondingly , in the step of forming the gate dielectric layer, the gate dielectric layer is formed on the dummy gate dielectric layer and on sidewalls of the opening.

In the method for forming a fin field effect transistor provided in this embodiment, after forming the dummy gate structure across the fin, ion implantation is performed on the fin below the dummy gate structure, because the dummy gate structure covers the fin Part of the top and sidewall surface of the part, so during the ion implantation process of the fin under the dummy gate structure, the dummy gate structure can protect the fin on the one hand and reduce the impact of the fin on the ion implantation. and other damages in the semiconductor process; on the other hand, the dummy gate structure can also reduce the outward diffusion of dopant ions in the fin through lattice defects such as interstitial atoms and vacancies, thereby reducing the amount of dopant ions in the fin. dose loss, and the dummy gate structure can also reduce fin damage caused by ion implantation, thereby improving the electrical performance of the FinFET.

In addition, in the process of performing ion implantation on the fin, ion implantation will also be performed on the dummy gate structure. Since the dummy gate structure has the same dopant ions as the fin, the gap between the inside of the fin and the outside of the fin is reduced. The difference in concentration of dopant ions reduces the outward diffusion of dopant ions in the fin, thereby reducing the dose loss of dopant ions in the fin; and the dopant ions in the dummy gate structure will also diffuse into the fin , so as to increase the concentration of dopant ions in the fin portion, thereby improving the electrical performance of the fin field effect transistor.

Referring to FIGS. 10 to 12, a schematic structural view of an embodiment of the fin field effect transistor of the present invention is shown. FIG. 10 is a schematic structural view of a secant line along the extending direction of the fin. Schematic diagram of the structure of the extension direction secant. Correspondingly, the present invention also provides a fin field effect transistor, comprising:

A substrate 100 with a plurality of discrete fins (not shown); a dummy gate structure (not shown) across the fins, the dummy gate structure covering part of the top of the fins and sidewall surfaces; wherein, there are dopant ions in the fin below the dummy gate structure, and the dopant ions are formed by performing ion implantation on the fin below the dummy gate structure.

In this embodiment, the substrate 100 only includes a region with P-type devices. In other embodiments, the substrate may include a region with only N-type devices; or the substrate may include an N-type device region with N-type devices and a P-type device region with P-type devices, the N The P-type device region is adjacent to or separated from the P-type device region.

The material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; The material of the fin can be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or gallium indium. In this embodiment, the substrate 100 is a silicon substrate, and the material of the fins 110 is silicon.

It should be noted that, in this embodiment, the fin field effect transistor further includes: an isolation layer 130 located on the substrate 100 between adjacent fins, wherein the fins higher than the top surface of the isolation layer 130 110 is the first partial fin 111 .

The isolation layer 130 is used for electrical isolation between adjacent fins. In this embodiment, the material of the isolation layer 130 is silicon oxide. In other embodiments, the material of the isolation layer can be silicon nitride, silicon oxynitride, low K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9) or ultra-low K dielectric material (dielectric constant less than 2.5 ).

In this embodiment, the dummy gate structure is used to protect the fins during the formation of the dopant ions and reduce the possibility of damage to the fins; in addition, the dummy gate The structure can also reduce the probability of outward diffusion of dopant ions in the fin through lattice defects such as interstitial atoms and vacancies, thereby reducing the dose loss of dopant ions in the fin, which is beneficial to improve the Electrical properties of field effect transistors.

In this embodiment, the dummy gate structure includes a dummy gate dielectric layer 140 (as shown in FIG. 10 ) and a dummy gate electrode layer 150 on the dummy gate dielectric layer 140 (as shown in FIG. 10 ); The gate electrode layer 150 spans the fin and covers a part of the surface of the dummy gate dielectric layer 140 on the sidewall and top of the fin.

In this embodiment, the material of the dummy gate dielectric layer 140 is silicon oxide, and the material of the dummy gate electrode layer 150 is polysilicon.

It should be noted that the FinFET also includes: lightly doped regions 170 located in the fins on both sides of the dummy gate structure; source and drain doped regions 190 located in the fins on both sides of the dummy gate structure a dielectric layer 200 located on the substrate 100 between the fins 110 , the dielectric layer 200 exposing the dummy gate structure.

The lightly doped region 170 serves as a shallow junction to suppress channel leakage current, and reduces the electric field distribution of the source-drain doped region 190 in the channel to overcome the hot carrier effect.

In this embodiment, since the FinFET is a PMOS device, the doping ions in the lightly doped region 170 are P-type ions. Specifically, the doping ions in the lightly doped region 170 are B.

In this embodiment, the FinFET further includes a stress layer, and the source-drain doped region 190 is located in the stress layer. The fin field effect transistor is a PMOS device, so the stress layer is a "Σ" stress layer, the material of the "Σ" stress layer is SiGe, SiB or SiGeB, and the "Σ" stress layer is The channel region of the P-type device provides compressive stress, thereby improving the carrier mobility of the P-type device.

In other embodiments, for example, when the fin field effect transistor is an N-type device, correspondingly, the stress layer is a "U"-shaped stress layer, and the material of the "U"-shaped stress layer is SiC, SiP Or SiCP, the "U"-shaped stress layer provides tensile stress for the channel region of the N-type device, thereby improving the carrier mobility of the N-type device.

The dielectric layer 200 is used to realize electrical isolation between different device layers. The material of the dielectric layer 200 includes silicon oxide, silicon nitride silicon oxynitride, low-K dielectric material or ultra-low-K dielectric material.

In this embodiment, the dopant ions are used to adjust the threshold voltage of the FinFET.

Specifically, the dopant ions are formed by performing multiple ion implantations on the fins; wherein, the multiple ion implantations are performed on different positions of the fins perpendicular to the surface of the substrate 100. Ion Implantation.

Since the dopant ions are formed by performing multiple ion implantations on the fins, the concentration of dopant ions in the fins can be increased, thereby reducing the difficulty in better adjustment due to the loss of the dose of dopant ions. The problem of transistor threshold voltage further improves the electrical performance of the fin field effect transistor.

In addition, the multiple ion implantation is to perform ion implantation on different positions of the fin portion perpendicular to the surface direction of the substrate 100. On the one hand, the uniformity of the distribution of dopant ions in the fin portion can be relatively high. Thereby, it is beneficial to improve the effect of the dopant ions for adjusting the threshold voltage of the fin field effect transistor, thereby improving the electrical performance of the fin field effect transistor; A shadow effect is caused, thereby improving the formation quality of the dopant ions.

Since the dopant ions are used to adjust the threshold voltage of the FinFET, the type of the dopant ions is opposite to that of the FinFET.

In this embodiment, the FinFET is a P-type transistor, so the dopant ions are P ions or As ions. In other embodiments, for example, when the FinFET is an N-type transistor, the dopant ions are B ions.

It should be noted that the FinFET further includes an isolation layer 130, and the fin 110 higher than the top surface of the isolation layer 130 is the first part of the fin 111, so in this embodiment, the dopant ions are It is formed by performing first ion implantation on the top of the first partial fin 111 and performing second ion implantation on the bottom of the first partial fin 111 .

Specifically, the dopant ions of the first ion implantation are P ions, and the dopant ions of the second ion implantation are As ions.

In other embodiments, when the substrate includes an N-type device region and a P-type device region, correspondingly, the dopant ions of the N-type device region pass through the top of the first part of the fin of the N-type device region It is formed by performing the first ion implantation and performing the second ion implantation on the bottom of the first part of the fin of the N-type device region; similarly, the dopant ions in the P-type device region are formed by the second ion implantation of the P-type device region. The first ion implantation is performed on the top of a part of the fin, and the second ion implantation is performed on the bottom of the first part of the fin in the P-type device region.

In the fin field effect transistor described in this embodiment, there are dopant ions in the fin below the dummy gate structure of the fin field effect transistor, and the dopant ions pass through the fin located below the dummy gate structure. formed by ion implantation; therefore, on the one hand, the dummy gate structure can protect the fins during the formation of the dopant ions, reducing the possibility of damage to the fins; on the other hand, the dummy The gate structure can reduce the probability of outward diffusion of dopant ions in the fin through lattice defects such as interstitial atoms and vacancies, thereby reducing the dose loss (doseloss) of dopant ions in the fin, thereby improving the fin field Electrical properties of effect transistors.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (20)

1. a kind of forming method of fin formula field effect transistor, which is characterized in that including：

Substrate is provided, there are multiple discrete fins on the substrate；

It is developed across the pseudo- grid structure of the fin, dummy gate structure covering fin atop part and sidewall surfaces；

Ion implanting is carried out to being located at the fin below dummy gate structure；

After the ion implanting, dummy gate structure is removed；

After the pseudo- grid structure of removal, be developed across the gate structure of the fin, the gate structure covering fin atop part and Sidewall surfaces.

2. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that it is described fin is carried out from The step of son injection, includes：Ion implanting is carried out to the fin along perpendicular to substrate surface direction.

3. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that it is described fin is carried out from Son injection the step of for adjust fin formula field effect transistor threshold voltage ion implanting.

4. the forming method of fin formula field effect transistor as claimed in claim 3, which is characterized in that the fin field effect is brilliant In the step of body pipe is N-type transistor, the progress ion implanting, B ion implantings are carried out to the fin；

Alternatively, the fin formula field effect transistor is P-type transistor, in described the step of carrying out ion implanting, to the fin Carry out P ion or As ion implantings.

5. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that it is described fin is carried out from The step of son injection, includes：Multiple ion implanting is carried out to the fin, the multiple ion implanting is to fin vertical respectively Ion implanting is carried out at the different position in substrate surface direction.

6. the forming method of fin formula field effect transistor as claimed in claim 5, which is characterized in that the forming method is also wrapped It includes：After substrate is provided, is formed before pseudo- grid structure, separation layer is formed on the substrate between the fin, wherein, it is higher than The fin of separation layer top surface is first portion's fin；Described the step of carrying out ion implanting to fin, includes：To first The top of fin is divided to carry out the first ion implanting, the second ion implanting is carried out to the bottom of first portion's fin.

7. the forming method of fin formula field effect transistor as claimed in claim 6, which is characterized in that the first ion of the progress The step of injection, includes：To being less than the first ion implanting of progress at 100-300 angstroms of first portion's fin top surface；

The step of the second ion implanting of the progress, includes：To being higher than first at 100-300 angstroms of the separation layer top surface Part fin carries out the second ion implanting.

8. the forming method of fin formula field effect transistor as claimed in claim 6, which is characterized in that the fin field effect is brilliant Body pipe is N-type transistor, and the ion source of first ion implanting is BF₂, energy range 2-35keV, dosage range is 1.0E13-5.0E14atm/cm²；

The ion source of second ion implanting is B, energy range 1-15keV, dosage range 1.0E13-5.0E14atm/ cm²。

9. the forming method of fin formula field effect transistor as claimed in claim 6, which is characterized in that the fin field effect is brilliant Body pipe is P-type transistor, and the ion source of first ion implanting is P, energy range 2-25keV, and dosage range is 1.0E13-5.0E14atm/cm²；

The ion source of second ion implanting is As, energy range 5-40keV, dosage range 1.0E13- 5.0E14atm/cm²。

10. the forming method of fin formula field effect transistor as described in claim 1, which is characterized in that the forming method is also Including：After dummy gate structure is formed, before carrying out ion implanting, source is formed in the fin of dummy gate structure both sides Leak doped region.

11. the forming method of fin formula field effect transistor as claimed in claim 10, which is characterized in that the forming method is also Including：After dummy gate structure is formed, formed before the source and drain doping area, to the fins of dummy gate structure both sides into Ion implanting is lightly doped to form lightly doped district in row；

First annealing process processing is carried out to the lightly doped district.

12. the forming method of fin formula field effect transistor as claimed in claim 11, which is characterized in that first lehr attendant Skill is n 2 annealing, spike annealing or laser annealing.

13. the forming method of fin formula field effect transistor as claimed in claim 10, which is characterized in that the forming method is also Including：After carrying out ion implanting to the fin, before removing pseudo- grid structure, the second annealing process processing is carried out, with activation Ion below the source and drain doping area and pseudo- grid structure in fin.

14. the forming method of fin formula field effect transistor as claimed in claim 13, which is characterized in that the progress second is moved back The step of ignition technique processing, includes：Using the second annealing process of one or more progress in spike annealing and laser annealing mode Processing.

15. the forming method of fin formula field effect transistor as claimed in claim 14, which is characterized in that second lehr attendant Skill is spike annealing, and the technological temperature of the spike annealing is 950-1100 DEG C；

Alternatively, second annealing process is laser annealing, the technological temperature of the laser annealing is 1150-1300 DEG C.

16. a kind of fin formula field effect transistor, which is characterized in that including：

Substrate has multiple discrete fins on the substrate；

Across the pseudo- grid structure of the fin, dummy gate structure covers the atop part and sidewall surfaces of the fin；

Wherein, there are Doped ions, the Doped ions are by being located at the puppet in the fin below dummy gate structure Fin below grid structure carries out ion implanting and is formed.

17. fin formula field effect transistor as claimed in claim 16, which is characterized in that the Doped ions are described for adjusting The threshold voltage of fin formula field effect transistor.

18. fin formula field effect transistor as claimed in claim 16, which is characterized in that the fin formula field effect transistor is N Transistor npn npn, the Doped ions are B ions；

Alternatively, the fin formula field effect transistor is P-type transistor, the Doped ions are P ion or As ions.

19. fin formula field effect transistor as claimed in claim 16, which is characterized in that the Doped ions are by described Fin carries out multiple ion implanting and is formed；Wherein, the multiple ion implanting is respectively to the fin vertical in substrate table Ion implanting is carried out at the different position in face direction.

20. fin formula field effect transistor as claimed in claim 19, which is characterized in that the fin formula field effect transistor also wraps It includes：Separation layer between the adjacent fin on substrate, wherein, the fin higher than the separation layer top surface is first Part fin；

The Doped ions are to carry out the first ion implanting, to the first portion by the top to first portion's fin The bottom of fin carries out the second ion implanting and is formed.