CN108052468A - A kind of autonomous controllable pci bus controller based on FPGA - Google Patents
A kind of autonomous controllable pci bus controller based on FPGA Download PDFInfo
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- CN108052468A CN108052468A CN201711260608.8A CN201711260608A CN108052468A CN 108052468 A CN108052468 A CN 108052468A CN 201711260608 A CN201711260608 A CN 201711260608A CN 108052468 A CN108052468 A CN 108052468A
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a kind of based on the autonomous controllable pci bus controllers of FPGA, including：Local data bus module (1), parity check module (2), address command latch module (3), base address check module (4), read states module (5), write state module (6), configuration space module (7), low order address logic module (8) and interruption control module (9).The present invention realizes 32 pci bus to the logical transition of local bus, and local bus bandwidth supports 8,16 and 32, while supports 5 tunnel external interrupts.The present invention can not only realize the autonomous controllable of test bussing technique, improve reliability, can also be combined into one the interface controller of PCI test boards and data processor, reduce component number and cloth plate suqare, reduce cost, improve integrated level.
Description
Technical field
The present invention relates to a kind of pci bus controller, particularly a kind of autonomous controllable pci bus control based on FPGA
Device.
Background technology
In recent years, the CPCI to be grown up based on pci bus, i.e. Compact pci bus, with its higher transmission speed
Degree, compatible and higher reliability, is widely used in Aeronautics and Astronautics and industrial instrumentation well.
Traditional pci bus controller, mostly using PCI protocol chips, such as PCI9052, PCI9054, measuring technology should
With FPGA or dsp processor is often also needed to, to realize specific test function.Which not only adds CPCI to test plate
Component number, considerably increase cost, and the needs that user minimizes test equipment cannot be met.
Therefore, by Programmable Design technology, pci bus is controlled and is combined into one with data processor, be to realize to integrate
Change the important method of design.IP kernel that current PCI bus controller is generally provided by FPGA manufacturers is realized, as Xilinx is public
The LogiCore of the department or MegaCore of altera corp, these IP kernels are provided in a manner of black box, it is difficult to be met current
Aeronautics and Astronautics national defence requires autonomous controlling technology.
The content of the invention
Present invention aims at a kind of autonomous controllable pci bus controller based on FPGA is provided, solve tradition CPCI and survey
Test plate (panel) card interface circuit relies on foreign countries IC or IP kernel, integrated relatively low, and cannot be independently controllable the problem of.
A kind of autonomous controllable pci bus controller based on FPGA, including：Local data bus module, even-odd check mould
Block, address command latch module, base address are with checking module, read states module, write state module, configuration space module, low level
Location logic module and interruption control module.
The function of local data bus module is：According to pci bus agreement, realize data/address bus by pci bus to part
The conversion of bus.According to address command latch module decode out as a result, determine read-write operation, design data bus input interface
With data/address bus output interface, local end equipment to be facilitated to use.
The function of parity check module is：According to pci bus agreement, it is even that data are carried out to data address bus and command word
Verification.In address field the latter clock, checking signal is stablized simultaneously effective.For data segment, in data transmission is write, checking signal
In effective the latter clock stables of IRDY# and effective；And for reading in data transmission, checking signal is in the effective the latter of TRDY#
Clock stable is simultaneously effective.After PAR is effective, it is kept effectively until current data section completes the latter clock.
The function of address command latch module is：Address and command word are obtained from pci bus, address is as local bus
Address, while address and command word are checked that module checks to base address.
Base address checks that the function of module is：According to address command latch module and the information of configuration space module feedback,
Determine the address in pci bus and the legitimacy of command word；It is selected according to command word to read states module or write state module
It sends and starts order.
The function of read states module is：The command word and address information and pci bus provided according to base address inspection module
Control signal completes read operation；Read operation pattern includes：Configuration is read, memory is read and IO is read.
The function of write state module is：The command word and address information and pci bus provided according to base address inspection module
Control signal is completed write operation, is write comprising configurable write, memory and I/O write operation Three models.
The function of configuration space module is：Read states module and write state module is coordinated to complete pci bus configuration read-write, is matched somebody with somebody
Configuration information between emptying is provided by the form of parameter, and addressing space application can be completed by simply changing parameter in user
With determining for space type.
The function of low order address logic module is：By into row decoding, determining the bandwidth of bus access and low to command word
Bit address information, to realize conversion of 32 pci bus operations to 8 and 16 lower bus operations.
The function of interruption control module is：5 road bureau's portion's interrupt source interfaces are provided, can side be configured independently as by parameter
Along triggering or level triggers, interrupt control unit module record interrupt status information and control information are read for host computer, upper
Machine can also be by specifying address to be written and read to change interrupt control information.
Operating mode is divided into two parts, and a part is PCI configuration read-writes, refers to and receives host computer configuration read write command, to
Host computer feeds back the essential information of device PCI, and to host computer application addressing space size and type, the logical design of controller
Meet the needs of pattern, and record base address；Another part is user operation mode, including：IO reads and writes and memory read/write, with
And interrupt operation.
After pci bus system electrification where pci bus controller, host computer sends configuration to pci bus controller and reads
Write order first latches address information by address command latch module, and base address checks that module solves command word
Analysis and interpretation when being read and write for configuration, start read states module or write state module, and configuration space module are opened, to
Host computer feeds back pci controller basic configuration information, and records the base address of each addressing space, and base address is examined during for user writable
Look into module use.
After host computer completes configuration read-write, you can carry out user's operation to pci bus controller.During user's operation, with
Read-write operation type is put, base address checks that the command word of module is different from configuration read-write, therefore base address checks what module started
It is user's operation, base address checks that module is compared after receiving address with the address after configuration read-write, determines that host computer is visited
The space asked, and start read states machine module either write state module read states module or write state module according to pci bus
Signal provides local bus control signal, including：It reads effectively or with effect, while exports or read in data to local end.
A kind of autonomous controllable pci bus controller based on FPGA, one piece is concentrated on by cpci bus interface, user logic
In FPGA, it can not only accomplish independently controllably, to also reduce the type and quantity of component, greatly reduce component cloth plate face
Product, so as to improve the functional density of test board, for test equipment it is integrated, minimize support is provided.
Description of the drawings
A kind of autonomous controllable pci bus controller composition schematic diagrams based on FPGA of Fig. 1.
1. 2. parity check module of local data bus module, 3. address command latch module, 4. base address checks module
5. 8. low order address logic module of read states module 6. write state module, 7. configuration space module, 9. interruption control module
Specific embodiment
A kind of autonomous controllable pci bus controller based on FPGA, including：Local data bus module 1, even-odd check mould
Block 2, address command latch module 3, base address check module 4, read states module 5, write state module 6, configuration space module 7,
Low order address logic module 8 and interruption control module 9.
The function of local data bus module 1 is：According to pci bus agreement, realize data/address bus by pci bus to part
The conversion of bus.It is decoding out according to address command latch module 3 as a result, determine read-write operation, design data bus input connect
Mouth and data/address bus output interface, local end equipment to be facilitated to use.
The function of parity check module 2 is：According to pci bus agreement, data are carried out to data address bus and command word
Even parity check.In address field the latter clock, checking signal is stablized simultaneously effective.For data segment, in data transmission is write, verification letter
Number in effective the latter clock stables of IRDY# and effective；And for reading in data transmission, checking signal is effectively latter in TRDY#
A clock stable is simultaneously effective.After PAR is effective, it is kept effectively until current data section completes the latter clock.
3 function of address command latch module is：Address and command word are obtained from pci bus, address is as local bus
Address, while address and command word are checked that module 4 checks to base address.
Base address checks that 4 function of module is：According to 7 feedack of address command latch module 3 and configuration space module,
Determine the address in pci bus and the legitimacy of command word；It is selected according to command word to read states module 5 or write state module
6 send startup order.
The function of read states module 5 is：The command word and address information and PCI provided according to base address inspection module 4 is total
Line control signal completes read operation；Read operation pattern includes：Configuration is read, memory is read and IO is read.
The function of write state module 6 is：The command word and address information and PCI provided according to base address inspection module 4 is total
Line control signal completes write operation；Write operation pattern includes：Configurable write, memory are write and IO writes.
The function of configuration space module 7 is：Read states module 5 and write state module 6 is coordinated to complete pci bus configuration and read
It writes, the configuration information of configuration space is provided by the form of parameter, and access sky can be completed by simply changing parameter in user
Between application and space type determine.
8 function of low order address logic module：By to command word into row decoding, with determining bandwidth and the low level of bus access
Location information, the conversion operated with the lower bus for realizing 32 pci bus operations to 8,16.
The function of interruption control module 9 is：5 road bureau's portion's interrupt source interfaces are provided, can be configured independently as by parameter
Edging trigger or level triggers, interruption control module 9 record interrupt status information and control information, are read for host computer, on
Position machine can also be by specifying address to be written and read to change interrupt control information.
Operating mode is divided into two parts, and a part is PCI configuration read-writes, refers to and receives host computer configuration read write command, to
Host computer feeds back the essential information of device PCI, and to host computer application addressing space size and type, the logical design of controller
Meet the needs of pattern, and record base address；Another part is user operation mode, including：IO reads and writes and memory read/write, with
And interrupt operation.
After pci bus system electrification where pci bus controller, host computer sends configuration to pci bus controller and reads
Write order first latches address information by address command latch module 3, and base address checks that module 4 carries out command word
Parsing and interpretation when being read and write for configuration, start read states module 5 or write state module 6, and configuration space module 7 are opened
It puts, feeds back pci controller basic configuration information to host computer, and record the base address of each addressing space, base during for user writable
Address check module 4 uses.
After host computer completes configuration read-write, you can carry out user's operation to pci bus controller.During user's operation, with
Read-write operation type is put, base address checks that the command word of module 4 is different from configuration read-write, therefore base address checks that module 4 starts
Be user's operation, base address checks that the address that module 4 is received after being read and write with configuration behind address is compared, and determines host computer
The space of access, and start read states module 5 either 6 read states module 5 of write state module or write state module 6 according to PCI
Bus signals provide local bus control signal, including：It reads effectively or with effect, while exports or read in data to local end.
Claims (10)
1. a kind of autonomous controllable pci bus controller based on FPGA, it is characterised in that including：Local data bus module (1),
Parity check module (2), address command latch module (3), base address check module (4), read states module (5), write state mould
Block (6), configuration space module (7), low order address logic module (8) and interruption control module (9)；
Operating mode is divided into two parts, and a part is PCI configuration read-writes, refers to and receives host computer configuration read write command, to upper
Machine feeds back the essential information of device PCI, and to host computer application addressing space size and type, the logical design of controller meets
The demand of pattern, and record base address；Another part is user operation mode, including：IO reads and writes and memory read/write, Yi Jizhong
Disconnected operation；
After pci bus system electrification where pci bus controller, host computer sends configuration read-write life to pci bus controller
Order, first latches address information by address command latch module (3), and base address checks that module (4) carries out command word
Parsing and interpretation when being read and write for configuration, start read states module (5) or write state module (6), and by configuration space module
(7) it is open, pci controller basic configuration information is fed back to host computer, and the base address of each addressing space is recorded, for user writable
When base address check module (4) use；
After host computer completes configuration read-write, you can carry out user's operation to pci bus controller；During user's operation, read with configuration
Write operation type, base address checks that the command word of module (4) is different from configuration read-write, therefore base address checks that module (4) starts
Be user's operation, base address checks that the address that module (4) is received after being read and write with configuration behind address is compared, and determines upper
The space that machine accesses, and start read states module (5) either write state module (6) read states module (5) or write state module
(6) local bus control signal is provided according to pci bus signal, including：Read effectively or with effect, while to local end output or
Read in data.
2. a kind of autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that described
The function of ground data bus module (1) is：According to pci bus agreement, realize that data/address bus is turned by pci bus to local bus
It changes；According to address command latch module (3) decode out as a result, determine read-write operation, design data bus input interface sum number
According to bus output interface, local end equipment to be facilitated to use.
3. a kind of autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that described strange
The function of even parity check module (2) is：According to pci bus agreement, data even parity check is carried out to data address bus and command word；
Address field the latter clock, checking signal stabilization are simultaneously effective.For data segment, in data transmission is write, checking signal is in IRDY#
Effective the latter clock stable is simultaneously effective；And for reading in data transmission, checking signal is in the effective the latter clock stables of TRDY#
And effectively；After PAR is effective, it is kept effectively until current data section completes the latter clock.
4. a kind of autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that describedly
Location order latch module (3) function is：Obtain address and command word from pci bus, address is as local bus address, simultaneously
Address and command word are checked that module (4) checks to base address.
A kind of 5. autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that the base
Address check module (4) function is：According to address command latch module (3) and configuration space module (7) feedack, determine
The legitimacy of address and command word in pci bus；It is selected according to command word to read states module (5) or write state module
(6) send and start order.
A kind of 6. autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that the reading
The function of block of state (5) is：Command word and address information and the pci bus control provided according to base address inspection module (4)
Signal completes read operation；Read operation pattern includes：Configuration is read, memory is read and IO is read.
7. a kind of autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that described to write
The function of block of state (6) is：Command word and address information and the pci bus control provided according to base address inspection module (4)
Signal completes write operation；Write operation pattern includes：Configurable write, memory are write and IO writes.
8. a kind of autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that described to match somebody with somebody
The function of putting space module (7) is：Read states module (5) and write state module (6) is coordinated to complete pci bus configuration read-write, is matched somebody with somebody
Configuration information between emptying is provided by the form of parameter, and addressing space application can be completed by simply changing parameter in user
With determining for space type.
9. a kind of autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that described low
Bit address logic module (8) function：By into row decoding, determining the bandwidth of bus access and low order address information to command word,
To realize conversion of 32 pci bus operations to the lower bus operation of 8 or 16.
10. a kind of autonomous controllable pci bus controller based on FPGA according to claim 1, it is characterised in that described
The function of interruption control module (9) is：5 road bureau's portion's interrupt source interfaces are provided, can be configured independently as edge by parameter touches
Hair or level triggers, interruption control module (9) record interrupt status information and control information, read, host computer for host computer
It can also be by address be specified to be written and read to change interrupt control information.
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| CN201711260608.8A CN108052468A (en) | 2017-12-04 | 2017-12-04 | A kind of autonomous controllable pci bus controller based on FPGA |
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Cited By (3)
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| CN109558358A (en) * | 2018-11-16 | 2019-04-02 | 上海工程技术大学 | A kind of Real-time Data Transfer Method of pci data bus |
| CN112559402A (en) * | 2020-12-23 | 2021-03-26 | 广东高云半导体科技股份有限公司 | PCI slave interface control circuit based on FPGA and FPGA |
| CN113742269A (en) * | 2021-11-03 | 2021-12-03 | 浙江国利信安科技有限公司 | Data transmission method, processing device and medium for EPA device |
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Application publication date: 20180518 |