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CN107976700B - Stable output method of second pulse of satellite navigation receiver - Google Patents

Stable output method of second pulse of satellite navigation receiver Download PDF

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CN107976700B
CN107976700B CN201710966093.7A CN201710966093A CN107976700B CN 107976700 B CN107976700 B CN 107976700B CN 201710966093 A CN201710966093 A CN 201710966093A CN 107976700 B CN107976700 B CN 107976700B
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output
fpga
pps
pulse
atomic clock
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CN107976700A (en
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杨晚晴
李涛
任传秋
龙丽妮
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Wuhan Huazhong Tianwei Measurements And Controls Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
    • G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
    • G01S19/13—Receivers
    • G01S19/35—Constructional details or hardware or software details of the signal processing chain
    • G01S19/37—Hardware or software details of the signal processing chain

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Abstract

The invention discloses a stable output method of a satellite navigation receiver second pulse, wherein an FPGA maintains local PPS according to the frequency of a local rubidium atomic clock, the PPS output by a general satellite navigation receiver is recorded, and a TDC measures the time interval between the PPS output by the receiver and the local PPS; the FPGA transmits the measurement result to the DSP, the DSP carries out limited memory Kalman filtering processing and estimates the position of ideal second in real time, the position of ideal second is converted into control parameters of a numerical control delay line in the DSP, and the ideal second parameters are output through the numerical control delay line; and the FPGA outputs configuration parameters according to the ideal second parameters, and then the final second output is adjusted through a numerical control delay line, so that the stabilization of the second pulse is completed. The system of the invention is easy to realize, is suitable for a universal receiver and has lower cost; the output second pulse precision is better than 3ns (RMS) after the synchronization is performed for 6 h; and by using a Kalman filter for limiting memory, the system divergence caused by the non-Gaussian property of the model is effectively inhibited.

Description

Stable output method of second pulse of satellite navigation receiver
Technical Field
The invention belongs to the technical field of atomic clocks and time frequency, and particularly relates to a method for outputting a second pulse of a general satellite navigation receiver, which is used for improving the stability of the second pulse output by the receiver.
Background
The satellite navigation system provides navigation positioning and a high-precision time service means. The time service means based on satellite navigation can be roughly divided into several methods such as one-way time service, common view time transmission, satellite two-way time frequency transmission and the like.
The unidirectional time service refers to a method for determining the clock deviation of a station by observing one or more satellites at an observation station with known coordinates (or with unknown coordinates but capable of receiving more than four satellites). The time service precision is mainly related to receiver errors, satellite ephemeris errors, satellite clock errors, atmospheric correction errors and the like.
Its advantages are simple application, global coverage of time service signal and low cost of receiver. However, only 100ns time service precision under a certain confidence interval can be provided, and the requirement of high-precision application clock is difficult to meet.
The common view time transfer and the satellite two-way time frequency transfer can provide higher time synchronization precision, but the common view time transfer and the satellite two-way time frequency transfer essentially acquire clock differences of two stations, namely time synchronization, mainly realize time comparison among a few users, and have relatively higher cost.
Disclosure of Invention
The invention aims to design a pulse per second stabilizing method based on TDC _ GPX and limited memory Kalman filtering, which can be used for a general satellite navigation receiver according to the defects of the prior art.
The technical scheme adopted by the invention for solving the technical problems is as follows: a stable output method of a second pulse of a satellite navigation receiver is applied to a general satellite navigation receiver comprising an FPGA, a DSP and a TDC and comprises the following steps:
s1, the FPGA maintains local PPS according to the frequency of the local rubidium atomic clock, the PPS output by the universal satellite navigation receiver is recorded, and the TDC measures the time interval between the PPS output by the receiver and the local PPS;
s2, the FPGA transmits the measurement result to the DSP, the DSP carries out limited memory Kalman filtering processing and estimates the position of ideal second in real time, the position of ideal second is converted into the control parameter of the numerical control delay line in the DSP, and the ideal second parameter is output through the numerical control delay line;
and S3, the FPGA outputs configuration parameters according to the ideal second parameters, and then the final second output is adjusted through a numerical control delay line, so that the stabilization of the second pulse is completed.
The stable output method of the satellite navigation receiver pulse per second, wherein S1 specifically includes the following steps:
11) power-on reset, in FPGA, the second pulse signal of receiver is used to construct local PPS, so that the delay between the PPS output by receiver and local PPS is about 5us, ensuring that the direct measurement result is as
Figure 139034DEST_PATH_IMAGE001
；
12) With continuous measurement, when finding
Figure 525016DEST_PATH_IMAGE002
When the value of (2) is close to 0us or 10us, the local second pulse is moved forward or backward respectively
Figure 491704DEST_PATH_IMAGE003
Or
Figure 355755DEST_PATH_IMAGE004
To ensure that the direct measurement remains within the measurement range, wherein
Figure 842231DEST_PATH_IMAGE005
Clock period of FPGA;
13) the final output measurement is
Figure 382803DEST_PATH_IMAGE006
。
The method for stably outputting the pulse per second of the satellite navigation receiver comprises the following steps of:
21) the measured time interval is called clock difference x (t) of an atomic clock, and a second-order model is established for the clock difference x (t) according to the following steps:
Figure 118678DEST_PATH_IMAGE007
(ii) a In the formula
Figure 786419DEST_PATH_IMAGE008
Is the initial clock difference of the atomic clock,
Figure 51703DEST_PATH_IMAGE009
is the initial frequency difference of the atomic clock,
Figure 134148DEST_PATH_IMAGE010
is the linear drift of the atomic clock.
Figure 91739DEST_PATH_IMAGE011
Is a random variation component of atomic clock error;
wherein, the frequency difference of the atomic clock is represented as:
Figure 812440DEST_PATH_IMAGE012
；
the frequency shift ratio of an atomic clock is expressed as:
Figure 447077DEST_PATH_IMAGE013
；
22) aiming at the three formulas, a state transition model and an observation model of the atomic clock error Kalman filter discretization are established according to the following steps:
Figure 712141DEST_PATH_IMAGE014
Figure 203034DEST_PATH_IMAGE015
in the formula
Figure 605721DEST_PATH_IMAGE016
In order to observe the time interval, it is,
Figure 921296DEST_PATH_IMAGE017
zero mean Gaussian noise with uncorrelated samples with variance of
Figure 302468DEST_PATH_IMAGE018
。
The stable output method of the satellite navigation receiver pulse per second, wherein the establishment of the memory Kalman filtering model in S2 comprises the following steps:
31) establishing a state model for limiting the memory Kalman filtering according to the following steps:
Figure 969073DEST_PATH_IMAGE019
wherein
Figure 622121DEST_PATH_IMAGE020
；
32) An observation model is established according to the following steps:
Figure 775891DEST_PATH_IMAGE021
wherein
Figure 265647DEST_PATH_IMAGE022
；
33) Then, according to the basic kalman equation, a correction formula can be obtained:
Figure 124275DEST_PATH_IMAGE023
and the minimum predicted MSE matrix:
Figure 405782DEST_PATH_IMAGE024
and a kalman gain vector:
Figure 663326DEST_PATH_IMAGE025
Figure 467858DEST_PATH_IMAGE026
。
in the stable output method of the satellite navigation receiver second pulse, in S3, the output of the final second pulse is completed by the coarse adjustment of the FPGA and the fine adjustment of the numerical control delay line.
The stable output method of the satellite navigation receiver pulse per second comprises the steps that the FPGA adopts EP4CE115F23I7 of Altera company, the TDC adopts a TDC _ GPX chip, the DSP adopts TMS320F28335ZJZS of TI company, and the numerical control delay line adopts DS1124
The invention has the beneficial effects that:
the system of the invention is easy to realize, is suitable for a general satellite navigation receiver and has lower cost; the output second pulse precision is better than 3ns (RMS) after the synchronization is performed for 6 h; and by using a Kalman filter for limiting memory, the system divergence caused by the non-Gaussian property of the model is effectively inhibited.
Drawings
FIG. 1 is a functional block diagram of the present invention;
FIG. 2 is a software flow diagram of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1, the invention discloses a second pulse stabilization method based on TDC _ GPX and limited memory kalman filtering, which is applied to a general satellite navigation receiver comprising an FPGA, a DSP and a TDC (time to digital converter).
The method specifically comprises the following steps:
s1, the FPGA maintains local PPS (pulse per second) according to the frequency of the local rubidium atomic clock, the PPS output by the universal satellite navigation receiver is recorded, and the TDC measures the time interval between the PPS output by the receiver and the local PPS;
s2, the FPGA transmits the measurement result to the DSP, the DSP carries out limited memory Kalman filtering processing and estimates the position of ideal second in real time, the position of ideal second is converted into the control parameter of the numerical control delay line in the DSP, and the ideal second parameter is output through the numerical control delay line;
and S3, the FPGA outputs configuration parameters according to the ideal second parameters, and then the final second output is adjusted through a numerical control delay line, so that the stabilization of the second pulse is completed.
The FPGA adopts an EP4CE115F23I7 chip of Altera company, the TDC adopts a TDC _ GPX chip, the DSP adopts a TMS320F28335ZJZS chip of TI company, and the numerical control delay line adopts a DS1124 chip.
The software flow of the present invention is shown in fig. 2.
After the FPGA is initially electrified, basic initialization and local second synchronization are carried out, and a clock error measurement result is sent to the DSP in an interrupted mode. The DSP controls initialization of each part, receives interruption of the FPGA, reads clock error data to carry out limited memory Kalman filtering, and carries out boundary crossing control of the TDC, boundary crossing control of a numerical control delay line and the like. The key contents of each part are described in detail below.
1. Time interval measuring circuit
The TDC _ GPX is a high-precision time interval measuring chip produced by the German ACAM company, and has the advantages of high resolution, low power consumption, small volume and the like. The main characteristics are as follows: 1) the device comprises a plurality of measurement modes with different resolutions and measurement channels, wherein the measurement modes comprise an I mode, a G mode, an R mode and an M mode; 2) under the action of the phase-locked loop, the measurement precision is very slightly changed by external temperature and voltage; 3) with an internal retriggering mode, the measurement range can be extended.
The M-mode measurement accuracy with the highest accuracy is 10ps, but the measurement range only supports 0-10 us, so that the FPGA is required to control trigger pulses to expand the measurement range. The time interval measurement process comprises the following steps:
11) power-on reset, in FPGA, the second pulse signal of receiver is used to construct local PPS, so that the delay between the PPS output by the receiver and the local PPS is about 5us, ensuring that the direct measurement result is as follows in the measurement range of TDC _ GPX
Figure 791611DEST_PATH_IMAGE001
。
12) With continuous measurement, when finding
Figure 602442DEST_PATH_IMAGE002
When the value of (A) is close to 0us or 10us, the local pulse per second is dividedRespectively moving forwards or backwards
Figure 934066DEST_PATH_IMAGE003
Or
Figure 440658DEST_PATH_IMAGE004
To ensure that the direct measurement remains within the measurement range, wherein
Figure 552839DEST_PATH_IMAGE005
Is the clock period of the FPGA.
13) The final output measurement is
Figure 918093DEST_PATH_IMAGE006
。
2. Establishing atomic clock model
And transmitting the result of the time interval measurement to the DSP for subsequent data processing, wherein the core link is a Kalman filtering algorithm limited to be memorized, so as to estimate the position of the ideal pulse per second.
The section models the atomic clock model first, and the next section explains the realization process of the limited memory.
21) And (3) the time interval obtained by the previous measurement is called the clock difference x (t) of the atomic clock, and a second-order model is established for the clock difference x (t) according to the following steps:
Figure 822333DEST_PATH_IMAGE007
；
in the formula
Figure 912210DEST_PATH_IMAGE008
Is the initial clock difference of the atomic clock,
Figure 278732DEST_PATH_IMAGE009
is the initial frequency difference of the atomic clock,
Figure 431364DEST_PATH_IMAGE010
is the linear drift of the atomic clock.
Figure 144105DEST_PATH_IMAGE011
Is a random variation component of atomic clock error;
the frequency difference of the atomic clock can be expressed as:
Figure 314537DEST_PATH_IMAGE012
；
the frequency shift ratio of an atomic clock can be expressed as:
Figure 152043DEST_PATH_IMAGE013
；
22) aiming at the three formulas, a state transition model and an observation model of the atomic clock error Kalman filter discretization are established according to the following steps:
Figure 186995DEST_PATH_IMAGE014
Figure 144456DEST_PATH_IMAGE015
in the formula
Figure 973871DEST_PATH_IMAGE016
In order to observe the time interval, it is,
Figure 16783DEST_PATH_IMAGE017
zero mean Gaussian noise with uncorrelated samples with variance of
Figure 307956DEST_PATH_IMAGE018
。
3. Limited memory filtering
In order to reduce the influence of model errors and the like on filtering, the idea of the invention is to limit memory filtering. That is, the weight of prediction in estimation is reduced, the influence of innovation on the data is increased, and only the most recent N observations are considered when correcting the prediction amount.
According to the contents of the previous section, the state model of the system is:
Figure 667393DEST_PATH_IMAGE019
wherein
Figure 402130DEST_PATH_IMAGE020
。
The observation model is as follows:
Figure 732005DEST_PATH_IMAGE021
wherein
Figure 764552DEST_PATH_IMAGE022
。
Then, based on the basic Kalman equation
And (3) prediction:
Figure 165446DEST_PATH_IMAGE027
minimum predicted MSE matrix:
Figure 602244DEST_PATH_IMAGE028
kalman gain vector:
Figure 167218DEST_PATH_IMAGE029
and (3) correction:
Figure 613242DEST_PATH_IMAGE030
minimum MSE matrix
Figure 196539DEST_PATH_IMAGE031
Assuming that 2-N +1 points are observed first and then the 1 st point is observed, the relation can be obtained
Figure 273080DEST_PATH_IMAGE032
Figure 325349DEST_PATH_IMAGE033
Figure 301963DEST_PATH_IMAGE034
The two formulas can be obtained
Figure 959341DEST_PATH_IMAGE023
Figure 456050DEST_PATH_IMAGE025
Figure 933299DEST_PATH_IMAGE026
Figure 970394DEST_PATH_IMAGE024
The recursion flow only needs to calculate the inverse of a three-order matrix except for general multiplication and division operation, and is relatively simple and convenient to realize in a DSP. And because the operation frequency is only 1Hz, the requirement on the DSP main frequency is lower.
4. Numerical control delay line and ideal second output
The position of ideal pulse per second can be estimated through the processing, if the ideal pulse per second is directly output through the FPGA, the position is limited by the highest frequency of the system, and the output precision is difficult to guarantee. The invention adopts a numerical control delay line to make up the defect, so that the adjustment stepping reaches a sub-ns magnitude.
DS1124 is a 5V, 8 bit programmable digital control delay line derived from maxim, the device has a 3-line serial interface, and can realize multi-stage programmable delay by cascading multiple periods. The device has a nominal delay step of 0.25ns, a delay of 20ns for stage 0 and 83.75ns for stage 255. In the industrial temperature range, DS1124 has an integral nonlinearity of 3ns or the maximum deviation value to be a straight line connecting two points of 0 th order and 255 th order.
Assume that the control amount of the final output second pulse is
Figure 279015DEST_PATH_IMAGE035
And the coarse adjustment of the FPGA and the fine adjustment of the numerical control delay line are used for jointly finishing the output of the final second pulse. Middle period of FPGA is
Figure 353151DEST_PATH_IMAGE005
Then the FPGA is adjusted by the amount
Figure 38734DEST_PATH_IMAGE036
The adjustment amount of the numerical control delay line is
Figure 99094DEST_PATH_IMAGE037
。
5. Estimation accuracy analysis and actual measurement result
According to the CRLB theorem, a joint PDF (probability density function) between the observed and estimated quantities
Figure 980332DEST_PATH_IMAGE038
Satisfies the "regular" condition
Figure 490947DEST_PATH_IMAGE039
In the case of (2), any unbiased estimate
Figure 192056DEST_PATH_IMAGE040
Must satisfy
Figure 993790DEST_PATH_IMAGE041
In the case of white Gaussian noise, the observed signal is
Figure 664287DEST_PATH_IMAGE042
In which the signal pairs are clearly indicated
Figure 408121DEST_PATH_IMAGE043
The resistance to stress of (1). The likelihood function is
Figure 862105DEST_PATH_IMAGE044
Wherein N is the number of observations
Once derivation
Figure 264267DEST_PATH_IMAGE045
Second derivation
Figure 854518DEST_PATH_IMAGE046
Get the result after taking mathematical expectation
Figure 519985DEST_PATH_IMAGE047
So as to finally have
Figure 464195DEST_PATH_IMAGE048
The form of the lower limit indicates signal dependence
Figure 856999DEST_PATH_IMAGE043
The importance of (c). Rapid changes in the signal as the unknown parameters change will produce accurate estimates.
For simplifying the calculation, only scalar parameters are considered in some cases
Figure 318067DEST_PATH_IMAGE049
Then its standard deviation is
Figure 934862DEST_PATH_IMAGE050
Assuming that the derived PPS signal jitter is about 40ns (RMS), a good stabilization effect can be obtained after 100 points theoretically. However, according to the results measured by the inventor, the system can obtain an accuracy of 3ns (RMS) after being stably operated for 6h, and the difference is caused by inaccuracy of a rubidium clock model, non-gaussian noise of a receiver raw pulse per second and the like.
The above-described embodiments are merely illustrative of the principles and effects of the present invention, and some embodiments may be applied, and it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the inventive concept of the present invention, and these embodiments are within the scope of the present invention.

Claims (4)

1. A stable output method of a second pulse of a satellite navigation receiver is characterized by being applied to a general satellite navigation receiver comprising an FPGA, a DSP and a TDC and comprising the following steps:
s1, the FPGA maintains local PPS according to the frequency of the local rubidium atomic clock, the PPS output by the universal satellite navigation receiver is recorded, and the TDC measures the time interval between the PPS output by the receiver and the local PPS:
11) the FPGA adopts the pulse per second signal of the receiver to construct the local PPS, so that the delay between the PPS output by the receiver and the local PPS is 5us, and the direct measurement result is ensured to be within the measurement range of the TDC
Figure DEST_PATH_IMAGE001
；
12) With continuous measurement, when finding
Figure DEST_PATH_IMAGE002
When the value of (2) is close to 0us or 10us, the local second pulse is moved forward or backward respectively
Figure DEST_PATH_IMAGE003
Or
Figure DEST_PATH_IMAGE004
To ensure that the direct measurement remains within the measurement range, wherein
Figure DEST_PATH_IMAGE005
Clock period of FPGA;
13) the final output measurement is
Figure DEST_PATH_IMAGE006
；
S2, the FPGA transmits the measurement result to the DSP, the DSP carries out limited memory Kalman filtering processing and estimates the position of ideal second in real time, the position of ideal second is converted into the control parameter of the numerical control delay line in the DSP, and the ideal second parameter is output through the numerical control delay line:
the establishment of the discrete model of the Kalman filter of the atomic clock error comprises the following steps:
21) the measured time interval is called clock difference x (t) of an atomic clock, and a second-order model is established for the clock difference x (t) according to the following steps:
Figure DEST_PATH_IMAGE007
(ii) a In the formula
Figure DEST_PATH_IMAGE008
Is the initial clock difference of the atomic clock,
Figure DEST_PATH_IMAGE009
is the initial frequency difference of the atomic clock,
Figure DEST_PATH_IMAGE010
is the linear drift of the atomic clock and,
Figure DEST_PATH_IMAGE011
is a random variation component of atomic clock error;
wherein, the frequency difference of the atomic clock is represented as:
Figure DEST_PATH_IMAGE012
(ii) a The frequency shift ratio of an atomic clock is expressed as:
Figure DEST_PATH_IMAGE013
；
22) aiming at the three formulas, a state transition model and an observation model of the atomic clock error Kalman filter discretization are established according to the following steps:
Figure DEST_PATH_IMAGE014
Figure DEST_PATH_IMAGE015
in the formula
Figure DEST_PATH_IMAGE016
In order to observe the time interval, it is,
Figure DEST_PATH_IMAGE017
zero mean Gaussian noise with uncorrelated samples with variance of
Figure DEST_PATH_IMAGE018
；
And S3, the FPGA outputs configuration parameters according to the ideal second parameters, and then the final second output is adjusted through a numerical control delay line, so that the stabilization of the second pulse is completed.
2. The method as claimed in claim 1, wherein the step of building a kalman filter model in S2 comprises the steps of:
31) establishing a state model for limiting the memory Kalman filtering according to the following steps:
Figure DEST_PATH_IMAGE019
wherein
Figure DEST_PATH_IMAGE020
；
32) An observation model is established according to the following steps:
Figure DEST_PATH_IMAGE021
wherein
Figure DEST_PATH_IMAGE022
；
33) Then, according to the basic kalman equation, a correction formula can be obtained:
Figure DEST_PATH_IMAGE023
；
and the minimum predicted MSE matrix:
Figure DEST_PATH_IMAGE024
；
and kalman gain vector:
Figure DEST_PATH_IMAGE025
Figure DEST_PATH_IMAGE026
。
3. the method as claimed in claim 1, wherein the step S3 is performed by coarse tuning of FPGA and fine tuning of digital control delay line to complete the final pulse per second output.
4. The method as claimed in any one of claims 1 to 3, wherein the FPGA employs EP4CE115F23I7 of Altera, the TDC employs a TDC _ GPX chip, the DSP employs TMS320F28335ZJZS of TI, and the numerical control delay line employs DS 1124.
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