CN107944128B - FLASH bad block simulation verification system based on storage control FPGA - Google Patents
FLASH bad block simulation verification system based on storage control FPGA Download PDFInfo
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Abstract
The invention provides a FLASH bad block simulation verification system based on a storage control FPGA, which comprises: the system comprises an imitation EEPROM module, an imitation analog quantity telemetering receiving module, an imitation serial port telemetering receiving module, an imitation storage board module, an imitation clock, a reset module, a block protection module, an imitation auxiliary control board module and an imitation remote control instruction sending module. The method is suitable for ground simulation verification of the storage control FPGA in the satellite product. The invention can generate bad blocks at any position by changing the code simulation storage board (based on FLASH) of the simulation system, and can verify the working correctness of the storage control FPGA under various working conditions. Meanwhile, the invention can record the work flow of the bad block table, can simulate to input various remote control instructions to the storage control FPGA, receive and store the remote measurement information, and provide a closed loop simulation environment for the storage control FPGA. The invention can be used for the ground simulation verification of the storage control FPGA of various types of satellite products.
Description
Technical Field
The invention relates to a solid-state memory in a satellite product, in particular to ground simulation of a solid-state memory comprehensive processor system, which is mainly applied to the technical field related to high-capacity solid memory design, and particularly relates to a FLASH bad block simulation verification system based on a storage control FPGA.
Background
FLASH-based solid-state memories (solid-state memories) are widely used in satellite engineering as storage devices. The advantages of FLASH are that the power consumption is small, the cost is low, the data is not lost when the power is cut off, the defects are limited by the chip process, and the reliable performance in the life cycle of the FLASH can not be ensured. For this purpose, it is necessary to design a storage control FPGA to perform bad block management on the FLASH in the satellite product. However, the generation of the FLASH bad blocks of the effective storage unit in the storage board is random, so that the position of the bad blocks generated by the storage board is difficult to accurately set in the ground hardware joint test, and the hardware joint test cannot ensure the management correctness of the bad blocks of the storage control FPGA under different bad block distribution working conditions. Therefore, a FLASH bad block simulation verification system based on the storage control FPGA is needed to be designed to simulate various working conditions of bad blocks generated by a storage board, and the bad block generation position is accurately set so as to ensure the test coverage rate of the storage control FPGA. Therefore, the invention provides a FLASH bad block simulation verification system based on a storage control FPGA.
No relevant literature similar to the present invention is found at present.
Disclosure of Invention
The invention aims to provide a FLASH bad block simulation verification system based on a storage control FPGA, which aims to solve the problems of establishment and maintenance of an initial bad block table, a factory bad block table and a working bad block table in the existing storage technology of satellite engineering, and establishment of a mechanism for erasing and writing and reading FLASH in a storage board and feeding back bad block information to the storage control FPGA. In addition, the simulation system also comprises a function of outputting various remote control instructions, a reset signal and a working clock to the storage control FPGA, and the simulation auxiliary control board receives the page reading and writing state output by the storage control FPGA and outputs a readable and writable enabling signal. Particularly solves the problem that the position of a bad block of a storage plate which is difficult to control in the hardware joint test,
in order to achieve the above object, the present invention provides a FLASH bad block simulation verification system based on a storage control FPGA, which is used for providing a closed-loop working environment for the storage control FPGA and simulating a working condition of a bad block occurring in an erasing/reading process that a storage board cannot realize in ground hardware joint test, and specifically comprises:
the simulated EEPROM module comprises three EEPROMs which are respectively used for simulating an initial bad block table, a factory bad block table and a working bad block table;
the analog quantity simulating telemetering receiving module is used for receiving and recording bad block change, bad block downloading addresses, bad block total amount and read/erase address information output by the storage control FPGA;
the simulated serial port telemetering receiving module is used for receiving the telemetering information output by the storage control FPGA;
the simulated storage board module is used for simulating that the storage board receives address latch, command combination signal and address/state combination signal, feeding back the good/bad block state in the storage board to the storage control FPGA, and matching with the simulated EEPROM module to complete the detection and marking of the bad block by the storage board;
the clock imitation, reset and block protection module is used for providing a reset signal, a working clock and a working table protection signal for the storage control FPGA;
the auxiliary control board simulating module is used for receiving the read overflow mark, the page writing state and the page reading state output by the storage control FPGA and inputting a readable and writable instruction to the storage control FPGA;
and the simulated remote control instruction sending module is used for inputting a storage board writing instruction, a storage board reading instruction, a storage board stopping instruction and a bad block uploading instruction to the storage control FPGA.
Preferably, the three EEPROMs of the EEPROM-like module respectively store initial data of the initial bad block table, the factory bad block table, and the working bad block table in an initial state, and maintain the initial bad block table, the factory bad block table, and the working bad block table according to a remote control instruction received by the storage control FPGA, and simultaneously record processes of maintaining the initial bad block table, the factory bad block table, and the working bad block table, respectively.
Preferably, the remote control instruction includes reading an initial bad block table, restoring the initial bad block table, restoring a factory bad block table, injecting bad blocks, canceling bad blocks, backing up a bad block table state, downloading a complete bad block table, and recording processes of maintaining the initial bad block table, the factory bad block table and a working bad block table in files eepromm 1.dat, eepromm 2.dat and eepromm 3.dat respectively. .
Preferably, the analog quantity telemetering receiving module is further configured to receive an analog quantity output by the storage control FPGA, and record a current working state of the storage control FPGA.
Preferably, the serial port simulation telemetry receiving module is specifically configured to receive serial port telemetry and generate a record file RS422rx _ log.
Preferably, the memory board simulating module is specifically configured to receive a working clock, a feedback clock, an address latch, a command latch, a state feedback gating command combination, and an address state combination output to the memory board by the memory control FPGA, design a memory board bad block generating logic, feed back a bad block occurring in an erasing/writing process to the memory control FPGA, accurately set an address where the bad block is generated, and generate a memory board control recording file flash ctrl. By changing the Verilog code, the position of the bad block generated by the storage board can be set arbitrarily, and the test coverage rate of the storage control FPGA simulation system on the bad block management is improved.
Preferably, the clock imitation, reset and block protection module is specifically configured to provide clock, reset and block protection functions for the storage control FPGA.
Preferably, the auxiliary control board simulating module is specifically configured to receive read overflow and page read/write states output by the storage control FPGA, design related logic, and output a readable and writable control signal to the storage control FPGA.
Preferably, the simulated remote control instruction sending module is specifically configured to output various required remote control instructions to the storage control FPGA according to the requirement of the comprehensive processor.
Preferably, the system is written by using Verilog codes, and the used platform is a simulation verification tool VCS of Synopsys company, so that a closed-loop working environment is provided for the storage control FPGA and the interaction between the EEPROM and the memory board.
The invention has the following beneficial effects:
1) the unpredictability of bad block generation in a storage board (FLASH) in the ground hardware joint test is overcome. The invention can flexibly simulate the bad block generating mechanism of the storage board (FLASH) in the erasing and writing and reading processes by adjusting the FLASH model through software, and the related working process information is stored in the record file FLASH ctrl. By setting block addresses, layer addresses and page addresses at the module parameter ports, any address of a FLASH generating bad block can be simulated, and the coverage rate of the simulation system on the simulation verification of the storage control FPGA is improved.
2) The EEPROM model is realized, and the mechanisms of an initial bad block table, a factory bad block table and a working bad block table are established and maintained. In the working process of the FLASH, the bad block information fed back by the FLASH is received, the FLASH bad block information is marked in a working bad block table of the EEPROM and is recorded in a file eeprom3.dat in the form of a data file, and the FLASH bad block table maintenance process of the FPGA in the FLASH working process can be visually simulated, stored and controlled by comparing the FLASH with the FLASH ctrl.
3) In order to simulate the ground joint test system to the maximum extent, the auxiliary control board is added to be used as partial excitation of the storage control FPGA and used for receiving page reading and writing requests and providing page reading and writing enabling signals for the storage control FPGA. The invention provides a remote control instruction sending module which can send remote control instructions in any format according to the requirement of a storage control FPGA (field programmable gate array), and the applicability is expanded to storage main control systems in different satellite models, so that the spectral construction of satellite products is promoted.
4) The operation platform of the invention is a VCS platform of Synopsys company, and has stronger developability. With the continuous development and progress of satellite products, the VCS platform can synchronously carry out technology development and upgrade, and provide sustainable technical support for the ground simulation work of the satellite products.
Drawings
FIG. 1 is a system block diagram of a preferred embodiment of the present invention;
FIG. 2 is a flowchart of the method for creating a work bad block table according to the preferred embodiment of the present invention;
FIG. 3 is a flow chart of the memory board (FLASH) model operation of the preferred embodiment of the present invention.
Detailed Description
While the embodiments of the present invention will be described and illustrated in detail with reference to the accompanying drawings, it is to be understood that the invention is not limited to the specific embodiments disclosed, but is intended to cover various modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims.
For the convenience of understanding the embodiments of the present invention, the following description will be further explained by taking specific embodiments as examples with reference to the drawings, and the embodiments are not to be construed as limiting the embodiments of the present invention.
The embodiment provides a FLASH bad block simulation verification system based on a storage control FPGA, which is used for providing a closed-loop working environment for the storage control FPGA, particularly simulating the working condition of a storage board (FLASH) that a bad block appears in the erasing/reading process which cannot be realized in ground hardware joint test, and designing an EEPROM model.
As shown in fig. 1, the system specifically includes:
the simulated EEPROM module 1 comprises three EEPROMs which are respectively used for simulating an initial bad block table, a factory bad block table and a working bad block table;
the analog quantity simulating telemetering receiving module 2 is used for receiving and recording bad block change, bad block downloading addresses, bad block total amount and read/erase address information output by the storage control FPGA 8;
the simulated serial port telemetry receiving module 3 is used for receiving the telemetry information output by the storage control FPGA 8;
the imitation storage board module 4 is used for simulating a storage board (FLASH) to receive address latch, command combination signals and address/state combination signals, feeding back good/bad block states in the storage board to the storage control FPGA8, and matching with the imitation EEPROM module 1 to finish the detection and marking of bad blocks by the storage board (FLASH);
the clock imitation, reset and block protection module 5 is used for providing a reset signal, a working clock and a working table protection signal for the storage control FPGA 8;
the auxiliary control board simulating module 6 is used for receiving the read overflow mark, the page writing state and the page reading state output by the storage control FPGA8, and inputting a readable and writable instruction to the storage control FPGA;
the imitation remote control instruction sending module 7 is used for inputting a storage board writing instruction, a storage board reading instruction, a storage board stopping instruction and a bad block uploading instruction to the storage control FPGA 8.
The three EEPROMs of the emulated EEPROM module 1 respectively store the initial data of the initial bad block table, the factory bad block table, and the working bad block table in the initial state, and maintain the initial bad block table, the factory bad block table, and the working bad block table according to a remote control instruction received by the storage control FPGA8, and simultaneously record the processes of maintaining the initial bad block table, the factory bad block table, and the working bad block table, respectively. The remote control instruction received by the storage control FPGA8 specifically includes reading an initial bad block table, restoring the initial bad block table, restoring a factory bad block table, injecting bad blocks, canceling bad blocks, backing up a bad block table state, and downloading a complete bad block table, and meanwhile, the module records the processes of maintaining the initial bad block table, the factory bad block table, and the working bad block table in files eeprom1.dat, eeprom2.dat, and eeprom3.dat respectively.
Further, the simulated memory board module is specifically configured to receive a working clock, a feedback clock, an address latch, a command latch, a state feedback gating command combination, and an address state combination output to the memory board by the memory control FPGA, design a memory board bad block generation logic, feed back a bad block occurring in an erasing/writing process to the memory control FPGA, accurately set an address where the bad block is generated, and generate a memory board control record file flash ctrl. By changing the Verilog code, the position of the bad block generated by the storage board can be set arbitrarily, and the test coverage rate of the storage control FPGA simulation system on the bad block management is improved.
In a further preferred embodiment, the analog quantity telemetry receiving module is further configured to receive an analog quantity output by the storage control FPGA, and record a current working state of the storage control FPGA.
In a further preferred embodiment, the serial port simulation telemetry receiving module is specifically configured to receive serial port telemetry and generate a record file RS422rx _ log.
In a further preferred embodiment, the clock imitation, reset and block protection module is specifically configured to provide the functions of clock, reset and block protection for the storage control FPGA.
In a further preferred embodiment, the auxiliary control board simulating module is specifically configured to receive read overflow and page read/write states output by the storage control FPGA, design related logic, and output a readable and writable control signal to the storage control FPGA.
In a further preferred embodiment, the simulated remote control instruction sending module is specifically configured to output various required remote control instructions to the storage control FPGA according to the requirements of the comprehensive processor.
The system is written by using Verilog codes, and a used platform is a simulation verification tool VCS of Synopsys company and provides a closed-loop working environment for the storage control FPGA and the interaction work of the EEPROM and a storage board.
The idea of implementing the system of the above embodiment is: an EEPROM simulation model is established through a Verilog language, initial bad block table, factory bad block table and work bad block table data in an original state are provided, a work bad block table is maintained in a working process of a storage board FLASH according to bad block information fed back by the FLASH, and meanwhile, various maintenance operations such as reading the initial bad block table, recovering the initial bad block table and recovering the factory bad block table can be realized by receiving a remote control instruction. A storage board FLASH simulation model is established through Verilog language, signals such as a combination command, a query pulse, address latching, command latching and the like are received, and a bad block mark is fed back to the storage control FPGA.
In order to achieve the above object, the method of the present invention mainly comprises the following steps:
step 1: firstly, an imitation EEPROM module 1, an imitation analog quantity telemetering receiving module 2, an imitation serial port telemetering receiving module 3, an imitation storage board (FLASH) module 4, an imitation clock, a reset, a block protection module 5, an imitation auxiliary control board module 6 and an imitation remote control instruction sending module 7 shown in figure 1 are constructed.
The method comprises the steps of establishing an EEPROM model by using a Verilog language, receiving feedback bad block information in FLASH work, and maintaining the three bad block tables, wherein the EEPROM model comprises original data of an initial bad block table, a factory bad block table and a work bad block table.
Step 2: referring to fig. 2, when a model of a working bad block table in the emulated EEPROM module is specifically constructed, the construction includes an initialization process and a read/write process controlled by the storage control FPGA. The meaning of the initialization process is to establish an initial bad block table, and the meaning of the read-write process is to maintain a working bad block table in the EEPROM according to the change condition of the FLASH bad block in the working process of the storage board. The range of the EEPROM address is 0-131071, the bit width of the stored data is 8 bits, and each EEPROM address corresponds to one block address in the FLASH of the storage board. And the data bit width in each EEPROM address is 8 bits, the threshold value of the bad block is judged to be 5, namely the number of '1' in the EEPROM address is more than or equal to 5, and the FLASH block corresponding to the EEPROM address is considered to be a good block. Bad blocks can be generated randomly or accurately by the Verilog language. The address range of the EEPROM is 0-131071 and corresponds to 131072 blocks in the FLASH. The maintenance process for the working bad block table is stored in the record file eeprom3. dat.
And step 3: an EEPROM simulating module is arranged to cooperate with the storage control FPGA8 to maintain the bad block information in three EEPROMs (EEPROM 11, EEPROM12 and EEPROM13 respectively) according to the remote control command. The above eeprom1.dat records the initial bad block table information, eeprom2.dat records the backup bad block table information, and eeprom3.dat records the working bad block table information. Mainly comprises the following seven operations.
(1) Establishing an initial bad block table: the imitated remote control instruction sending module sends an instruction of establishing an initial bad block table to the solid-state control FPGA, and the EEPROM11 can automatically generate the initial bad block table and store information in a file eeprom1. dat.
(2) And (3) recovering an initial bad block table: when the solid memory control FPGA is in a stop state, the simulation system sends an instruction of recovering the initial bad block table, and writes the information of the initial bad block table in the EEPROM11 into the working bad block table of the EEPROM3.
(3) And (3) restoring the backup bad block table: the emulation system writes the bad block information in EEPROM12 into the EEPROM3 working bad block table.
(4) Establishing a backup bad block table: the emulation system writes the information in the working bad block table in EEPROM13 to EEPROM2 backup bad block table.
(5) And (3) downloading a bad block table: the simulation system judges the information in the working bad block table in the EEPROM13, judges the information meeting the bad block judgment threshold value (the number of '1' in the EEPROM storage unit is less than 5) as a bad block, and downloads the corresponding bad block information through the telemetering serial port.
(6) And (4) bad block upper injection: when a certain block of a FLASH memory is considered as a bad block, the block can be directly marked as the bad block through a remote control command, namely 00H is written into a block address corresponding to the EEPROM 13.
(7) And (3) bad block cancellation: in the using process, if a certain block of the FLASH is considered to be a good block, the good block can be marked directly through a remote control command, namely the FFH is written into a block address corresponding to the EEPROM 13.
And 4, step 4: as shown in fig. 3, a memory board (FLASH) model is built. The model is characterized in that a Hamming check counting threshold value in a FLASH reading flow can be accurately set through port parameters, block addresses, layer addresses and page addresses of FLASH with bad blocks in the reading and writing flows can be accurately set, and bad block addresses can also be randomly set. The storage board (FLASH) module analyzes and stores an address combination and an instruction combination output by the FPGA and converts the address combination and the instruction combination into operations of erasing, page writing, page reading and the like. The erasing and writing are binding processes, and the current block is written while the next block is erased until a good block is erased and the good block is written. The reading process is carried out according to pages, each block comprises a plurality of pages, and whether a bad block is generated or not is judged according to Hamming check times after each block is read. The FLASH block address range is 0-131071. The operation process of the storage board (FLASH) is stored in a record file, FLASH ctrl.
In the step, a storage board (FLASH) model is established by using a Verilog language, and the position of generating a bad block (setting the block address, the layer address and the page address of the FLASH) can be accurately set at a module parameter port. According to the FLASH chip data, the way of generating bad blocks in the erasing and writing process is different from the way of generating bad blocks in the reading process. Therefore, a bad block feedback mechanism with three modes is set in the FLASH model: firstly, a bad block judgment standard in FLASH erasing is as follows: and inquiring 6 times that the ready information is not received, or when the ready information is received but the memory board feeds back a bad block, considering that the bad block exists. Secondly, reading a FLASH initial bad block table bad block judgment standard: and inquiring 1 time, if the received read factory mark is low level (bad block), considering that the bad block appears. Thirdly, reading FLASH to obtain a bad block judgment standard: and in the reading operation, after reading data of one block, judging the received Hamming verification counting result, and if the number of low-level pulses of the Hamming verification signal is greater than the threshold set by the remote control command, considering the block as a bad block.
And 5: as shown in fig. 1, serial remote control commands, including commands of a memory board (FLASH) to write, read, stop, etc., are sent according to a remote control command baud rate of 38400bps defined by a storage control FPGA.
Step 6: as shown in fig. 1, the auxiliary control board emulation logic is constructed, and a page read/write enable signal is output to the storage control FPGA.
And 7: as shown in fig. 1, the telemetry receiving module is constructed to receive and store the telemetry information output by the control FPGA, and store the telemetry information in a file RS422rx _ log.
And 8: as shown in fig. 1, reset, clock, block protection signals are constructed. When the block protection signal is at high level, the work bad block table can not be written, and a stable work table is provided for the memory board.
The set threshold value of the FLASH bad judging block and the threshold value of the Hamming checking times selected in the preferred embodiment are both selected to be 5. The method of the above embodiment is to help illustrate the composition and function of the system, and the modifications made to the system by those skilled in the art according to the above method are also included in the scope of the present invention.
The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be able to make modifications or substitutions within the technical scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. The utility model provides a FLASH bad block emulation verification system based on storage control FPGA which characterized in that for storage control FPGA provides the operational environment of closed loop to and simulate the operating mode that bad block appears in the erase/read process that the memory board can not realize in ground hardware joint survey, specifically include:
the simulated EEPROM module comprises three EEPROMs which are respectively used for simulating an initial bad block table, a factory bad block table and a working bad block table, and maintaining the initial bad block table, the factory bad block table and the working bad block table according to a remote control instruction received by the storage control FPGA;
the analog quantity simulating telemetering receiving module is used for receiving and recording bad block change, bad block downloading addresses, bad block total amount and read/erase address information output by the storage control FPGA;
the simulated serial port telemetering receiving module is used for receiving the telemetering information output by the storage control FPGA;
the simulated storage board module is used for simulating that the storage board receives address latch, command combination signal and address/state combination signal, feeding back the good/bad block state in the storage board to the storage control FPGA, and matching with the simulated EEPROM module to complete the detection and marking of the bad block by the storage board; maintaining the working bad block table in the working process of the storage board FLASH according to the bad block information fed back by the FLASH;
the clock imitation, reset and block protection module is used for providing a reset signal, a working clock and a working table protection signal for the storage control FPGA;
the auxiliary control board simulating module is used for receiving the read overflow mark, the page writing state and the page reading state output by the storage control FPGA and inputting a readable and writable instruction to the storage control FPGA;
and the simulated remote control instruction sending module is used for inputting a storage board writing instruction, a storage board reading instruction, a storage board stopping instruction and a bad block uploading instruction to the storage control FPGA.
2. The FLASH bad block simulation verification system based on the storage control FPGA of claim 1, wherein three EEPROMs of the EEPROM simulation module respectively store initial data of the initial bad block table, the factory bad block table and the working bad block table in an initial state, and maintain the initial bad block table, the factory bad block table and the working bad block table according to a remote control instruction received by the storage control FPGA, and simultaneously record processes of maintaining the initial bad block table, the factory bad block table and the working bad block table respectively.
3. The FLASH bad block simulation verification system based on storage control FPGA of claim 2, wherein the remote control instruction comprises reading an initial bad block table, restoring the initial bad block table, restoring a factory bad block table, injecting bad blocks, canceling bad blocks, backing up the state of the bad block table, downloading a complete bad block table, and recording the processes of maintaining the initial bad block table, the factory bad block table and the working bad block table in files eepromm 1.dat, eepromm 2.dat and eepromm 3.dat respectively.
4. The FLASH bad block simulation verification system based on storage control FPGA of claim 1, wherein said simulation analog telemetry receiving module is further configured to receive an analog output by the storage control FPGA and record a current working state of the storage control FPGA.
5. The FLASH bad block simulation verification system based on storage control FPGA of claim 1, wherein said simulated serial telemetry receiving module is specifically configured to receive serial telemetry and generate a record file RS422rx _ log.
6. The FLASH bad block simulation verification system based on the storage control FPGA of claim 1, wherein the simulated storage board module is specifically configured to receive a working clock, a feedback clock, an address latch, a command latch, a state feedback gating command combination, and an address state combination output by the storage control FPGA to a storage board, design a storage board bad block generation logic, feed back a bad block occurring in an erasing/reading process to the storage control FPGA, accurately set an address of the generated bad block, and generate a storage board control record file FLASH ctrl.
7. The FLASH bad block simulation verification system based on storage control FPGA of claim 1, wherein the clock emulation, reset and block protection module is specifically configured to provide clock, reset and block protection functions to the storage control FPGA.
8. The FLASH bad block simulation verification system based on the storage control FPGA of claim 1, wherein the auxiliary simulation control board module is specifically configured to receive read overflow and page read write states output by the storage control FPGA, design related logic, and output readable and writable control signals to the storage control FPGA.
9. The FLASH bad block simulation verification system based on the storage control FPGA of claim 1, wherein the simulated remote control instruction sending module is specifically configured to output various required remote control instructions to the storage control FPGA according to the requirements of the integrated processor.
10. The FLASH bad block simulation verification system based on storage control FPGA of claim 1, wherein the system is written using Verilog code, and the platform used is a simulation verification tool VCS of Synopsys, and provides a closed-loop working environment for the storage control FPGA and the EEPROM to work with the storage board.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101751328A (en) * | 2008-12-12 | 2010-06-23 | 北京中电华大电子设计有限责任公司 | Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM) |
| US8161227B1 (en) * | 2006-10-30 | 2012-04-17 | Siliconsystems, Inc. | Storage subsystem capable of programming field-programmable devices of a target computer system |
| US8898243B2 (en) * | 2013-04-08 | 2014-11-25 | Jani Turkia | Device relay control system and method |
| CN104749593A (en) * | 2013-12-31 | 2015-07-01 | 深圳航天东方红海特卫星有限公司 | Satellite delay telemetry data storing and downloading method |
-
2017
- 2017-11-21 CN CN201711167449.7A patent/CN107944128B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8161227B1 (en) * | 2006-10-30 | 2012-04-17 | Siliconsystems, Inc. | Storage subsystem capable of programming field-programmable devices of a target computer system |
| CN101751328A (en) * | 2008-12-12 | 2010-06-23 | 北京中电华大电子设计有限责任公司 | Simulation method of FLASH/electrically erasable programmable read-only memory (EEPROM) |
| US8898243B2 (en) * | 2013-04-08 | 2014-11-25 | Jani Turkia | Device relay control system and method |
| CN104749593A (en) * | 2013-12-31 | 2015-07-01 | 深圳航天东方红海特卫星有限公司 | Satellite delay telemetry data storing and downloading method |
Non-Patent Citations (2)
| Title |
|---|
| Large Capacity Airborne Waveform Recorder for UWB System Based on FPGA and Flash Array;Wang Xing 等;《2013 Third International Conference on Instrumentation, Measurement, Computer, Communication and Control》;20140623;第1309-1312页 * |
| 一种新型NAND FLASH坏块管理算法的研究与实现;乔立岩 等;《电子测量技术》;20151115;第38卷(第11期);第37-41页 * |
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