CN107832083B - Microprocessor with conditional instruction and processing method thereof - Google Patents

Abstract

A microprocessor with an instruction set architecture. The instruction set architecture defines an instruction, which includes an immediate field, which has a first part specifying a first value and a second part specifying a second value. The instruction instructs the microprocessor to perform an operation with a fixed value as one of the source operands, and the fixed value is obtained by rotating/shifting the first value based on the second value by a certain number of bits. The microprocessor includes: an instruction translator, which translates the instruction into at least one immediate ALU microinstruction, wherein the immediate ALU microinstruction is encoded in an instruction encoding method different from that defined by the instruction set architecture; and an execution pipeline, which executes the microinstruction generated by the instruction translator to generate a result defined by the instruction set architecture. The instruction translator, rather than the execution pipeline, generates a fixed value as a source operand for the immediate ALU microinstruction based on the first value and the second value for execution by the execution pipeline.

Description

Microprocessor with conditional instruction and processing method thereof

The present invention is an application entitled "Microprocessor with Conditional Instructions and Its Processing Method" with an application date of April 9, 2012 and an application number of 201610126292.2 (wherein the application date of the original application of this application is 2012 April 9 and divisional application with application number 201210102141.5).

technical field

The present invention relates to the technical field of microprocessors, and particularly to microprocessors having conditional instructions in the instruction set.

Background technique

The x86 processor architecture developed by Intel Corporation of Santa Clara, California and the advanced riscmachines (ARM) architecture developed by ARM Ltd. of Cambridge, UK are two well-known processors in the computer field. Architecture. Many computer systems using ARM or x86 processors have emerged, and the demand for such computer systems is growing rapidly. Today, the ARM architecture processing core dominates the low-power, low-cost computer market, such as mobile phones, handheld electronic products, tablet computers, network routers and hubs, and set-top boxes. For example, the main processing power of Apple's iPhone and iPad is provided by the processing core of the ARM architecture. On the other hand, x86-based processors dominate high-priced markets that require high performance, such as laptops, desktops, and servers. However, with the improvement of ARM core performance and the improvement of power consumption and cost of some x86 processors, the line between the low-priced and high-priced markets mentioned above is gradually blurred. In the mobile computing market, such as smart phones, the two architectures have begun to compete fiercely. In the laptop, desktop and server markets, expect more competition between the two architectures.

The aforementioned competitive situation creates a dilemma between computer device manufacturers and consumers, as it is impossible to determine which architecture will dominate the market, and more precisely, which architecture software developers will develop more software. For example, some consumers who purchase a large number of computer systems on a monthly or yearly basis will tend to purchase computers with the same system configuration settings based on cost-efficiency considerations, such as price concessions for large-scale purchases and simplification of system maintenance. system. However, the user groups in these large consumer entities often have various computing requirements for these computer systems with the same system configuration settings. Specifically, the needs of some users are to be able to execute programs on ARM-based processors, and the needs of other users are to be able to execute programs on x86-based processors. Execute the program on the architecture. In addition, new, unanticipated computing requirements may arise that require the use of another architecture. In these cases, some of the money invested by these large individuals becomes wasted. In another example, a user has an important application that can only be executed on the x86 architecture, so he purchases an x86 architecture computer system (and vice versa). However, subsequent versions of this application were instead developed for the ARM architecture and outperformed the original x86 version. The user will want to switch the architecture to execute the new version of the application, but unfortunately, he has invested considerable cost in the architecture he does not prefer to use. Likewise, users who originally invested in applications that could only run on the ARM architecture, but later also wanted to be able to use applications developed for the x86 architecture that were not found on the ARM architecture or better than those developed on the ARM architecture, and also will encounter such problems, and vice versa. It is worth noting that although small entities or individuals with larger amounts invested are small, the proportion of investment losses may be higher. Other examples of similar investment losses may occur in various computing markets, such as switching from an x86 architecture to an ARM architecture or vice versa. Finally, computing device manufacturers, such as OEMs, that invest significant resources to develop new products are also caught in the dilemma of this architecture choice. If the manufacturer develops and manufactures a large number of products based on the x86 or ARM architecture, and the user's demand suddenly changes, it will lead to the waste of many valuable research and development resources.

For manufacturers and consumers of computing devices, it is helpful to be able to protect their investments from the influence of which of the two architectures wins, so there is a need for a solution for system manufacturers to develop systems that allow users to run concurrently A computing device for programs of the x86 architecture and the ARM architecture.

The long-standing need to enable systems to execute programs in multiple instruction sets arises primarily from the fact that consumers will invest considerable cost in software programs that execute on older hardware, whose instruction sets are often incompatible with newer hardware. For example, the IBM 360 system Model 30 has features compatible with the IBM 1401 system to ease the pain of users switching from the 1401 system to the 360 system with higher performance and improved features. The Model 30 has the Read Only Storage (ROS) of the 360 system and the 1401 system, so that it can be used in the 1401 system if the auxiliary storage space is pre-stored with the required information. In addition, with software programs developed in high-level languages, new hardware developers have little control over software programs compiled for old hardware, and software developers have little incentive to re-compile source code for new hardware, This is especially the case when the software developer and the hardware developer are different individuals. In the article "An Architectural Framework for Supporting Heterogeneous Instruction-Set Architectures" proposed by Siberman and Ebcioglu in Computer, June 1993, No. 6, they disclose a method that implements RISC, superscalar and super long Instruction word (VLIW) architecture (hereinafter referred to as the native architecture) system to improve the execution efficiency of the existing complex instruction set (CISC) architecture (such as IBM S/390) technology, the disclosed system includes a native engine (native engine) that executes native code. engine) and the migration engine (migrant engine) that executes the object code, and can convert between the two encodings as needed according to the translation effect of the translation software translating the object bode into the native code. Please refer to US Patent No. 7,047,394 published on May 16, 2006. VanDyke et al. discloses a processor having an execution pipeline for executing program instructions of a native reduced instruction set (Tapestry), and utilizing hardware translation and The combination of software translation translates x86 program instructions into native reduced instruction set instructions. Nakada et al. proposed a heterogeneous SMT processor with front-end pipeline of ARM architecture and front-end pipeline of Fujitsu FR-V (very long instruction word) architecture, and the front-end pipeline of ARM architecture is used for irregular (irregular) Software programs (such as operating systems), while the front-end pipeline of the Fujitsu FR-V (very long instruction word) architecture is used for multimedia applications, which provides an increased queue of very long instruction words to the backend of FR-V very long instruction words front-end pipeline to maintain instructions from the front-end pipeline. Please refer to the paper published by Buchty and Weib, eds, Universitatsverlag Karlsruhe in November 2008 in First International Workshop on New Frontiers in High-performance and Hardware-aware Computing (HipHaC'08), Lake Como, Italy, (with MICRO-41) Set (ISBN 978-3-86644-298-6) for the article "OROCHI: A Multiple Instruction Set SMTProcessor". The method presented here is designed to reduce the space occupied by the entire system in a heterogeneous system-on-a-chip (SOC) device, such as the Texas Instruments OMAP applications processor, which has an ARM processor core plus an or multiple co-processors (eg TMS320, various digital signal processors, or various graphics processing units (GPUs)). These coprocessors do not share instruction execution resources, but are integrated into different processing cores on the same chip.

Software translator (software translator), or software emulator (software emulator, software simulator), dynamic binary code translator, etc., are also used to support the ability to execute software programs on processors with different architectures from the software program. . Among the popular commercial examples are the Motorola 68K-to-PowerPC emulator paired with an Apple Macintosh computer, which can execute 68K programs on a Macintosh computer with a PowerPC processor, and the subsequent PowerPC-to-PowerPC emulator. to-x86 emulator, which can execute 68K programs on a Macintosh computer with an x86 processor. Transmeta Corporation, located in Santa Clara, California, combines the core hardware of very long instruction word (VLIW) with the "translator of pure software instructions (ie CodeMorphing Software) to dynamically Compile or emulate x86 code sequences" to execute x86 code, please refer to the 2011 Wikipedia description for Transmeta <http://en.wikipedia.org/wiki/Transmeta>. Also, see US Patent No. 5,832,205, filed November 3, 1998 by Kelly et al. IBM's DAISY (Dynamic Architecture Instruction Set from Yorktown) system features a very long instruction word (VLIW) machine and dynamic binary software translation that provides 100 percent software-compatible emulation of legacy architectures. DAISY has a Virtual Machine Monitor located in ROM to parallelize and store VLIW primitives to parts of main memory not found in legacy system architectures. It is possible to avoid re-translation of these old architecture code fragments in subsequent programs. DAISY has a high-speed compiler optimization algorithm (fast compiler optimization algorithms) to improve performance. QEMU is a machine emulator with a software dynamic translator. QEMU can emulate a variety of CPUs, such as x86, PowerPC, ARM, and SPARC, on a variety of hosts, such as x86, PowerPC, ARM, SPARC, Alpha, and MIPS. Please refer to QEMU, a Fast and Portable DynamicTranslator, Fabrice Bellard, USENIX Association, FREENIX Track: 2005USENIX AnnualTechnical Conference, as its developers call "the runtime conversion of the target processor instruction execution by the dynamic translator, convert it To the main system instruction set, the resulting binary code is stored in a translation cache to facilitate repeated access....QEMU [compared to other dynamic translators] is much simpler because it only links the GNC C compiler offline (off line) generated machine code fragment". Also refer to the dissertation "ARM Instruction Set Simulation on Multi-core x86Hardware" by Lee Wang Hao of Adelaide University on June 19, 2009. Although the processing performance provided by the software translation-based solution can meet some of the multiple computing requirements, it is not sufficient for multiple users.

Static binary translation is another technique with high performance potential. However, there are technical problems with the use of binary translation techniques (such as self-modifying code, indirect branches values known only at run-time) and commercial and legal issues. Obstacles (eg: this technology may require hardware developers to cooperate with the development of channels needed to distribute new programs; potential licensing or copyright infringement risks for original program distributors).

The ARM Instruction Set Architecture (ISA) features conditional instruction execution. As stated on page A4-3 of the ARM Architecture Reference Manual: "Most ARM instructions can be executed conditionally, meaning that if the N, Z, C and V flags in the APSR satisfy the conditions, they will operate in programmer mode, memory and coprocessors will have normal effects. If these flags do not meet the conditions, the instruction will behave like a no-operation (NOP) machine instruction, and the instruction will execute until the next normal operation. Instructions, including all relevant confirmation operations for exceptions, have no other effect."

Conditional execution helps reduce the size of the instruction code and can improve performance by reducing the number of branch instructions, but instruction misprediction will come with a performance penalty. Therefore, how to efficiently execute conditional instructions, especially in the case of supporting a high microprocessor clock, is an urgent problem to be solved.

SUMMARY OF THE INVENTION

One embodiment of the present invention provides a microprocessor for executing conditional non-branch instructions. Each of the conditional non-branch instructions specifies a condition, and each of the conditional non-branch instructions instructs the microprocessor to perform an operation when the condition is satisfied, and does not execute when the condition does not satisfy the condition flag of the microprocessor the operation. The microprocessor may include: a predictor for providing a prediction about a conditional non-branch instruction; an instruction translator for: when the prediction predicts that the condition will not be satisfied, the conditional non-branch instruction translates into a no-op microinstruction with a condition code, wherein the no-op microinstruction with a condition code does nothing but cause an execution unit to start to check the prediction; and when the prediction predicts that the condition will be met, The conditional non-branch instruction is translated into a single operable microinstruction with a condition code to perform the operation unconditionally. The instruction translator translates the instructions of the x86 instruction set architecture (ISA) program and the advanced reduced instruction set machine (ARM) ISA program into microinstructions defined by the microinstruction set of the microprocessor, wherein the microinstructions are in accordance with the The way in which the instructions defined by the x86 ISA and ARM ISA instruction sets are encoded is encoded in different ways. and includes an execution pipeline including an instruction issue unit and a plurality of execution units, wherein the instruction issue unit operates to issue the single operable microinstruction with a condition code to a selected one of the multiple execution units, and the selected execution unit operates to execute the single operable microinstruction with a condition code.

Another embodiment of the present invention provides a method for executing conditional non-branch instructions using a microprocessor. Wherein, the microprocessor has an instruction translator that translates instructions of x86 instruction set architecture (ISA) programs and advanced reduced instruction set machine (ARM) ISA programs into microinstructions defined by the microinstruction set of the microprocessor , where the microinstruction is encoded in a different way than the one in which the instructions defined by the instruction sets of the x86 ISA and ARM ISA are encoded, where each conditional non-branch instruction specifies a condition, and each conditional non-branch instruction specifies a condition in which Instructs the microprocessor to perform an operation when satisfied, and does not perform the operation when the condition does not satisfy the condition flag of the microprocessor. The method includes: providing a prediction about a conditional non-branch instruction; when the prediction predicts that the condition will not be satisfied, translating the conditional non-branch instruction into a no-op microinstruction with a condition code, wherein the The no-op microinstruction does nothing but cause the execution unit to start to check the prediction; when the prediction predicts that the condition will be met, the conditional non-branch instruction is translated into a single operable microinstruction with a condition code to performing the operation unconditionally; and the instruction issue unit issues the single operable microinstruction with the condition code to a selected one of the plurality of execution units, the selected execution unit executing the single operable microinstruction with the condition code. The instruction issuing unit and the selected execution unit are part of a hardware execution pipeline of the microprocessor.

Yet another embodiment of the present invention provides a computer program product encoded on a computer-readable storage medium, comprising computer-readable program code for instructing a microprocessor to execute conditional non-branch instructions. Wherein, each conditional non-branch instruction specifies a condition. Each conditional non-branch instruction instructs the microprocessor to perform an operation when the condition is satisfied, and does not perform the operation when the condition does not satisfy the condition flag of the microprocessor. The computer-readable program code includes first program code to designate a predictor that provides prediction for a conditional non-branch instruction. The computer can read the program code and include the second program code to designate an instruction translator for translating the conditional non-branch instruction into a no-operation microinstruction when the aforementioned prediction prediction condition will not be satisfied, and in the When it is predicted that the predicted condition will be satisfied, the conditional non-branch instruction is translated into a microinstruction group composed of one or more microinstructions to unconditionally execute the operation. The computer can read the program code and include the third program code to designate an execution pipeline to execute the aforementioned non-operational microinstructions or a group of microinstructions provided by an instruction translator.

An embodiment of the present invention provides a microprocessor having an instruction set architecture. The instruction set architecture defines an instruction, the instruction includes an immediate field, the immediate field has a first part specifying a first value and a second part specifying a second value, the instruction instructs the microprocessor to perform an operation Taking a fixed value as one of the source operands, the fixed value is obtained by rotating/shifting the first value by a certain number of bits based on the second value. The microprocessor includes: an instruction translator that translates the instruction into at least one immediate ALU microinstruction, wherein the immediate ALU microinstruction is encoded in an instruction encoding manner different from that defined by the instruction set architecture; and an execution pipeline , executes microinstructions generated by the instruction translator to produce results defined by the instruction set architecture. The instruction translator, not the execution pipeline, generates the fixed value according to the first value and the second value as a source operand for the immediate ALU microinstruction for the execution pipeline to execute.

Another embodiment of the present invention provides a method performed by a microprocessor having an instruction set architecture. The instruction set architecture defines an instruction, the instruction includes an immediate field, the immediate field has a first part specifying a first value and a second part specifying a second value, the instruction instructs the microprocessor to perform an operation Taking a fixed value as one of the source operands, the fixed value is obtained by rotating/shifting the first value by a certain number of bits based on the second value. The method includes: translating the instruction into at least one immediate ALU microinstruction, wherein the immediate ALU microinstruction is encoded in an instruction encoding manner different from that defined by the instruction set architecture, wherein the translating step is performed by the microprocessor and executing microinstructions generated by the instruction translator to generate a result defined by the instruction set architecture, wherein the execution steps are performed by an execution pipeline of the microprocessor. The fixed value is generated by the instruction translator, not the execution pipeline, according to the first value and the second value as a source operand for the immediate ALU microinstruction for the execution pipeline to execute.

Another embodiment of the present invention provides a microprocessor having an instruction set architecture. The instruction set architecture defines an instruction, the instruction includes an immediate field, the immediate field has a first part specifying a first value and a second part specifying a second value, the instruction instructs the microprocessor to perform an operation Taking a fixed value as one of the source operands, the fixed value is obtained by rotating/shifting the first value by a certain number of bits based on the second value. The microprocessor includes: an instruction translator that translates the instruction into microinstructions; and an execution pipeline that executes the microinstruction generated by the instruction translator to generate a result defined by the instruction set architecture. Wherein, when a value of the immediate field falls within a predetermined value subset: the instruction translator translates the instruction into at least one immediate ALU microinstruction; the instruction translator, not the execution pipeline, according to the first generating the fixed value with the second value; and the execution pipeline executes the immediate ALU microinstruction using the fixed value generated by the instruction translator as one of the source operands. and wherein, when the value of the immediate field does not fall within the predetermined subset of values: the instruction translator translates the instruction into at least the first and second microinstructions; the execution pipeline, not the instruction translator, By executing the first microinstruction, the fixed value is generated; and the execution pipeline executes the second microinstruction by using the fixed value generated by executing the first microinstruction as one of the source operands.

Another embodiment of the present invention provides a method performed by a microprocessor having an instruction set architecture. The instruction set architecture defines an instruction, the instruction includes an immediate field, the immediate field has a first part specifying a first value and a second part specifying a second value, the instruction instructs the microprocessor to perform an operation Taking a fixed value as one of the source operands, the fixed value is obtained by rotating/shifting the first value by a certain number of bits based on the second value, the microprocessor includes an instruction translator and an execution pipeline. The method includes: using the instruction translator to confirm whether a value of the immediate field falls within a predetermined value subset; when the value of the immediate field falls within the predetermined value subset: using the instruction to translate A processor translates the instruction into at least immediate ALU microinstructions; uses the instruction translator instead of the execution pipeline to generate the fixed value based on the first and second values; and utilizes the execution pipeline to generate the fixed value from the instruction translator The fixed value is used as one of the source operands to execute the immediate ALU microinstruction. and wherein, when the value of the immediate field does not fall within the predetermined subset of values: use the instruction translator to translate the instruction into at least first and second microinstructions; use the execution pipeline instead of the instruction A translator, by executing the first microinstruction, to generate the fixed value; and by using the execution pipeline, by using the fixed value generated by executing the first microinstruction as one of the source operands, to execute the second microinstructions.

Yet another embodiment of the present invention provides a computer program product encoded in at least one computer-readable storage medium for use in a computing device. The computer program product includes computer readable program code encoded on the medium for specifying a microprocessor. The microprocessor has an instruction set architecture, and the instruction set architecture defines at least one instruction. The command includes an immediate field with a first part for specifying a first value and a second part for specifying a second value. An instruction instructs the microprocessor to perform an operation with a fixed value as one of its source operands. This fixed value is obtained by rotating/shifting the first value by a certain number of bits based on the second value. The computer-readable program code has a first program code and designates an instruction translator for translating at least one instruction into one or more micro-instructions, wherein the instruction is in an instruction encoding manner different from that defined by the instruction set architecture to encode. The computer can read program code and has a second program code designating an execution pipeline for executing microinstructions generated by an instruction translator to generate a result defined by the instruction set architecture. The instruction translator, not the execution pipeline, uses a fixed value generated according to the first and second values as a source operand of at least one microinstruction for the execution pipeline to execute.

The advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings.

Description of drawings

FIG. 1 is a block diagram of an embodiment of a microprocessor for executing x86 assembly architecture and ARM assembly architecture machine language programs according to the present invention.

FIG. 2 is a block diagram showing the hardware instruction translator of FIG. 1 in detail.

FIG. 3 is a block diagram showing the instruction formatter of FIG. 2 in detail.

FIG. 4 is a block diagram showing the execution pipeline of FIG. 1 in detail.

FIG. 5 is a block diagram showing the register file of FIG. 1 in detail.

6A and 6B are a flowchart showing the operation steps of the microprocessor of FIG. 1. FIG.

7 is a block diagram of a dual-core microprocessor of the present invention.

FIG. 8 is a block diagram of another embodiment of the microprocessor for executing x86 ISA and ARM ISA machine language programs according to the present invention.

FIG. 9 is a block diagram showing a portion of the microprocessor of FIG. 1 in detail.

10A and 10B are flowcharts showing the operation steps of the hardware instruction translator of FIG. 1 to translate a conditional ALU instruction.

FIG. 11 is a flowchart showing the operation steps of the execution unit of FIG. 4 to execute a shift microinstruction.

12A and 12B are flowcharts showing the operational steps of the execution unit of FIG. 4 to execute a conditional ALU microinstruction.

FIG. 13 is a flowchart showing the operation steps of the execution unit of FIG. 4 to execute a conditional move microinstruction.

FIGS. 14-20 are block diagrams illustrating the operational steps of the execution pipeline 112 of FIG. 1 to execute various forms of conditional ALU instructions translated in accordance with the translation operation of FIG. 10 .

21A and 21B are flowcharts showing the operation steps for the hardware instruction translator of FIG. 1 to translate the conditional ALU instruction to specify that one of the source registers is the same as the destination register.

FIGS. 22-28 are block diagrams illustrating the operational steps of the execution pipeline 112 of FIG. 1 to execute various forms of conditional ALU instructions translated in accordance with the translation operation of FIG. 21 .

FIG. 29 is a block diagram showing an embodiment of the microprocessor 100 for predicting unconditional branch instructions according to the present invention.

FIG. 30 is a block diagram illustrating an embodiment of the translation of conditional ALU instructions by the instruction translator of FIG. 29 .

FIGS. 31A and 31B are a flowchart showing an embodiment of the present invention in which the microprocessor of FIG. 29 executes a conditional ALU instruction of FIG. 30 .

FIG. 32 is a block diagram showing one embodiment of a microprocessor for processing immediate post-correction constants during translation according to the present invention.

33 is a block diagram showing an embodiment of the present invention for selectively translating an immediate operand instruction into a ROR microinstruction and an ALU microinstruction or into an immediate ALU microinstruction.

34A and 34B are flowcharts showing one embodiment of the operation of the microprocessor 100 of FIG. 32 to execute an immediate operand instruction of FIG. 33 of the present invention.

[Main component label description]

Microprocessor (processing core) 100 Instruction cache 102

Hardware Instruction Translator 104 Register File 106

memory subsystem 108 execution pipeline 112

Instruction Fetch Unit and Branch Predictor 114 ARM Program Counter (PC) Register 116

x86 Instruction Pointer (IP) Register 118

configuration register 122

ISA Instructions 124 Microinstructions 126

Results 128

instruction mode indicator 132

Fetch address 134

environment mode indicator 136

Instruction Formatter 202 Simple Instruction Interpreter (SIT) 204

Complex Instruction Translator (CIT) 206 Multiplexer (mux) 212

x86 Simple Instruction Translator 222 ARM Simple Instruction Translator 224

Micro-program counter (micro-program counter, micro-PC) 232

Microcode ROM 234

Microsequencer 236

Instruction indirection register (IIR) 235

Microtranslator 237

format ISA instructions 242

Implementing microinstructions 244

Execute microinstructions 246

select input 248

Microcode address 252

ROM address 254

ISA Directive Information 255

Pre-decoder (pre-decoder) 302

Instruction Byte Queue (IBQ) 304

Length decoders and ripple logic 306

Multiplexer queue (mux queue, MQ) 308

Multiplexer 312

Formatted instruction queue (FIQ) 314

ARM instruction set status 322

Microinstruction Queue 401

Register allocation table (RAT) 402

instruction dispatcher 404

reservation station 406

Instruction issue unit 408

Integer/branch unit 412

Media unit 414

load/store unit 416

floating point unit 418

Reorder buffer (ROB) 422

Execution unit 424 ARM specific registers 502

x86 specific registers 504 shared registers 506

Dual-core microprocessor 700 microinstruction cache 892

Condition Flag Register 926 Multiplexer 922

Flag Bus 928 Condition Flag Value 928/924

ISA Condition Flag 902 Condition Satisfied (SAT) bit 904

Preshift Carry (PSC) bit 906 Use Shift Carry (USE) bit 908

Dynamic Predictor 2932 Predictor Selector 2934

Static Predictors 2936 Dynamic Predictors 2982

Forecast selection 2984 Static forecast 2986

Historical update 2974 Misprediction 2976

ALU microinstructions 3044 Conditional move microinstructions 3046

Conditional ALU microinstructions with condition codes 3045

No-op microinstruction with condition code 3047

Opcode fields a202,a212,a222,a252,a272

Condition code fields a204,a224,a254,a274

Fields a206, a216, a256 of source registers 1 and 2

Destination register fields a208,a218,a232,a258

Field a226 of Source Register 1 Field a228 of Source Register 2

Immediate operand 3266 ROR microinstruction 3344

ALU microinstruction 3346 Immediate ALU microinstruction 3348

Opcode fields b202,b212,b222,b232

Fields b204, b214, b234 of source register 1

Field b235 of source register 2

Destination register fields b206,b216,b226,b236

Immediate field b207 immed_8 field b208,b228

rotate_imm field b209, b229 immediate-32 field b218

Detailed ways

noun definition

An instruction set defines the correspondence between a set of binary-coded values (ie, machine language instructions) and the operations performed by the microprocessor. Machine language programs are basically coded in binary, but other systems can also be used. For example, the machine language programs of some early IBM computers are ultimately expressed as physical signals with binary values of voltage levels, but they are not. Encode in decimal. Machine language instructions instruct the microprocessor to perform operations such as: add the operand in register 1 to the operand in register 2 and write the result to register 3, subtract the operand at memory address 0x12345678 by the immediate value specified by the instruction. The operand and the result are written into register 5, and the value in register 6 is shifted according to the number of bits specified by register 7. If the zero flag is set, branch to the 36 bytes after the instruction, and store the value of memory address 0xABCD0000. The value is loaded into register 8. Thus, an instruction set is a binary coded value that defines individual machine language instructions that cause the microprocessor to perform the operations it is intended to perform. It should be understood that the instruction set defines the correspondence between binary values and microprocessor operations, and does not mean that a single binary value corresponds to a single microprocessor operation. Specifically, in some instruction sets, multiple binary values may correspond to the same microprocessor operation.

The instruction set architecture (ISA), from the perspective of the microprocessor family, includes (1) the instruction set; (2) the resource set that the instructions of the instruction set can access (for example: registers and modes required for memory addressing) ; and (3) a set of exceptional events (eg, division by zero, page fault, memory protection violation, etc.) generated by the microprocessor in response to instruction execution of the instruction set. Because program writers, such as assemblers and compiler writers, want to make machine language programs for a family of microprocessors to execute, they need the ISA definition of the family of microprocessors, so the manufacturer of the family of microprocessors ISA is usually defined in the operator's manual. For example, the Intel 64 and IA-32 Architectures Software Developer's Manual published in March 2009 is the ISA that defines the Intel 64 and IA-32 processor architectures. This software developer's manual contains five chapters, the first chapter is the basic architecture; the second chapter A is the instruction set reference A to M; the second B chapter is the instruction set reference N to Z; the third chapter A is the system programming guide ;Chapter 3B is the second part of the System Programming Guide, this manual series is the reference document for this case. This processor architecture is often referred to as the x86 architecture, and is described in this document in terms of x86, x86ISA, x86ISA family, x86 family, or similar terms. In another example, the ARM Architecture Reference Manual published in 2010, the ARM v7-A and ARM v7-R versions Errata markup, defines the ISA for the ARM processor architecture. This reference manual series is a reference document. The ISA for the ARM processor architecture is also referred to herein as ARM, ARM ISA, ARM ISA family, ARM family, or similar terms. Other well-known ISA families are IBM System/360/370/390 and z/Architecture, DEC VAX, Motorola 68k, MIPS, SPARC, PowerPC and DEC Alpha, etc. The definition of ISA will cover processor families, as processor families evolve, manufacturers will improve the ISA of the original processor by adding new instructions to the instruction set, and/or adding new registers to the register set. For example, with the development of the x86 assembly architecture, it introduced a set of 128-bit Multimedia Extensions (MMX) registers in the Intel Pentium III processor family as part of the Single Instruction Multiple Stream Extensions (SSE) instruction set, And x86ISA machine language programs have been developed to use XMM registers to improve performance, although existing x86ISA machine language programs do not use the XMM registers of the SIMD extended instruction set. In addition, other manufacturers have designed and built microprocessors that can execute x86ISA machine language programs. For example, AMD and VIA Technologies are adding new technology features to the x86ISA, such as AMD's 3DNOW! Single instruction multiple data stream (SIMD) vector processing instructions, as well as VIA's Padlock security engine random number generator (random number generator) and advanced cryptography engine (advanced cryptography engine) technology, the aforementioned technologies are machine language programs using x86ISA , but not implemented by existing Intel microprocessors. As another example, the ARM ISA originally defines the ARM instruction set state to have 4-byte instructions. However, with the development of the ARM ISA other instruction set states have been added, such as the Thumb instruction set state with 2-byte instructions to increase coding density and the Jazelle instruction set state to accelerate Java bytecode programs, while the ARM ISA machine language Programs have been developed to use some or all of the other ARM ISA instruction set states, even though existing ARM ISA machine language programs do not use these other ARM ISA instruction set states.

An Instruction Set Architecture (ISA) machine language program includes a sequence of ISA instructions, that is, a sequence of binary coded values in the ISA instruction set corresponding to the sequence of operations that the program author wants the program to perform. Thus, x86ISA machine language programs contain x86ISA instruction sequences, and ARM ISA machine language programs contain ARM ISA instruction sequences. Machine language program instructions are stored in the memory and are retrieved and executed by the microprocessor.

Hardware instruction translator, including a configuration of multiple transistors, to receive ISA machine language instructions (such as x86ISA or ARM ISA machine language instructions) as input, and correspondingly output one or more microinstructions to the execution pipeline of the microprocessor . The execution result of the execution pipeline executing the microinstruction is defined by the ISA instruction. Thus, the execution pipeline "implements" ISA instructions through collective execution of these microinstructions. That is, the execution pipeline implements the operation specified by the input ISA instruction through collective execution of the execution microinstructions output by the hardware instruction translator, so as to generate the result defined by the ISA instruction. Thus, a hardware instruction translator can be thought of as "translating" an ISA instruction into one or more execution microinstructions. The microprocessor described in this embodiment has a hardware instruction translator to translate x86 ISA instructions and ARM ISA instructions into micro-instructions. However, it should be understood that the hardware instruction translator is not necessarily capable of translating the entire instruction set defined in the x86 user manual or the ARM user manual, but often can only translate a subset of these instructions, just like absolutely Most x86ISA and ARM ISA processors only support a subset of instructions as defined by their corresponding user manuals. Specifically, the x86 user manual defines the instruction subset translated by the hardware instruction translator, which does not necessarily correspond to all existing x86 ISA processors. The ARM user manual defines the instruction subset translated by the hardware instruction translator. Does not necessarily correspond to all existing ARM ISA processors.

The execution pipeline is a sequence of stages. Each level of the multi-level sequence has hardware logic and a hardware register, respectively. The hardware register holds the output signal of the hardware logic and provides the output signal to the next level of the multi-level sequence according to the clock signal of the microprocessor. An execution pipeline can have multiple multi-level sequences, such as multiple execution pipelines. The execution pipeline receives the microinstruction as an input signal, and accordingly executes the operation specified by the microinstruction to output the execution result. The operations specified by the microinstructions and performed by the hardware logic of the execution pipeline include but are not limited to arithmetic, logic, memory load/store, comparison, testing, and branch parsing, and the data formats for operations include but are not limited to integer, floating Points, words, binary coded decimal (BCD), and packed formats. The execution pipeline executes microinstructions to implement ISA instructions (eg, x86 and ARM), thereby producing the results defined by the ISA instructions. The execution pipeline is different from the hardware instruction translator. Specifically, the hardware instruction translator generates execution microinstructions, and the execution pipeline executes these instructions, but does not generate these execution microinstructions.

The instruction cache is a random-access storage device in a microprocessor in which the microprocessor places the instructions of an ISA machine language program (such as the machine language instructions of the x86 ISA and ARM ISA), which are fetched from system memory and stored. It is executed by the microprocessor according to the execution flow of the ISA machine language program. Specifically, the ISA defines an instruction address register to hold the memory address of the next ISA instruction to be executed (for example, the x86 ISA is defined as the instruction pointer (IP) and the ARM ISA is defined as the program counter (PC), When the microprocessor executes the machine language program to control the program flow, the microprocessor will update the content of the instruction address register. The ISA instruction is cached for subsequent retrieval. When the next machine language program contained in the register The ISA instruction address is located in the current instruction cache, and the ISA instruction can be quickly retrieved from the instruction cache and fetched from the system memory according to the content of the instruction register. In particular, this program is based on the instruction address register (such as The memory address of the instruction pointer (IP) or program counter (PC) fetches data from the instruction cache, rather than using the memory address specified by a load or store instruction for data retrieval. Therefore, the instruction set architecture Instructions are treated as dedicated data caches for data (such as data presented by the hardware portion of the system using software translation) and are specifically accessed using a load/store address rather than based on the value of the instruction address register. Not an instruction cache as referred to here. In addition, hybrid caches that can fetch instructions and data, based on the value of the instruction address register and based on the load/store address, not just the load/store address, are also covered in this document. Explain within the definition of instruction caching. In the content of this description, a load instruction refers to an instruction to read data from the memory to the microprocessor, and a store instruction refers to an instruction to write data from the microprocessor into the memory.

A microinstruction set is a collection of instructions (microinstructions) that can be executed by the execution pipeline of a microprocessor.

Example description

The microprocessor disclosed in the embodiment of the present invention can translate its corresponding x86ISA and ARM ISA instructions into microinstructions directly executed by the microprocessor execution pipeline through hardware, so as to achieve the purpose of executing the x86ISA and ARM ISA machine language programs. The microinstructions are defined by a microinstruction set that is different from the microarchitecture of the x86 ISA and the ARM ISA. Since the microprocessor described in this paper needs to execute x86 and ARM machine language programs, the hardware instruction translator of the microprocessor will translate the x86 and ARM instructions into microinstructions, and provide these microinstructions to the execution pipeline of the microprocessor, These microinstructions are executed by the microprocessor to implement the aforementioned x86 and ARM instructions. Since these execution microinstructions are directly provided by the hardware instruction translator to the execution pipeline for execution, different from the system using the software translator, which needs to pre-store the local (host) instructions in the memory before executing the instructions in the execution pipeline, therefore, The aforementioned microprocessors have the potential to execute x86 and ARM machine language programs at relatively high execution speeds.

FIG. 1 is a block diagram showing an embodiment of a microprocessor 100 of the present invention that executes machine language programs for x86 ISA and ARM ISA. The microprocessor 100 has an instruction cache 102; a hardware instruction translator 104 for receiving x86 ISA instructions and ARM ISA instructions 124 from the instruction cache 102 and translating them into micro-instructions 126; an execution pipeline 112, which is executed by The microinstructions 126 received by the hardware instruction translator 104 are used to generate microinstruction results 128, which are passed back to the execution pipeline 112 in the form of operands; a register file 106 and a memory subsystem 108, respectively, provide operands to the execution pipelines 112 and receive microinstruction result 128 by execution pipeline 112; an instruction fetch unit and branch predictor 114, providing a fetch address 134 to instruction cache 102; an ARM ISA-defined program counter register 116 and an x86 ISA-defined instruction a pointer register 118, which is updated according to the microinstruction result 128 and provides its contents to the instruction fetch unit and branch predictor 114; and a plurality of configuration registers 122, which provides an instruction mode pointer 132 and an ambient mode pointer 136 to hardware instructions The translator 104 and the instruction fetch unit and the branch predictor 114 are updated based on the microinstruction result 128 .

Since the microprocessor 100 can execute x86 ISA and ARM ISA machine language instructions, the microprocessor 100 retrieves the instructions from the system memory (not shown) to the microprocessor 100 according to the program flow. The microprocessor 100 accesses the most recently fetched x86 ISA and ARM ISA machine language instructions to the instruction cache 102 . The instruction fetch unit 114 will generate a fetch address 134 according to the x86 or ARM instruction byte segment fetched from the system memory. If the instruction cache 102 is hit, the instruction cache 102 provides the x86 or ARM instruction byte segment at the fetch address 134 to the hardware instruction translator 104, otherwise the instruction set architecture instruction 124 is fetched from system memory. The instruction fetch unit 114 generates the fetch address 134 based on the values of the ARM program counter 116 and the x86 instruction pointer 118 . Specifically, the instruction fetch unit 114 maintains a fetch address in a fetch address register. Whenever the instruction fetch unit 114 fetches a new ISA instruction byte segment, it updates the fetch address according to the size of the segment, and proceeds in sequence according to the established manner until a control flow event occurs. Control flow events include the generation of an exception event, the prediction of branch predictor 114 indicating that there is a taking branch within the fetch section, and the response by execution pipeline 112 to a branch that was not predicted by branch predictor 114 to take The execution result of the instruction, and the update of the ARM program counter 116 and the x86 instruction pointer 118. The instruction fetch unit 114 updates the fetch address to the exception handler address, the prediction target address or the execution target address accordingly in response to a control flow event. In one embodiment, instruction cache 102 is a hybrid cache for accessing ISA instructions 124 and data. It should be noted that in this hybrid cache embodiment, although the hybrid cache can write data into the cache or read data from the cache based on a load/store address, the microprocessor 100 uses the hybrid cache In the case of fetching the instruction 124 of the instruction set architecture, the hybrid cache is accessed based on the values of the ARM program counter 116 and the x86 instruction pointer 118, rather than based on load/store addresses. Instruction cache 102 may be a random access memory device.

Instruction mode pointer 132 is a status indicating whether microprocessor 100 is currently fetching, formatting/decoding, and translating x86 ISA or ARM ISA instructions 124 into microinstructions 126 . In addition, execution pipeline 112 and memory subsystem 108 receive the instruction mode pointer 132, which affects how microinstructions 126 are executed, although only a small subset of the microinstruction set is affected. The x86 instruction pointer register 118 holds the memory address of the next x86 ISA instruction 124 to be executed, and the ARM program counter register 116 holds the memory address of the next ARM ISA instruction 124 to be executed. In order to control the program flow, the microprocessor 100 updates the x86 instruction pointer register 118 and the ARM program counter register 116 respectively when it executes the x86 and ARM machine language programs to the target address of the next instruction, branch instruction or exception handler address . When the microprocessor 100 executes the instructions of the machine language program of x86 and ARM ISA, the microprocessor 100 fetches the instruction of the instruction set architecture of the machine language program from the system memory, and puts it into the instruction cache 102 to replace the latest more recent instruction. Instructions that are not fetched and executed. The instruction fetch unit 114 generates a fetch based on the value of the x86 instruction pointer register 118 or the ARM program counter register 116, and according to the instruction mode pointer 132 indicating that the ISA instruction 124 being fetched by the microprocessor 100 is in x86 or ARM mode. Address 134. In one embodiment, the x86 instruction pointer register 118 and the ARM program counter register 116 may be implemented as a shared hardware instruction address register to provide its contents to the instruction fetch unit and branch predictor 114 and to be executed by the execution pipeline 112 according to the instruction. The mode indicated by the mode pointer 132 is the semantics of x86 or ARM and x86 or ARM to be updated.

The context mode pointer 136 is a status indicating that the microprocessor 100 is using the x86 or ARM ISA semantics meaning the various execution environments in which the microprocessor 100 operates, such as virtual memory, exceptions, cache control, and global execution time protection. Thus, the instruction mode pointer 132 and the ambient mode pointer 136 together generate multiple execution modes. In the first mode, the instruction mode pointer 132 and the environment mode pointer 136 both point to the x86 ISA, and the microprocessor 100 acts as a general x86 ISA processor. In the second mode, the instruction mode pointer 132 and the environment mode pointer 136 both point to the ARM ISA, and the microprocessor 100 acts as a general ARM ISA processor. In the third mode, the instruction mode pointer 132 points to the x86 ISA, but the environment mode pointer 136 points to the ARM ISA. This mode is conducive to executing user-mode x86 machine language programs under the control of the ARM operating system or the hypervisor; Conversely, in the fourth mode, the instruction mode pointer 132 points to the ARM ISA, but the environment mode pointer 136 points to the x86 ISA. This mode facilitates execution of user-mode ARM machines under the control of an x86 operating system or a hypervisor. language program. The values of the command mode pointer 132 and the environment mode pointer 136 are determined at the beginning of the reset. In one embodiment, this initial value is encoded as a microcode constant, but can be modified by blowing configuration fuses and/or using microcode patching. In another embodiment, the initial value is provided to the microprocessor 100 by an external input. In one embodiment, the ambient mode pointer 136 is only changed after a reset is performed by a reset-to-ARM instruction 124 or a reset-to-x86 instruction 124 (Please refer to FIGS. 6A and 6B below); that is, when the microprocessor 100 is operating normally without performing a reset by the general reset, reset to x86, or reset to ARM instructions 124, the ambient mode pointer 136 does not will not change.

The hardware instruction translator 104 receives x86 and ARM ISA machine language instructions 124 as input and accordingly provides one or more microinstructions 126 as output signals to implement the x86 or ARM ISA instructions 124. The execution pipeline 112 exposes one or more micro-instructions 126 before execution, and the result of its collective execution implements x86 or ARM ISA instructions 124. That is to say, the collective execution of these microinstructions 126 can execute the operations specified by the x86 or ARM ISA instructions 124 according to the x86 or ARM ISA instructions 124 specified by the input terminal to generate the x86 or ARM ISA instructions 124 specified operations. result. Accordingly, hardware instruction translator 104 translates x86 or ARM ISA instructions 124 into one or more microinstructions 126 . The hardware instruction translator 104 includes a set of transistors configured in a predetermined manner to translate x86 ISA and ARM ISA machine language instructions 124 into execution microinstructions 126 . The hardware instruction translator 104 also has Boolean logic gates to generate execute microinstructions 126 (simple instruction translator 204 shown in FIG. 2). In one embodiment, the hardware instruction translator 104 also has a microcode ROM (eg, element 234 of the complex instruction translator 206 in FIG. 2 ). The ISA instruction 124 generates the execution microinstruction 126, which will be further explained in the description of FIG. 2 . For a preferred embodiment, the hardware instruction translator 104 need not be able to translate the entire set of ISA instructions 124 as defined by the x86 user manual or the ARM user manual, but only a subset of these instructions. That's it. Specifically, the subset of ISA instructions 124 defined by the x86 user manual and translated by the hardware instruction translator 104 does not necessarily correspond to any existing x86 ISA processor developed by Intel, but is defined by the ARM user manual And the subset of ISA instructions 124 translated by hardware instruction translator 104 does not necessarily correspond to any existing ISA processor developed by ARM Ltd. The preceding one or more execution microinstructions 126 for implementing x86 or ARM ISA instructions 124 may be provided by hardware instruction translator 104 all at once to execution pipeline 112 or sequentially. The advantage of this embodiment is that the hardware instruction translator 104 can directly provide the execution microinstructions 126 to the execution pipeline 112 for execution without the need to store these microinstructions 126 in a memory between the two. In the embodiment of the microprocessor 100 in FIG. 1, when the microprocessor 100 executes the x86 or ARM machine language program, every time the microprocessor 100 executes the x86 or ARM instruction 124, the hardware instruction translator 104 will The x86 or ARM machine language instructions 124 are translated into one or more microinstructions 126 . However, the embodiment of FIG. 8 utilizes a microinstruction cache to avoid the double translation problem encountered by the microprocessor 100 every time the x86 or ARM ISA instruction 124 is executed. An embodiment of the hardware instruction translator 104 is described in more detail in FIG. 2 .

The execution pipeline 112 executes the execute microinstructions 126 provided by the hardware instruction translator 104 . Basically, the execution pipeline 112 is a general purpose high-speed microinstruction processor. Although the functions described herein are performed by the execution pipeline 112 with x86/ARM specific features, most x86/ARM specific functions are actually performed by other parts of the microprocessor 100, such as the hardware instruction translator 104. In one embodiment, execution pipeline 112 executes register renaming, superscalar issue, and non-sequential execution of execution microinstructions 126 received by hardware instruction translator 104 . The execution pipeline 112 is described in more detail in FIG. 4 .

The microarchitecture of the microprocessor 100 includes: (1) a microinstruction set; (2) a resource set that can be accessed by the microinstruction 126 of the microinstruction set, and this resource set is a superset of the resources of x86 and ARM ISA ; and (3) a micro-exception set defined by the microprocessor 100 corresponding to the execution of the microinstruction 126, which is a superset of the exceptions of the x86 ISA and the ARM ISA. This microarchitecture is different from x86ISA and ARM ISA. Specifically, this microinstruction set differs from that of the x86ISA and ARM ISA in many respects. First of all, the operations performed by the microinstructions of the microinstruction set instruct the execution pipeline 112 and the operations performed by the instructions of the x86 ISA and ARM ISA instruction sets instruct the microprocessor to perform are not in a one-to-one correspondence. While many of these operations are the same, there are some operations specified by the microinstruction set that are not specified by the x86 ISA and/or ARM ISA instruction set. Conversely, there are some operations specified by the x86ISA and/or ARM ISA instruction set that are not specified by the microinstruction set. Second, the microinstructions of the microinstruction set are encoded in a different way than the instructions in the x86ISA and ARM ISA instruction sets. That is, although many of the same operations (eg: add, offset, load, return) are specified in the microinstruction set as well as in the x86 and ARM ISA instruction sets, the binary operations of the microinstruction set and the x86 or ARM ISA instruction set The code value correspondence table does not have a one-to-one correspondence. It is usually a coincidence that the binary opcode value correspondence table of the microinstruction set is the same as that of the x86 or ARM ISA instruction set, and there is still no one-to-one correspondence between them. Third, the microinstruction bit field of the microinstruction set does not correspond one-to-one with the instruction bit field of the x86 or ARM ISA instruction set.

In general, the microprocessor 100 can execute x86 ISA and ARM ISA machine language program instructions. However, the execution pipeline 112 itself cannot execute x86 or ARM ISA machine language instructions; instead, it executes the execution microinstructions 126 of the microinstruction set of the microprocessor 100 microarchitecture translated from the x86 ISA and ARM ISA instructions. However, although this microarchitecture is different from x86ISA and ARMISA, the present invention also proposes other embodiments to open the microinstruction set and resources specified by other microarchitectures to users. In these embodiments, the microarchitecture can effectively act as a third ISA with machine language programs executable by the microprocessor, in addition to the x86 ISA and the ARM ISA.

The following table (Table 1) describes some of the bit fields of the microinstructions 126 of the microinstruction set of one embodiment of the microprocessor 100 of the present invention.

The following table (Table 2) describes some of the microinstructions of the microinstruction set of one embodiment of the microprocessor 100 of the present invention.

Microprocessor 100 also includes some microarchitecture-specific resources, such as microarchitecture-specific general purpose registers, media registers, and segment registers (eg, registers for renaming or registers used by microcode) and not found on x86 or ARM. ISA control registers, and a private random access memory (PRAM). Furthermore, this micro-architecture can generate exceptional events, ie, the aforementioned micro-exception events. These exceptions are not found in or specified by the x86 or ARM ISAs, but are typically replays of microinstructions 126 and associated microinstructions 126 . Such situations include, for example: load miss situations, in which the execution pipeline 112 assumes a load operation and re-executes the load microinstruction 126 when it misses; miss translation lookaside buffers (TLBs), where a lookup table ( page table walk) and the translation lookaside buffer is filled, the microinstruction 126 is re-executed; the floating-point microinstruction 126 receives a denormal operand but the operand is evaluated as a normal condition, which needs to be normal in the execution pipeline 112 The microinstruction 126 is re-executed after the operand is converted; after a load microinstruction 126 is executed, it is detected that an earlier store microinstruction 126 and its address-colliding conflict (address-colliding), and the load microinstruction 126 needs to be re-executed. It should be understood that the bit fields listed in Table 1, the microinstructions listed in Table 2, as well as the resources specified by the microarchitecture and the exception events specified by the microarchitecture are only used as examples to illustrate the microarchitecture of the present invention, rather than exhaustive. All possible embodiments of the invention.

Register file 106 contains hardware registers used by microinstructions 126 to hold resource and/or destination operands. The execution pipeline 112 writes its result 128 to the register file 106 , and the register file 106 receives operands for the microinstruction 126 . The hardware registers are some registers in the shared register file 106 that instantiate the x86 ISA-defined and ARM ISA-defined general purpose registers. For example, in one embodiment, the register file 106 references fifteen 32-bit registers shared by the ARM ISA registers R0 through R14 and the x86 ISA accumulation registers (EAX register) through R14D registers. Therefore, if a first microinstruction 126 writes a value to the ARM R2 register, a subsequent second microinstruction 126 that reads the x86 accumulation register will receive the same value as the first microinstruction 126 wrote, and vice versa Of course. This technical feature is beneficial to make the machine language programs of x86ISA and ARM ISA communicate quickly through registers. For example, assume that an ARM machine language program executed on an ARM machine language operating system can change the instruction mode 132 to x86ISA and transfer control to an x86 machine language program to perform a specific function, because the x86ISA can support some instructions, which The execution speed is faster than the ARM ISA, which in this case will benefit the execution speed. The ARM program provides the required data to the x86 execution program through the shared registers of the register file 106 . On the contrary, the x86 executable program can provide the execution result into the shared register of the register file 106, so that the ARM program can see the execution result after the x86 executable program responds. Similarly, an x86 machine language program executing on an x86 machine language operating system may change the instruction mode 132 to the ARM ISA and transfer control to the ARM machine language program; this x86 program may provide the required The data is sent to the ARM execution program, and the ARM execution program can provide the execution result through the shared register of the register file 106, so that the x86 program can see the execution result after the ARM execution program replies. Because the ARM R15 register is an independently referenced ARM program counter register 116, the sixteenth 32-bit register that references the x86R15D register is not shared with the ARM R15 register. In addition, in one embodiment, sixteen 128-bit XMM0 to XMM15 registers and sixteen 128-bit Advanced SIMD ("Neon") 32-bit segments of x86 registers are shared with Thirty-two 32-bit ARM VFPv3 floating point registers. Register file 106 also references flag registers (ie, the x86EFLAGS register and the ARM condition flags register), as well as various control and status registers defined by the x86 ISA and ARM ISA, including the x86 architecture specific model registers ( model specific registers, MSRs) and coprocessor (8-15) registers reserved for the ARM architecture. The register file 106 also references non-architectural registers, such as non-architectural general purpose registers used for register renaming or used by microcode 234, and non-architectural x86 model-specific registers and ARM implementation-defined or manufacturer-specified registers Coprocessor registers. The register file 106 is further illustrated in FIG. 5 .

The memory subsystem 108 includes a cache hierarchy consisting of caches (including, in one embodiment, a level-1 instruction cache 102, a level-1 data cache, and a level-2 cache). hybrid cache). The memory subsystem 108 contains various memory request queues such as load, store, fill, snoop, merge write merge buffer. The memory subsystem also includes a memory management unit (MMU). The memory management unit has translation lookaside buffers (TLBs), preferably separate instruction and data translation lookaside buffers. The memory subsystem also includes a table walkengine to obtain translations between virtual and physical addresses in response to translation lookaside buffer misses. Although the instruction cache 102 and the memory subsystem 108 are shown as independent in FIG. 1 , logically, the instruction cache 102 is also a part of the memory subsystem 108 . The memory subsystem 108 is configured to allow x86 and ARM machine language programs to share a common storage space, so that the x86 and ARM machine language programs can easily communicate with each other through memory.

Memory subsystem 108 is aware of instruction mode 132 and ambient mode 136, enabling it to perform various operations in the appropriate ISA context. For example, the memory subsystem 108 performs checks for certain memory access violations (eg, limit violation checks) according to the instruction mode pointer 132 indicating the x86 or ARM ISA. In another embodiment, the memory subsystem 108 flushes the translation lookaside buffer in response to a change in the ambient mode pointer 136; however, when the instruction mode pointer 132 changes, the memory subsystem 108 does not update the translation lookaside buffer accordingly area to provide better performance in the third and fourth modes in which the instruction mode pointer 132 and the environment mode pointer 136 respectively point to x86 and ARM. In another embodiment, in response to a translation lookaside buffer miss (TKB miss), the table lookup engine determines to use the x86 paging table or the ARM paging table to perform a paging table lookup according to the environment mode pointer 136 indicating the x86 or ARM ISA. Action to fetch the translation lookaside buffer. In another embodiment, if the environment state indicator 136 indicates x86 ISA, the memory subsystem 108 checks the architectural state of the x86 ISA control registers (eg, CROCD and NW bits) that affect the cache policy; if the environment mode indicator 136 indicates ARM ISA , check the architectural mode of the relevant ARM ISA control registers (such as the SCTLR I and C bits). In another embodiment, if the status indicator 136 indicates x86 ISA, the memory subsystem 108 checks the architectural status of the x86 ISA control registers (eg, the CROPG bit) that affect memory management; if the environment mode indicator 136 indicates ARM ISA, it checks the relevant The architectural mode of the ARM ISA control registers (such as the SCTLR M bit). In another embodiment, if the status indicator 136 indicates x86 ISA, the memory subsystem 108 checks the architectural status of the x86 ISA control registers (eg, the CROAM bit) that can affect alignment detection, and if the ambient mode indicator 136 indicates ARM ISA, checks Architectural mode of the associated ARM ISA control registers (such as the SCTLR A bit). In another embodiment, if status indicator 136 indicates x86ISA, memory subsystem 108 (and hardware instruction translator 104 for privileged instructions) checks the architectural state of the x86ISA control registers for the currently assigned privilege level (CPL); The environment mode pointer 136 indicates ARM ISA, then check the architectural mode of the relevant ARM ISA control register indicating user or privileged mode. However, in one embodiment, the x86 ISA and the ARM ISA share control bytes/registers with similar functions in the microprocessor 100, and the microprocessor 100 does not reference separate control bytes/registers for each instruction set architecture.

Although the configuration registers 122 and the register file 106 are shown separately in the figures, the configuration registers 122 may be understood as part of the register file 106 . The configuration register 122 has a global configuration register for controlling various aspects of the operation of the microprocessor 100 in the x86 ISA and the ARM ISA, such as the function of enabling or disabling various features. The global configuration register disables the ability of the microprocessor 100 to execute ARM ISA machine language programs, that is, makes the microprocessor 100 a microprocessor 100 that can only execute x86 instructions, and disables other related and ARM-specific capabilities ( Instructions 124 such as launch-x86 and reset to x86 and what are referred to herein as implementation-defined coprocessor registers) fail. The global configuration register can also disable the ability of the microprocessor 100 to execute x86ISA machine language programs, that is, make the microprocessor 100 a microprocessor 100 that can only execute ARM instructions, and enable other related capabilities (such as enabling ARM and reset to ARM instruction 124 and what is referred to herein as a new non-architecture specific model register) invalidation. In one embodiment, the microprocessor 100 is manufactured with preset configuration settings, such as hard-coded values in the microcode 234, which are used to configure the microprocessor 100 at startup with the hard-coded values configuration, such as writing to the encoding register 122. However, the partial code register 122 is set in hardware rather than in the microcode 234 . Additionally, the microprocessor 100 has multiple fuses that can be read by the microcode 234 . These fuses can be blown to modify preset configuration values. In one embodiment, the microcode 234 reads the fuse value, performs an exclusive-OR operation on the default value and the fuse value, and writes the operation result into the configuration register 122 . In addition, the effects of fuse value modification can be recovered using a microcode 234 patch. In the case where the microprocessor 100 is capable of executing x86 and ARM programs, the global configuration register can be used to confirm that the microprocessor 100 (or a particular core 100 of the multi-core portion of the processor as shown in FIG. 7) is in reset or as shown in FIG. As shown in FIG. 6A and FIG. 6B , when responding to the INIT instruction in the form of x86, whether the boot is performed in the form of the x86 microprocessor or the form of the ARM microprocessor. The global configuration register has some bits that provide initial preset values for specific architectural control registers, such as the ARM ISA SCTLT and CPACR registers. The multi-core embodiment shown in FIG. 7 only has one global configuration register, even if the configuration of each core can be set separately, for example, when the instruction mode pointer 132 and the environment mode pointer 136 are both set to x86 or ARM, select the x86 core or ARM core boot. In addition, the enable ARM instruction 126 and the enable x86 instruction 126 may be used to dynamically switch between the x86 and ARM instruction modes 132 . In one embodiment, the global configuration register can be read from a new non-architecture specific model register by an x86RDMSR instruction, and some of its control bits can be written to the new non-architecture specific model register by the x86WRMSR instruction. to perform the write operation. The global configuration register can also be read through the ARM MCR/MCRR instruction to an ARM coprocessor register corresponding to the new non-architecture-specific model register disclosed above, and some of the control bits can be corresponding to the new non-architecture model register through the ARM MRC/MRRC instruction. The non-architecture specific model registers are written to the ARM coprocessor registers to perform write operations.

Configuration registers 122 and contain a variety of different control registers from different orientations to control the operation of microprocessor 100 . These non-x86 (non-x86)/ARM control registers include what are referred to herein as global control registers, non-instruction set architecture control registers, non-x86/ARM control registers, general purpose control registers, and other similar registers. In one embodiment, these control registers can be accessed using x86 RDMSR/WRMSR instructions to non-architecture specific model registers (MSRs) and using ARM MCR/MRC (or MCRR/MRRC) instructions to new implementation-defined coprocessors register to access. For example, the microprocessor 100 includes non-x86/ARM control registers to enable fine-grained cache control that is smaller than what the x86 ISA and ARM ISA control registers can provide.

In one embodiment, microprocessor 100 provides ARM ISA machine language programs to access x86 ISA model-specific registers through implementation-defined ARM ISA coprocessor registers that directly correspond to corresponding x86 specific model registers. The address of this particular model register is assigned to the ARM ISA R1 register. This data is read from or written to the ARM ISA register specified by the MRC/MRRC/MCR/MCRR instruction. In one embodiment, a subset of the model-specific registers are password protected, ie instructions must use the password when attempting to access the model-specific registers. In this embodiment, the password is specified in the ARM R7:R6 registers. If the access operation results in an x86 general protection fault, the microprocessor 100 then generates an ARM ISA undefined instruction abort mode (UND) exception event. In one embodiment, the ARM coprocessor 4 (addresses: 0, 7, 15, 0) accesses the corresponding x86 model-specific registers.

The microprocessor 100 also includes an interrupt controller (not shown) coupled to the execution pipeline 112 . In one embodiment, the interrupt controller is an x86 style Advanced Programmable Interrupt Controller (APIC). The interrupt controller maps x86ISA interrupt events to ARM ISA interrupt events. In one embodiment, x86INTR corresponds to an ARM IRQ interrupt event; x86NMI corresponds to an ARM IRQ interrupt event; x86INIT triggers an INIT-reset sequence when the microprocessor 100 starts up, regardless of the instruction set architecture (x86 or ARM) were originally initiated by hardware reset; x86SMI corresponds to ARM FIQ interrupt events; and x86STPCLK, A20, Thermal, PREQ, and Rebranch do not correspond to ARM interrupt events. The ARM machine language can access advanced programmable interrupt controller functionality through new implementation-defined ARM coprocessor registers. In one embodiment, the APIC register address is assigned to the ARM R0 register, and the address of the APIC register is the same as the x86 address. In one embodiment, the ARM coprocessor 6 is usually used for the privileged mode function executed by the operating system, and the address of the ARM coprocessor 6 is: 0, 7, nn, 0; Program the interrupt controller; nn is 12-14 to access the bus interface unit to perform 8-bit, 16-bit and 32-bit input/output cycles on the processor bus. The microprocessor 100 also includes a bus interface unit (not shown), which is coupled to the memory subsystem 108 and the execution pipeline 112 as an interface between the microprocessor 100 and the processor bus. In one embodiment, the processor bus conforms to the specification of a microprocessor bus of the Intel Pentium microprocessor family. ARM machine language programs can access the functions of the bus interface unit through the new implementation-defined ARM coprocessor registers to generate an input/output cycle on the processor bus, that is, a specific address transferred from the input/output bus to the input/output space , so as to communicate with the system chip set, for example, ARM machine language program can generate a specific loop recognized by SMI or input and output loop about C state transition. In one embodiment, the input and output addresses are assigned to ARM R0 registers. In one embodiment, the microprocessor 100 has power management capabilities, such as known P-state and C-state management. ARM machine language programs can perform power management through new implementation-defined ARM coprocessor registers. In one embodiment, the microprocessor 100 includes an encryption unit (not shown) located within the execution pipeline 112 . In one embodiment, the encryption unit is substantially similar to the encryption unit of a VIA microprocessor with Padlock security technology. ARM machine language programs can access cryptographic unit functions, such as cryptographic instructions, through new implementation-defined ARM coprocessor registers. In one embodiment, the ARM coprocessor 5 is used for user-mode functions typically performed by user-mode applications, such as those generated using technical features of the encryption unit.

When the microprocessor 100 executes the x86 ISA and ARM ISA machine language programs, every time the microprocessor 100 executes the x86 or ARM ISA instruction 124, the hardware instruction translator 104 performs hardware translation. Conversely, systems using software translation can help improve performance by reusing the same translation across multiple events, rather than repeating translations of previously translated machine language instructions. Furthermore, the embodiment of FIG. 8 uses microinstruction caching to avoid repeated translation operations that may occur each time the microprocessor executes an x86 or ARM ISA instruction 124 . The manners described in the foregoing embodiments of the present invention are adapted to different program features and their execution environments, and thus are indeed helpful to improve performance.

The branch predictor 114 accesses historical data of previously executed x86 and ARM branch instructions. The branch predictor 114 analyzes whether there are x86 and ARM branch instructions and their target addresses in the cache line obtained by the instruction cache 102 according to the previous cache history data. In one embodiment, the cache history data includes the memory address of the branch instruction 124, the branch target address, a direction pointer, the type of the branch instruction, the start byte of the branch instruction cache line, and an indication of whether it spans multiple Cache line indicator. In one embodiment, such as US Provisional Application No. 61/473,067, "APPARATUS AND METHOD FOR USING BRANCH PREDICTION TO EFFICIENTLYEXECUTE CONDITIONAL NON-BRANCH INSTRUCTIONS," filed April 7, 2011, provides improved performance of branch predictor 114 A way to make it predict the direction of an ARM ISA conditional non-branch instruction. In one embodiment, the hardware instruction translator 104 also includes a static branch predictor that can predict x86 and ARM branch instructions based on data such as execution code, type of condition code, backward or forward, etc. direction and branch target address.

The present invention also contemplates a number of different embodiments to implement the combination of different features defined by the x86 ISA and the ARM ISA. For example, in one embodiment, microprocessor 100 implements the ARM, Thumb, ThumbEE, and Jazelle instruction set states, but provides a trivial implementation for the Jazelle extended instruction set; microprocessor 100 does not implement The following extended instruction sets, including: Thumb-2, VFPv3-D32, Advanced SIMD (Neon), multiprocessing, and VMSA; but do not implement the following extended instruction sets, including: Security extensions , Fast content switching extension, ARM debug (ARM program can obtain x86 debug function through ARM MCR/MRC instruction to the new implementation-defined coprocessor register), performance check counter (ARM program can use the new implementation-defined coprocessor register to obtain the x86 debug function) processor registers to obtain x86 performance counters). For example, in one embodiment, the microprocessor 100 treats the ARM SETEND instruction as a no-operation instruction (NOP) and only supports the Little-endian data format. In another embodiment, the microprocessor 100 does not implement x86SSE4.2 functionality.

The present invention contemplates the improvement of the microprocessor 100 of various embodiments, such as the improvement of the commercial microprocessor VIA Nano ^TM produced by VIA Electronics Co., Ltd. of Taipei, Taiwan. This Nano microprocessor is capable of executing x86 ISA machine language programs, but not ARM ISA machine language programs. The Nano microprocessor includes high-performance register renaming, superscalar instruction technology, an out-of-order execution pipeline, and a hardware translator to translate x86 ISA instructions into microinstructions for execution by the execution pipeline. The invention improves the Nano hardware instruction translator, so that in addition to translating x86 machine language instructions, it can also translate ARM ISA machine language instructions into micro-instructions for execution by the execution pipeline. Improvements to hardware instruction translators include improvements to simple instruction translators and improvements to complex instruction translators (including microcode). In addition, the microinstruction set can add new microinstructions to support the translation between ARM ISA machine language instructions and microinstructions, and can improve the execution pipeline to enable the execution of new microinstructions. In addition, the Nano register file and memory subsystem can also be improved to support the ARM ISA, also including the sharing of specific registers. The branch prediction unit can be improved to be suitable for ARM branch instruction prediction in addition to x86 branch prediction. The advantage of this embodiment is that, because of the largely ISA-agnostic limitations, only minor modifications to the Nano microprocessor's execution pipeline are required to accommodate ARM ISA instructions. Improvements to the execution pipeline include the generation and use of condition code flags, the semantics for updating and reporting the instruction pointer register, access privilege protection methods, and various memory management related functions such as access violation detection, paging and translation The use of lookaside buffers (TLBs), and caching strategies, etc. The foregoing content is only an example, rather than a limitation of the present invention, and some of the features will be further described in the subsequent content. Finally, as mentioned above, some features defined by the x86 ISA and ARM ISA may not be supported by the previously disclosed embodiments that improve the Nano microprocessor, such as the x86SSE 4.2 and ARM security extensions, fast content switching extensions, debugging and Performance counter, some of its features will be further explained in the following content. In addition, the previous disclosure is an embodiment of a single integrated circuit product capable of executing x86 and ARM machine language programs by improving the Nano processor to support ARM ISA machine language programs, which is an integrated use of design, testing and manufacturing resources to execute x86 and ARM machine language programs. Integrated circuit products cover the vast majority of existing machine language programs in the market, and are in line with current market trends. The embodiments of the microprocessor 100 described herein may be configured essentially as an x86 microprocessor, an ARM microprocessor, or a microprocessor that can execute both x86 ISA and ARM ISA machine language programs. The microprocessor can achieve the ability to simultaneously execute x86 ISA and ARM ISA machine language programs through dynamic switching between x86 and ARM instruction modes 132 on a single microprocessor 100 (or core 100 of FIG. 7 ), or through One or more cores of the multi-core microprocessor 100 (corresponding to that shown in FIG. 7 ) are configured as ARM cores and one or more cores as x86 cores, that is, by performing x86 and Dynamic switching between ARM instructions to achieve simultaneous execution of x86ISA and ARM ISA machine language programs. In addition, traditionally, the ARM ISA core was designed as an intellectual property core and incorporated into its applications by various third-party third-party vendors, such as SoCs and/or embedded applications. Therefore, the ARM ISA does not have a specific standard processor bus as the interface between the ARM core and other parts of the system (such as chipsets or other interface devices). Advantageously, the Nano processor already has a high-speed x86-style processor bus as an interface to memory and interface devices, and a memory-coherent architecture that cooperates with the microprocessor 100 to support ARM ISA machine language programs in an x86 computer system environment. execution.

Please refer to FIG. 2 , which is a block diagram showing the hardware instruction translator 104 of FIG. 1 in detail. The hardware instruction translator 104 includes hardware, more specifically, a collection of transistors. The hardware instruction translator 104 includes an instruction formatter 202, which receives the instruction mode pointer 132 and the block of x86ISA and ARM ISA instruction bytes 124 from the instruction cache 102 of FIG. 1, and outputs formatted x86ISA and ARM ISA instructions 242 ; a simple instruction translator (SIT) 204 receives instruction mode pointer 132 and ambient mode pointer 136, and outputs implementation microinstructions 244 and a microcode address 252; a complex instruction translator (CIT) 206 (also known as a microcode unit), receives microcode address 252 and ambient mode pointer 136, and provides execution microinstructions 246; and a multiplexer 212, one input of which receives microinstructions 244 by simple instruction translator 204, and the other input is composed of complex instructions Translator 206 receives microinstructions 246 and provides implementation of microinstructions 126 to execution pipeline 112 of FIG. 1 . The instruction formatter 202 is described in more detail in FIG. 3 . The simple instruction translator 204 includes an x86 simple instruction translator 222 and an ARM simple instruction translator 224 . The complex instruction translator 206 includes a micro-PC (micro-PC) 232 that receives the micro-program address 252, a micro-code ROM 234 that receives the ROM address 254 from the micro-program counter 232, a micro-PC for updating the micro-PC The microsequencer 236, an instruction indirection register (IIR) 235, and a microtranslator (microtranslator) 237 for generating the execution microinstructions 246 output by the complex instruction translator. Both the execution microinstructions 244 generated by the simple instruction translator 204 and the execution microinstructions 246 generated by the complex instruction translator 206 belong to the microinstructions 126 of the microinstruction set of the microarchitecture of the microprocessor 100, and can be directly accessed by The execution pipeline 112 executes.

Multiplexer 212 is controlled by a select input 248 . Normally, the multiplexer 212 selects a microinstruction from the simple instruction translator 204; however, when the simple instruction translator 204 encounters a complex x86 or ARM ISA instruction 242 and transfers control, or encounters traps, To transfer to complex instruction translator 206, simple instruction translator 204 controls select input 248 to allow multiplexer 212 to select microinstructions 246 from the complex instruction translator. When register allocation table (RAT) 402 (see FIG. 4 ) encounters a microinstruction 126 with a specific bit indicating that it is the last microinstruction 126 to implement a sequence of complex ISA instructions 242 , register allocation table 402 then controls select input 248 The multiplexer 212 is reverted to selecting the microinstruction 244 from the simple instruction translator 204 . In addition, when the reorder buffer 422 (see FIG. 4) is ready to retire the microinstruction 126 and the state of the instruction indicates that a microinstruction from the complex instruction set needs to be selected, the reorder buffer 422 controls the select input 248 to multiplex The processor 212 selects the microinstructions 246 from the complex instruction translator 206 . For example, the situation in which the microinstruction 126 needs to be retired is as follows: the microinstruction 126 has caused an exception condition to be generated.

The simple instruction translator 204 receives ISA instructions 242 and decodes these instructions as x86 ISA instructions when the instruction mode pointer 132 indicates x86, and treats these instructions as ARMISA instructions when the instruction mode pointer 132 indicates ARM. decoding. Simple instruction translator 204 and confirms that ISA instruction 242 is a simple or complex ISA instruction. The simple instruction translator 204 is capable of outputting all the implement microinstructions 126 for implementing the simple ISA instruction 242 for the simple ISA instruction 242; that is, the complex instruction translator 206 does not provide any implement microinstructions 126 to the simple ISA instruction 124. Conversely, complex ISA instructions 124 require complex instruction translator 206 to provide at least some, if not all, of execute microinstructions 126 . In one embodiment, for the subset of instructions 124 of the ARM and x86 ISA instruction sets, the simple instruction translator 204 outputs microinstructions 244 that partially implement the x86/ARM ISA instructions 126, and then transfers control to the complex instruction translator 206, the complex instruction translator 206 continuously outputs the remaining microinstructions 246 to implement the x86/ARM ISA instructions 126. The multiplexer 212 is controlled to first provide the execute microinstructions 244 from the simple instruction translator 204 as the microinstructions 126 to the execution pipeline 112, and then provide the execute microinstructions 246 from the complex instruction translator 206 to be supplied to the execution pipeline 112 microinstructions 126. Simple instruction translator 204 knows to be executed by hardware instruction translator 104 to generate the address of starting microcode ROM 234 in multiple microcode programs that implement microinstruction 126 for multiple different complex ISA instructions 124, and when simple When the instruction translator 204 decodes a complex ISA instruction 242 , the simple instruction translator 204 provides the corresponding microcode program address 252 to the microprogram counter 232 of the complex instruction translator 206 . The simple instruction translator 204 outputs the microinstructions 244 required to implement a substantial proportion of the instructions 124 in the ARM and x86ISA instruction sets, especially for the ISA instructions 124 that need to be executed more frequently by x86ISA and ARMISA machine language programs, while only relatively A small number of instructions 124 need to be provided by complex instruction translator 206 to implement microinstructions 246 . According to one embodiment, x86 instructions such as RDMSR/WRMSR, CPUID, complex arithmetic instructions (such as FSQRT and transcendental instructions), and IRET instructions are mainly implemented by complex instruction translator 206; ARM instructions such as MCR, MRC, MSR, MRS, SRS, and RFE instructions. The instructions disclosed above do not limit the present invention, but merely illustrate the types of ISA instructions that can be implemented by the complex instruction translator 206 of the present invention.

When the instruction mode pointer 132 indicates x86, the x86 simple instruction translator 222 decodes the x86 ISA instruction 242, and translates it into an execution microinstruction 244; when the instruction mode pointer 132 indicates ARM, the ARM simple instruction translator 224 for the ARM ISA Instructions 242 are decoded and translated into implement microinstructions 244 . In one embodiment, the simple instruction translator 204 is a block of Boolean logic gates that can be synthesized by known synthesis tools. In one embodiment, x86 simple instruction translator 222 and ARM simple instruction translator 224 are separate Boolean logic gate blocks; however, in another embodiment, x86 simple instruction translator 222 and ARM simple instruction translator 224 are located in the same Boolean logic gate block. In one embodiment, the simple instruction translator 204 translates up to three ISA instructions 242 and provides up to six execute microinstructions 244 to the execution pipeline 112 in a single clock cycle. In one embodiment, the simple instruction translator 204 includes three sub-translators (not shown), each sub-translator translating a single formatted ISA instruction 242, wherein the first translator is capable of translating no more than Three formatted ISA instructions 242 implementing microinstructions 126; a second translator capable of translating no more than two formatted ISA instructions 242 implementing microinstructions 126; a third translator capable of posttranslation requiring no more than one Formatted ISA instructions 242 of microinstructions 126 are executed. In one embodiment, the simple instruction translator 204 includes a hardware state machine that enables it to output multiple microinstructions 244 over multiple clock cycles to implement an ISA instruction 242 .

In one embodiment, the simple instruction translator 204 performs a number of different exception detections based on the instruction mode pointer 132 and/or the ambient mode pointer 136 . For example, if the instruction mode pointer 132 indicates x86 and the x86 simple instruction translator 222 decodes an ISA instruction 124 that is invalid for the x86 ISA, the simple instruction translator 204 then generates an x86 invalid opcode exception; similarly Also, if the instruction mode pointer 132 indicates ARM and the ARM simple instruction translator 224 decodes an ISA instruction 124 that is not valid for the ARM ISA, the simple instruction translator 204 then generates an ARM undefined instruction exception event. In another embodiment, if ambient mode pointer 136 indicates x86 ISA, simple instruction translator 204 then checks whether each x86 ISA instruction 242 it encounters requires a particular privilege level, and if so, checks the current privilege level (CPL) whether the special privilege level required by this x86ISA instruction 242 is satisfied, and an exception is generated if not; similarly, if the environment mode pointer 136 indicates ARM ISA, the simple instruction translator 204 then checks whether each format The ARM ISA instruction 242 requires a privileged mode instruction. If so, it detects whether the current mode is the privileged mode, and generates an exception when the current mode is the user mode. Complex instruction translator 206 performs similar functions for certain complex ISA instructions 242 .

Complex instruction translator 206 outputs a series of execute microinstructions 246 to multiplexer 212 . The microcode ROM 234 stores the ROM instructions 247 of the microcode program. The microcode ROM 234 outputs the ROM instruction 247 in response to the address of the next ROM instruction 247 fetched by the microcode ROM 234 and held by the microprogram counter 232 . Generally, the microprogram counter 232 receives its start value 252 from the simple instruction translator 204 in response to the simple instruction translator 204 decoding a complex ISA instruction 242 . In other cases, such as in response to a reset or exception event, the microprogram counter 232 receives the reset microcode program address or the appropriate microcode exception handler address, respectively. The microprogrammer 236 typically updates the microprogram counter 232 to a sequence of microcode programs and, optionally, to the execution pipeline 112 in response to the execution of control-type microinstructions 126 (eg, branch instructions), depending on the size of the ROM instruction 247. target address to enable branches to non-program addresses within microcode ROM 234 to take effect. Microcode ROM 234 is fabricated within the semiconductor chip of microprocessor 100 .

In addition to microinstructions 244 used to implement simple ISA instructions 124 or portions of complex ISA instructions 124 , simple instruction translator 204 also generates ISA instruction information 255 for writing to instruction indirect registers 235 . The ISA instruction information 255 stored in the instruction indirect register 235 contains information about the ISA instruction 124 being translated, for example, information identifying the source and destination registers specified by the ISA instruction and the format of the ISA instruction 124, such as the ISA instruction 124 in the Executes on an operand of memory or within an architectural register 106 of the microprocessor 100 . This can thereby enable the microcode routines to be generalized, ie, eliminating the need to use different microcode routines for each different source and/or destination architectural register 106 . In particular, the simple instruction translator 204 knows the contents of the register file 106, including which registers are shared registers 504, and can translate the register information provided in the x86 ISA and ARM ISA instructions 124 to the register file through the use of the ISA instruction information 255. appropriate registers within 106. ISA instruction information 255 includes a shift field, an immediate field, a constant field, renaming information for each source operand and microinstruction 126 itself, the first and Information about the last microinstruction 126, and other bits that store useful information collected by the hardware instruction translator 104 when translating the ISA instruction 124.

Microtranslator 237 receives ROM instruction 247 from the contents of microcode ROM 234 and indirect instruction register 235 and generates execute microinstruction 246 accordingly. The microtranslator 237 translates a particular ROM instruction 247 into a different microtranslator based on the information received by the indirect instruction register 235, such as based on the format of the ISA instruction 124 and the combination of source and/or destination architecture registers 106 specified by it. Instruction 246 series. In some embodiments, number of ISA instruction information 255 is combined with ROM instructions 247 to generate execute microinstructions 246 . In one embodiment, each ROM instruction 247 is approximately 40 bits wide, and each microinstruction 246 is approximately 200 bits wide. In one embodiment, the microtranslator 237 can generate up to three microinstructions 246 from one microread memory instruction 247 . Microtranslator 237 contains a plurality of Boolean logic gates to generate execute microinstructions 246 .

The advantage of using the microtranslator 237 is that since the simple instruction translator 204 itself generates the ISA instruction information 255, the microcode ROM 234 does not need to store the ISA instruction information 255 provided by the indirect instruction register 235, thus reducing its size. . Furthermore, because the microcode ROM 234 does not need to provide a separate program for each different ISA instruction format, and each source and/or destination architecture register 106 combination, the microcode ROM 234 program may contain fewer Conditional branch instruction. For example, if complex ISA instructions 124 are in memory format, simple instruction translator 204 generates logic programming of microinstructions 244 including microinstructions 244 that load source operands from memory into a scratch register 106, and microtranslator 237 A microinstruction 246 is generated to store the result from the scratch register 106 to memory; however, if the complex ISA instruction 124 is in register format, the logic programming will move the source operand from the source register specified by the ISA instruction 124 to the scratch register, And the microtranslator 237 generates a microinstruction 246 for moving the result from the scratch register to the architectural destination register 106 designated by the indirect instruction register 235 . In one embodiment, many aspects of microtranslator 237 are similar to US Patent Application Serial No. 12/766,244, filed April 23, 2010, which is incorporated herein by reference. However, in addition to the x86 ISA instructions 124, the microtranslator 237 in this case is also improved to translate the ARM ISA instructions 124.

It is worth noting that the microprogram counter 232 is different from the ARM program counter 116 and the x86 instruction pointer 118, that is, the microprogram counter 232 does not hold the address of the ISA instruction 124, and the address held by the microprogram counter 232 does not fall within the in the system memory address space. Furthermore, it is worth noting that the microinstructions 246 are generated by the hardware instruction translator 104 and provided directly to the execution pipeline 112 for execution, rather than as the execution result 128 of the execution pipeline 112 .

Please refer to FIG. 3 , which is a block diagram illustrating the command formatter 202 of FIG. 2 in detail. Instruction formatter 202 receives x86 ISA and ARM ISA instruction byte 124 blocks from instruction cache 102 of FIG. 1 . With the variable-length nature of x86 ISA instructions, x86 instruction 124 can start with any byte in the instruction byte 124 block. Since x86ISA allows the length of the prefix byte to be affected by the current address length and operand length presets, the task of confirming the length and location of x86ISA instructions within a cache block is more complicated. In addition, according to the current ARM instruction set state 322 and the opcode of the ARM ISA instruction 124, the length of the ARM ISA instruction is either 2 bytes or 4 bytes, so it is either 2-byte aligned or 4-byte aligned. Therefore, the instruction formatter 202 extracts different x86 ISA and ARM ISA instructions from a stream of instruction bytes 124 formed from blocks received by the instruction cache 102 . That is, the instruction formatter 202 formats the x86 ISA and ARMISA instruction byte strings, thereby greatly simplifying the difficult task of decoding and translating the ISA instructions 124 by the simple instruction translator of FIG. 2 .

The instruction formatter 202 includes a pre-decoder 302. When the instruction mode pointer 132 indicates x86, the pre-decoder 302 pre-decodes the instruction byte 124 as an x86 instruction byte to generate pre-decoding information. When 132 indicates ARM, the pre-decoder 302 pre-decodes the instruction byte 124 as an ARM instruction byte to generate pre-decoding information. Instruction Byte Queue (IBQ) 304 receives the ISA instruction byte 124 block and associated pre-decoding information generated by pre-decoder 302 .

An array of length decoders and ripple logic gates 306 receives the contents of the bottom entry of the instruction byte queue 304, ie, the ISA instruction byte 124 block and associated pre-decoding information. The length decoder and ripple logic gate 306 also receives the instruction mode pointer 132 and the ARM ISA instruction set status 322. In one embodiment, the ARM ISA instruction set state 322 includes the J and T bits of the ARM ISA CPSR register. In response to its input information, the length decoder and ripple logic gate 306 generate decoded information. The decoded information includes the length of the x86 and ARM instructions within the ISA instruction byte 124 block, the x86 prefix information, and a pointer to each ISA instruction byte 124 indicating whether the byte is the start word of the ISA instruction 124 section, termination byte, and/or a valid byte. A multiplexer queue 308 receives the block of ISA command bytes 124 , the associated predecode information generated by the predecoder 302 , and the associated decode information generated by the length decoder and ripple logic gate 306 .

Control logic (not shown) checks the contents of the bottom entry of multiplexer queue (MQ) 308 and controls multiplexer 312 to retrieve different, or formatted, ISA commands and associated pre-decoding and decoding information, the retrieved Information is provided to a formatted instruction queue (FIQ) 314 . Formatted instruction queue 314 acts as a buffer between formatted ISA instructions 242 and related information provided to simple instruction translator 204 of FIG. 2 . In one embodiment, the multiplexer 312 retrieves up to three formatted ISA instructions and associated information per clock cycle.

In one embodiment, the instruction formatter 202 is similar in many respects to US Patent Nos. 12/571,997, 12/572,002, 12/572,045, 12/572,024, XIBQ, Command Formatter, and FIQ disclosed jointly by Application Nos. 12/572,052 and 12/572,058, which are incorporated herein by reference. However, the XIBQ, instruction formatter, and FIQ disclosed in the aforementioned patent application are modified so that they can format ARM ISA instructions 124 in addition to the x86 ISA instructions 124 . Length decoder 306 is modified to enable decoding of ARM ISA instructions 124 to generate length and byte pointers for start, end and validity. In particular, if the instruction mode pointer 132 indicates ARM ISA, the length decoder 306 detects the current ARM instruction set state 322 and the opcode of the ARM ISA instruction 124 to confirm that the ARM instruction 124 is a 2-byte or 4-byte length. instruction. In one embodiment, the length decoder 306 includes a plurality of independent length decoders for generating the length data of the x86 ISA instruction 124 and the length data of the ARM ISA instruction 124 respectively, and the outputs of these independent length decoders are then wired or (wire-ORed) coupled together to provide the output to the ripple logic gate 306 . In one embodiment, the format command queue 314 includes separate queues to hold separate portions of the format command 242 . In one embodiment, the instruction formatter 202 provides the simple instruction translator 204 with up to three formatted ISA instructions 242 in a single clock cycle.

Please refer to FIG. 4 , which is a block diagram showing the execution pipeline 112 of FIG. 1 in detail. The execution pipeline 112 is coupled to the hardware instruction translator 104 to directly receive the execution microinstructions from the hardware instruction translator 104 of FIG. 2 . The execution pipeline 112 includes a microinstruction queue 401 for receiving microinstructions 126 ; a register allocation table 402 for receiving microinstructions from the microinstruction queue 401 ; an instruction scheduler 404 coupled to the register allocation table 402 ; a plurality of reservation stations 406 , coupled to the instruction scheduler 404; an instruction issue unit 408, coupled to the reservation station 406; a rearrangement buffer 422, coupled to the register allocation table 402, the instruction scheduler 404 and the reservation station 406; and, the execution unit 424 is coupled to the reservation station 406 , the instruction issue unit 408 and the rearrangement buffer 422 . The register configuration table 402 and the execution unit 424 receive the instruction mode pointer 132 .

The microinstruction queue 401 acts as a buffer in situations where the hardware instruction translator 104 generates and executes the microinstructions 126 at a different rate than the execution pipeline 112 executes the microinstructions 126 . In one embodiment, the microinstruction queue 401 includes an M to N compressible microinstruction queue. This compressible microinstruction queue enables the execution pipeline 112 to receive up to M (in one embodiment, M is six) microinstructions 126 from the hardware instruction translator 104 in a given clock cycle, and will subsequently receive The resulting microinstructions 126 are stored in a queue structure of width N (in one embodiment, N is three) to provide at most N microinstructions 126 per clock cycle to the register allocation table 402 , which Up to N microinstructions 126 can be processed per clock cycle. The microinstruction queue 401 is compressible because it fills up the empty items of the queue with the microinstructions 126 transmitted by the hardware instruction translator 104 in sequence, regardless of the particular clock cycle at which the microinstructions 126 are received. Will leave holes in the queue items. The advantage of this approach is that the execution unit 424 (please refer to FIG. 4) can be fully utilized because it can provide higher instruction storage performance than an instruction queue of incompressible width M or width M. Specifically, a queue of incompressible width N would require hardware instruction translators 104, especially simple instruction translators 204, to repeatedly translate in subsequent clock cycles one or more commands that have already been executed in previous clock cycles. Translated ISA instructions 124. The reason for this is that a queue of incompressible width N cannot receive more than N uops 126 in the same clock cycle, and repeated translations will result in power consumption. However, although a queue of incompressible width M does not require repeated translation by the simple instruction translator 204, it will generate holes in the queue entries and cause waste, thus requiring more column entries and a larger and more energy-intensive queue to provide considerable buffering capacity.

The register configuration table 402 is used by the microinstruction queue 401 to receive the microinstruction 126 and generate auxiliary information with the microinstruction 126 in progress in the microprocessor 100. The register configuration table 402 performs the register renaming operation to increase the capability of parallel processing of the microinstruction. , in order to facilitate the ultra-scalar, non-sequential execution capability of the execution pipeline 112 . If the ISA instruction 124 indicates x86, the register configuration table 402 will correspond to the x86 ISA register 106 of the microprocessor 100, generate auxiliary information and perform the corresponding register renaming operation; otherwise, if the ISA instruction 124 indicates ARM, the register configuration table 402 will correspond to the ARM ISA registers 106 of the microprocessor 100, generate additional information and perform the corresponding register renaming operations; however, as mentioned above, some of the registers 106 may be shared by the x86 ISA and the ARM ISA. The register allocation table 402 also allocates an entry in the rearrangement buffer 422 to each microinstruction 126 according to program order, so that the rearrangement buffer 422 enables the microinstruction 126 and its associated x86 ISA and ARM ISA instructions 124 to be retired according to program order , even though the execution of the microinstruction 126 is performed in a non-sequential manner corresponding to the x86 ISA and ARM ISA instructions 124 it is intended to implement. The rearrangement buffer 422 contains a circular queue whose entries are used to store information about the microinstruction 126 in progress. This information includes, among other things, the execution status of the microinstruction 126, a confirmation that the microinstruction 126 is Labels translated by x86 or ARMISA instructions 124, and storage space for storing the results of microinstructions 126.

The instruction scheduler 404 receives the register renaming microinstruction 126 and ancillary information from the register allocation table 402, and dispatches the microinstruction 126 and its ancillary information to the appropriate execution unit according to the type of instruction and the availability of the execution unit 424 424 of the reserved station 406 . The execution unit 424 will execute the microinstruction 126 .

For each microinstruction 126 waiting in the reservation station 406, the instruction issuing unit 408 issues the microinstruction 126 to when it detects that the relevant execution unit 424 is available and its associated information is satisfied (eg, the source operand is available). The execution unit 424 is for execution. As mentioned above, the microinstructions 126 issued by the instruction issuing unit 408 can be executed acyclically and in a superscalar manner.

In one embodiment, execution unit 424 includes integer/branch unit 412 , media unit 414 , load/store unit 416 , and floating point unit 418 . Execution unit 424 executes microinstructions 126 to produce results 128 and provide to reorder buffer 422 . Although execution unit 424 is not greatly affected by whether the microinstructions 126 it executes are translated from x86 or ARM ISA instructions 124, execution unit 424 still uses instruction mode pointer 132 and ambient mode pointer 136 to execute relatively small 126 subset of microinstructions. For example, the execution pipeline 112 manages the generation of flags, and its management is slightly different depending on whether the instruction mode pointer 132 indicates the x86 ISA or the ARM ISA, and the execution pipeline 112 according to the instruction mode pointer 132 indicates whether the x86 ISA or the ARM ISA, Updates the ARM condition code flags in the x86EFLAGS register or the Program Status Register (PSR). In another example, the execution pipeline 112 samples the instruction mode pointer 132 to determine whether to update the x86 instruction pointer (IP) 118 or the ARM program counter (PC) 116, or to update the common instruction address register. In addition, the execution pipeline 122 also uses this to determine whether to use the x86 or ARM semantics to perform the aforementioned operations. Once the microinstruction 126 becomes the oldest completed microinstruction 126 in the microprocessor 100 (ie, at the head of the queue in the rearrangement buffer 422 and assumes a completed state) and other functions used to implement the associated ISA instruction 124 When all microinstructions 126 have completed, the rearrangement buffer 422 retires the ISA instructions 124 and frees the entries associated with the execution of the microinstructions 126. In one embodiment, the microprocessor 100 can retire up to three ISA instructions 124 in a clock cycle. The advantage of this processing method is that the execution pipeline 112 is a high-performance, general-purpose execution engine that executes the microinstructions 126 of the microprocessor 100 microarchitecture that supports the x86 ISA and ARM ISA instructions 124.

Please refer to FIG. 5 , which is a block diagram illustrating the register file 106 of FIG. 1 in detail. According to a preferred embodiment, the register file 106 is a separate register block entity. In one embodiment, general purpose registers are implemented by a register file entity with multiple read and write ports; other registers may be physically independent of this general register file and others that access these registers but have more Adjacent functional blocks with fewer read and write ports. In one embodiment, some non-general purpose registers, especially those registers that do not directly control the hardware of the microprocessor 100 but only store values that the microcode 234 will use (such as some x86MSR or ARM coprocessor registers), then is implemented in a microcode 234 accessible private random access memory (PRAM). However, x86ISA and ARM ISA programmers cannot see this private random access memory, that is, this memory is not in the ISA system memory address space.

To sum up, as shown in FIG. 5 , the register file 106 is logically divided into three types, namely, ARM-specific registers 502 , x86-specific registers 504 , and shared registers 506 . In one embodiment, shared registers 506 include fifteen 32-bit registers shared by the ARM ISA registers R0 to R14 and x86ISA EAX to R14D registers, and sixteen 128-bit registers shared by the x86ISA XMM0 to XMM15 registers and the ARM ISA Advanced single instruction multiple data extension (Neon) registers are shared, and some of these registers overlap with thirty-two 32-bit ARM VFPv3 floating-point registers. As previously described in Figure 1, the sharing of general registers means that values written to a shared register by x86ISA instructions 124 will be seen by ARMISA instructions 124 when subsequently reading the shared register, and vice versa. The advantage of this method is that x86ISA and ARM ISA programs can communicate with each other through registers. In addition, as mentioned above, certain bits of the architecture control registers of the x86 ISA and the ARM ISA can also be referred to as shared registers 506 . As previously mentioned, in one embodiment, the x86-specific model registers are accessible by ARMISA instructions 124 through implementation-defined coprocessor registers, and are thus shared by the x86 ISA and the ARM ISA. This shared register 506 may include non-architectural registers, eg, non-architectural equivalents of conditional flags, which are also renamed by register configuration table 402 . The hardware instruction translator 104 knows which register is shared by the x86 ISA and the ARM ISA, and thus generates an execute microinstruction 126 to access the correct register.

ARM-specific registers 502 contain other registers defined by the ARM ISA but not included in shared registers 506 , while x86-specific registers 502 contain other registers defined by the x86 ISA but not included in shared registers 506 . For example, the ARM-specific registers 502 include the ARM program counter 116, CPSR, SCTRL, FPSCR, CPACR, co-processor registers, spare general-purpose registers for various exceptional event modes, saved program status registers (SPSRs), etc. Wait. The ARM-specific registers 502 listed above are not intended to limit the present invention, but are merely examples to illustrate the present invention. Additionally, x86-specific registers 504 include, for example, x86 instruction pointer (EIP or IP) 118, EFLAGS, R15D, the upper 32 bits of the 64-bit R0 through R15 registers (ie, the portion that does not fall within shared registers 506), Segment registers (SS, CS, DS, ES, FS, GS), x87FPU registers, MMX registers, control registers (such as CR0-CR3, CR8), etc. The x86 specific registers 504 listed above are not intended to limit the present invention, but are merely examples to illustrate the present invention.

In one embodiment, the microprocessor 100 includes new implementation-defined ARM coprocessor registers that can be accessed to perform x86 ISA-related operations when the instruction mode pointer 132 indicates the ARM ISA. operate. These operations include, but are not limited to: the ability to reset the microprocessor 100 to an x86 ISA processor (reset to x86 instructions); initialize the microprocessor 100 to an x86 specific state, switch the instruction mode pointer 132 to x86, And begin to fetch x86 instruction 124 (boot to x86 instruction) at a specific x86 target address; the ability to access the aforementioned global configuration registers; the ability to access x86 specific registers (such as EFLAGS), which are specified in the ARM In the R0 register, access to power management (such as P-state and C-state transitions), access to processor bus functions (such as input/output looping), access to the interrupt controller, and access to encryption acceleration functions. Additionally, in one embodiment, the microprocessor 100 includes new x86 non-architecture-specific model registers that can be accessed to perform ARM ISA-related operations when the instruction mode pointer 132 indicates the x86 ISA. These operations include, but are not limited to: the ability to reset the microprocessor 100 to an ARM ISA processor (reset to ARM instructions); initialize the microprocessor 100 to an ARM-specific state, and switch the instruction mode pointer 132 to ARM , and begin to retrieve the ability of ARM instruction 124 (start to ARM instruction) at a specific ARM target address; the ability to access the aforementioned global configuration registers; the ability to access ARM-specific registers (such as CPSR), which are specified in the in the EAX register.

Referring to FIGS. 6A and 6B , a flowchart is shown to illustrate the operation procedure of the microprocessor 100 of FIG. 1 . The process begins at step 602 .

As shown in step 602, the microprocessor 100 is reset. This reset operation may be performed by signaling the reset input of the microprocessor 100 . Additionally, in one embodiment, the microprocessor bus is an x86-style processor bus, and the reset operation can be performed by an x86-style INIT command. In response to this reset operation, the reset routine of microcode 234 is invoked to execute. The operation of the reset microcode includes: (1) initializing the x86-specific state 504 to the preset value specified by the x86 ISA; (2) initializing the ARM-specific state 502 to the preset value specified by the ARM ISA; (3) ) initialize the non-ISA specific state of the microprocessor 100 to the preset value specified by the manufacturer of the microprocessor 100; (4) initialize the shared ISA state 506, such as GPRs, to the preset value specified by the x86 ISA; and (5) The instruction mode pointer 132 and the environment mode pointer 136 are set to indicate x86ISA. In another embodiment, different from the preceding operations (4) and (5), the reset microcode initializes the shared ISA state 506 to ARM ISA-specific preset values, and resets the instruction mode pointer 132 and the environment mode pointer 136 is set to indicate the ARM ISA. In this embodiment, the operations of steps 638 and 642 need not be performed, and, prior to step 614, the reset microcode will initialize the shared ISA state 506 to the default value specified by the x86 ISA, and reset the instruction mode pointer 132 and ambient mode pointer 136 are set to indicate x86 ISA. Next, step 604 is entered.

At step 604, the reset microcode confirms whether the microprocessor 100 is configured as an x86 processor or an ARM processor to power on. In one embodiment, as described above, the default ISA boot mode is hard-coded in the microcode, but can be modified by blowing a configuration fuse, or using a microcode patch. In one embodiment, the default ISA boot mode is provided to the microprocessor 100 as an external input, such as an external input pin. Next, step 606 is entered. In step 606, if the default ISA boot mode is x86, the process goes to step 614; otherwise, if the default boot mode is ARM, the process goes to step 638.

In step 614, the reset microcode causes the microprocessor 100 to begin fetching the x86 instruction 124 at the reset vector address specified by the x86 ISA. Next, go to step 616 .

In step 616, x86 system software (eg, BIOS) configures microprocessor 100 to use instructions 124 such as x86 ISA RDMSR and WRMSR. Next, step 618 is entered.

In step 618, the x86 system software executes a reset to ARM instruction 124. This reset to ARM instruction causes the microprocessor 100 to reset and leave the reset procedure in the state of an ARM processor. However, since the x86-specific state 504 and the non-ISA-specific configuration state are not changed by the reset to ARM instruction 126, this approach facilitates the x86 system firmware to perform the initial setup of the microprocessor 100 and allow the microprocessor 100 to subsequently Rebooting in the state of the ARM processor while maintaining the non-ARM configuration of the microprocessor 100 executed by the x86 system software intact. In this way, the method can use the "small" micro-boot code to execute the boot procedure of the ARM operating system without using micro-boot code to solve the complicated problem of how to configure the microprocessor 100 . In one embodiment, the reset to ARM instruction is an x86WRMSR instruction to a new non-architecture specific model register. Next, step 622 is entered.

At step 622 , the simple instruction translator 204 enters a trap-to-reset microcode in response to the complex reset-to-ARM instruction 124 . This reset microcode initializes the ARM specific state 502 to the preset value specified by the ARM ISA. However, resetting the microcode does not modify the non-ISA specific state of the microprocessor 100, and thus facilitates saving the configuration settings required for the execution of step 616. Additionally, the reset microcode initializes the shared ISA state 506 to the default values specified by the ARM ISA. Finally, the microcode sets the instruction mode pointer 132 and the ambient mode pointer 136 to indicate the ARM ISA. Next, step 624 is entered.

In step 624, the reset microcode causes the microprocessor 100 to begin fetching the ARM instruction 124 at the address specified by the x86 ISA EDX:EAX registers. The process ends at step 624.

In step 638, the reset microcode initializes the shared ISA states 506, such as GPRs, to the default values specified by the ARM ISA. Next, step 642 is entered.

In step 642, the microcode sets the instruction mode pointer 132 and the ambient mode pointer 136 to indicate ARMISA. Next, step 644 is entered.

In step 644, the reset microcode causes the microprocessor 100 to begin fetching the ARM instruction 124 at the reset vector address specified by the ARM ISA. The ARM ISA defines two reset vector addresses and can be selected by an input. In one embodiment, the microprocessor 100 includes an external input to select between two ARM ISA-defined reset vector addresses. In another embodiment, microcode 234 includes a default selection between two ARM ISA-defined reset vector addresses, which may be modified by blowing fuses and/or microcode patching. Next, step 646 is entered.

In step 646, the ARM system software configures the microprocessor 100 to use specific instructions, such as the ARM ISA MCR and MRC instructions 124. Next, step 648 is entered.

In step 648, the ARM system software executes a reset to x86 instruction 124 to cause the microprocessor 100 to reset and exit the reset procedure in an x86 processor state. However, because the ARM-specific state 502 and the non-ISA-specific configuration state are not changed by the reset to x86 instruction 126, this approach facilitates the ARM system firmware to perform the initial setup of the microprocessor 100 and allow the microprocessor 100 to subsequently Rebooting in the state of an x86 processor while leaving the non-x86 configuration of the microprocessor 100 executed by the ARM system software intact. Thereby, the method can use the "small" micro-boot code to execute the boot procedure of the x86 operating system without using micro-boot code to solve the complicated problem of how to configure the microprocessor 100 . In one embodiment, the reset to x86 instruction is an ARM MRC/MRCC instruction to a new implementation-defined coprocessor register. Next, step 652 is entered.

In step 652, the simple instruction translator 204 enters a trap to reset microcode in response to the complex reset to x86 instruction 124. The reset microcode initializes the x86 specific state 504 to the default value specified by the x86 ISA. However, resetting the microcode does not modify the non-ISA-specific state of the microprocessor 100, which facilitates saving the configuration settings performed in step 646. Additionally, the reset microcode initializes the shared ISA state 506 to the default value specified by the x86 ISA. Finally, the microcode sets the instruction mode pointer 132 and the ambient mode pointer 136 to indicate the x86 ISA. Next, step 654 is entered.

In step 654, the reset microcode causes the microprocessor 100 to begin fetching the ARM instruction 124 at the address specified by the ARM ISA R1:R0 registers. The process ends at step 654.

Please refer to FIG. 7 , which is a block diagram illustrating a dual-core microprocessor 700 of the present invention. The dual-core microprocessor 700 includes two processing cores 100, and each core 100 includes the elements of the microprocessor 100 in FIG. 1, whereby each core can execute x86 ISA and ARM ISA machine language programs. The cores 100 can be configured such that both cores 100 execute x86 ISA programs, both cores 100 execute ARM ISA programs, or one core 100 executes x86 ISA programs and the other core 100 executes ARM ISA programs. During the operation of the microprocessor 700, the aforementioned three setting modes may be mixed and dynamically changed. As described in the description of FIGS. 6A and 6B , each core 100 has a preset value for its command mode pointer 132 and ambient mode pointer 136 , and the preset value can be modified by fuse or microcode patching, thereby , each core 100 can be independently changed to x86 or ARM processor through reset. Although the embodiment of FIG. 7 has only two cores 100, in other embodiments, the microprocessor 700 may have more than two cores 100, and each core may execute x86 ISA and ARM ISA machine language programs.

Please refer to FIG. 8 , which is a block diagram illustrating a microprocessor 100 capable of executing x86 ISA and ARM ISA machine language programs according to another embodiment of the present invention. The microprocessor 100 of FIG. 8 is similar to the microprocessor 100 of FIG. 1, and the element numbers therein are also similar. However, the microprocessor 100 of FIG. 8 also includes a microinstruction cache 892 that accesses the microinstructions 126 generated by the hardware instruction translator 104 and provided directly to the execution pipeline 112 . The microinstruction cache 892 is indexed by the fetch address generated by the instruction fetch unit 114 . If the fetch address 134 hits the microinstruction cache 892, a multiplexer (not shown) in the execution pipeline 112 selects the microinstruction 126 from the microinstruction cache 892 instead of the microinstruction 126 from the hardware instruction translator 104 On the contrary, the multiplexer selects the microinstructions 126 directly provided by the hardware instruction translator 104. The operation of microinstruction caching, also commonly referred to as trace caching, is a technique known in the art of microprocessor design. The advantage provided by the microinstruction cache 892 is that it generally takes less time to fetch the microinstruction 126 from the microinstruction cache 892 than to fetch the instruction 124 from the instruction cache 102 and translate it into a hardware instruction translator. The time of the microinstruction 126. In the embodiment of FIG. 8 , when the microprocessor 100 executes the x86 or ARM ISA machine language program, the hardware instruction translator 104 does not need to perform hardware translation every time the x86 or ARM ISA instruction 124 is executed, that is, when Execute microinstruction 126 already exists in microinstruction cache 892 and does not need to perform hardware translation.

The advantage of the embodiments of the microprocessor described herein is that it can execute x86ISA and ARM ISA machine language programs by translating x86ISA and ARM ISA instructions into microinstructions of the microinstruction set through a built-in hardware instruction translator. , this microinstruction set is different from the x86 ISA and ARM ISA instruction sets, and the microinstructions can be executed using the shared execution pipeline of the microprocessor to provide execution microinstructions. An advantage of the microprocessor embodiments described herein is that by cooperating with a large number of ISA-independent execution pipelines to execute microinstructions hardware translated from x86 ISA and ARM ISA instructions, the design and manufacture of the microprocessor requires The resources will be less than those required by two independently designed and manufactured microprocessors (ie, one capable of executing x86 ISA machine language programs and one capable of executing ARM ISA machine language programs). In addition, embodiments of these microprocessors, especially those using ultra-scalar out-of-order execution pipelines, have the potential to provide higher performance than existing ARMISA processors. In addition, these microprocessor embodiments also have the potential to provide higher performance on x86 and ARM implementations than systems using software translators. Finally, since the microprocessor can execute x86ISA and ARMISA machine language programs, the microprocessor facilitates the construction of a system that can efficiently execute both x86 and ARM machine language programs simultaneously.

Conditional Arithmetic and Logic Unit (CONDITIONAL ALU) Instructions

It would be desirable for a microprocessor to include in the instruction set the ability for instructions to be conditionally executed. Conditional execution of instructions means that the instruction specifies a condition (such as zero, or negative, or greater than), if the condition flag is met, the condition will be executed by the microprocessor, if the condition flag is not met, the condition will not be met. implement. As mentioned earlier, the ARM ISA provides this functionality not only to branch instructions, but also to most of the instructions in its instruction set. A conditionally executed instruction specifies a source operand from a general-purpose register to produce a result written to a general-purpose destination register. US Patent No. 7,647,480 to ARM Limited, of Cambridge, Great Britain describes a data processing apparatus for processing conditional instructions. Generally, a pipeline processing unit executes a conditional instruction to generate a resulting data value. The result data value displays the result of the calculation specified by the conditional instruction when the condition is satisfied, and displays the current data value stored in the destination register when the condition is not satisfied. Two possible solutions are described in the following paragraphs.

In the first solution, each conditional instruction in the instruction set is restricted to the register specified by the instruction condition is both the source register and the destination register. Using this method, conditional instructions occupy only two read ports of the register file, ie, provide the current destination register value as a source operand, and provide other source operands. Therefore, this first solution can further reduce the minimum number of register file read ports required to support the execution of conditional instructions by the pipeline processing unit.

The second solution removes the restriction on conditional instructions in the first solution, whereby conditional instructions can specify separate destination and source registers. The second solution requires an additional read port using the register file to be able to read the operand data values required by the conditional instruction (ie, source and destination operands from the register file) in a single cycle. Because the second solution requires not only the cost of an additional read port, but also a larger number of bits to specify conditional instructions and a more complex data path, US Pat. No. 7,647,480 chose the first solution for its target. Specifically, this data path needs to provide logic processing for the three input paths from the register file, and may also require steering logic to couple to any of the three paths.

An advantage of the embodiments presented here is that it enables conditional instructions to specify a source operand register other than the destination register and does not require the use of an additional read port in the register file. Generally speaking, in accordance with embodiments of the present invention, the hardware instruction translator 104 of the microprocessor 100 of FIG. 1 translates a conditional execution ISA instruction 124 into a sequence of one or more microinstructions 126 for execution by the execution pipeline 112 . The execution unit 424 executing the last microinstruction 126 of the sequence receives the original value of the destination register specified by the conditional instruction 124 to confirm whether the condition is satisfied. The previous microinstruction 126, or the last microinstruction 126 itself, performs an operation on the source operand to produce a result. If the condition is not met, the execution unit 424 executing the last microinstruction 126 in the sequence will write the original value back to the destination register instead of writing the resulting value to the destination register.

In an embodiment of the invention, the conditional ALU instruction is an ISA instruction 124 instructing the microprocessor 100 to perform an arithmetic or logical operation on more than one source operand to generate a result and write the result to a destination register. Other types of conditional instructions 124 may also be supported by the ISA instruction set of the microprocessor 100 , such as conditional branch instructions 124 or conditional load/store instructions 124 , which are distinct from conditional ALU instructions 124 .

The number and type of microinstructions 126 in the sequence sent by the hardware instruction translator 104 in response to an encountered conditional ALU instruction 124 is characterized by two characteristics. The first feature is whether the conditional ALU instruction 124 specifies that one of the source operands is to be subjected to a preshift operation. In one embodiment, the pre-shift operation includes, for example, the operations described on pages A8-10 to A8-12 of the ARM Architecture Reference Manual. If the conditional ALU instruction 124 specifies a preshift operation, the hardware instruction translator 104 generates a shift microinstruction 126 (designated SHF from FIG. 10 onwards) as the first microinstruction 126 in the sequence. The shift microinstruction 126 performs the preshift operation to generate a shift result written to a temporary register for use by subsequent microinstructions 126 in the sequence. The second feature is whether the destination register specified by the conditional ALU instruction 124 is also one of these source operand registers. If so, the hardware instruction translator 104 performs an optimization procedure to translate the conditional ALU instruction 124 into a conditional ALU instruction 124 that is one less number of microinstructions 126 than the one generated by the conditional ALU instruction 124 that does not specify the destination register as one of the source operand registers . This procedure is mainly described in Figures 21 to 28.

In addition, the conditional ALU instruction 124 specifies a condition that an architectural conditional flag must satisfy in order for the microprocessor 100 to execute the conditional ALU instruction 124. The conditional ALU instruction 124 specifies that the architectural condition flag needs to be updated with the result of the ALU operation and/or a carry flag generated by a preshift. However, if the condition is not met, the architectural condition flag will not be updated. Achieving this is rather complicated because the hardware instruction translator 104 needs to translate the conditional ALU instruction 124 into a sequence of microinstructions 126 . Specifically, if the condition is satisfied, at least one microinstruction 126 must write the new conditional flag value; however, the old value of the conditional flag may be used by the microinstruction 126 in the sequence to determine whether the conditional ALU instruction 124 specifies that conditions are met, and/or to perform an ALU operation. An advantage of these embodiments is that the microprocessor 100 employs techniques to ensure that the condition flag is not updated when the condition is not met, and that the flag is updated with the correct value when the condition is met, including using pre-shifting The carry flag value is updated.

In the embodiment of the microprocessor 100 of the present invention, as shown in FIG. 1 , the register file 106 for holding general registers has only enough read ports for the register file 106 to provide at most two source operands for execution. Execution unit 424 of microinstructions to implement conditional ALU instructions 124 . As previously disclosed corresponding to the description of FIG. 1 , the embodiment of the microprocessor 100 of the present invention is improved for a commercial microprocessor. The register file used to hold the general purpose registers of this commercial microprocessor has read ports only sufficient for the register file to provide up to two source operands to the execution unit, which executes what is referred to herein as microinstruction 126 to implement the conditional ALU instruction 124. Accordingly, the embodiments described herein are particularly advantageous for use in the microarchitecture of such commercial microprocessors. As mentioned earlier, corresponding to the description in Figure 1, the commercial microprocessor was originally designed as x86 ISA, and conditional execution of instructions is not a key feature, because the processor is based on accumulators and usually requires a source operand As a destination operand, therefore, the processor does not appear to need this additional read port.

An advantage of the embodiments described herein is that while in some instances there is an execution delay of two clock cycles associated with the execution of the two microinstructions translated by the conditional ALU instruction 124, in some instances , there will be an execution delay of three clock cycles associated with the execution of the two microinstructions translated by the conditional ALU instruction 124, but the operation performed by each microinstruction is relatively simple, and the implementation of the pipelined architecture can support Relatively high core clock frequency.

Although in the embodiments described herein, the microprocessor 100 is capable of executing ARM ISA and x86 ISA instructions, the invention is not limited thereto. Embodiments of the present invention are also applicable to situations where the microprocessor executes only a single ISA instruction. In addition, although in the embodiment described here, the microprocessor 100 translates the ARM ISA conditional ALU instruction into the microinstruction 126, this embodiment is also applicable to the microprocessor executing an ISA instruction different from the ARM, And also the case where conditional ALU instructions are included in its instruction set.

Please refer to FIG. 9 , which is a block diagram illustrating the microprocessor 100 of FIG. 1 in further detail. The microprocessor 100 includes an architectural condition flag register 926 in the register file 106 of FIG. 1 , and the microprocessor 100 also includes the execution unit 424 and the reorder buffer 422 of FIG. 4 . Condition flag register 926 stores architectural condition flags. In one embodiment, when the instruction mode pointer 132 indicates the ARM ISA, the condition flag register 926 stores the value according to the semantics of the ARM ISA condition flag, and when the instruction mode pointer 132 indicates the x86 ISA, the condition flag register 926 is according to the x86 ISA. The semantics of conditional flags, x86EFLAGS, store values. As described above in relation to FIG. 5, it is better to implement the register file 106 as an independent physical block composed of registers; in particular, for example, the condition flag register 926 may be a different register than a general-purpose register The physical register file of the register file. Thus, even though conditional flags are provided to execution unit 424 to execute microinstructions 126 as described below, the read port of the conditional flags register file may be a different read port from the general register file.

The condition flag register 926 outputs its condition flag value to a data input of a three-input multiplexer 922 . A second data input of the multiplexer 922 also receives the conditional flag result from the appropriate entry of the rearrangement buffer 422 . A third data input of the multiplexer 922 also receives the conditional flag result via a flag bus 928 . The multiplexer 922 selects the input of the appropriate data input as its output 924 provided to the execution unit 424 to execute the microinstruction 126 to read the condition flag. This process is described more clearly in subsequent paragraphs. Although this embodiment only describes a single flag bus 928, according to an embodiment of the present invention, each execution unit 424 capable of generating a conditional flag has its own flag bus 928, and each execution unit capable of reading a conditional flag Execution units 424 each have their own condition flag input 924 . Thus, various execution units 424 can concurrently execute various microinstructions 126 to read and/or write conditional flags.

Flag bus 928 is part of result bus 128 of FIG. 1 and is used to communicate conditional flag results output by execution unit 424 . The condition flag result is written to the reorder buffer 422, and more precisely, to the entry in the reorder buffer 422 that is allocated to the microinstruction 126 executed by the execution unit 424, and the result of the execution by the execution unit 424 is to the flag bus 928. The condition flag result is simultaneously transmitted to the third data input of the multiplexer 922 by the flag bus 928 .

FIG. 9 also shows, in block diagram form, the condition flag values output by execution unit 424 on condition bus 928 , and the condition flag values 924 received by execution unit 424 from multiplexer 922 . Condition flag values 928/924 include ISA condition flags 902, a Condition Satisfaction (SAT) bit 904, a Preshift Carry (PSC) bit 906, and a Use Shift Carry (USE) bit 908. When the instruction mode pointer 132 indicates ARM ISA, the ISA condition flags 902 include an ARM carry flag (C), a zero flag (Z), an overflow flag (V), and a negative flag (N). When the instruction mode pointer 132 indicates x86ISA, the ISA condition flags 902 include the x86EFLAGS carry flag (CF), zero flag (ZF), overflow flag (OF), sign flag (SF), parity flag (PF) ) and Auxiliary Flag (AF). Condition flag register 926 contains storage space provided for ISA condition flag 902 , SAT bit 904 , PSC bit 906 , and USE bit 908 . In one embodiment, the condition flags register 926 shares storage space for the x86 ISA and ARM ISA carry flags, zero flags, overflow flags, and negative/sign flags.

In addition to its basic operations (such as add, load/store, shift, Boolean sum, branch), each microinstruction 126 also indicates whether the microinstruction 126 performs one or more of the following three additional operations, which The operations are (1) read condition flags 926 (labeled RDFLAGS in the diagrams below in FIG. 10 ), (2) write condition flags 926 (indicated as WRFLAGS in the diagrams below in FIG. 10 ), and ( 3) A carry flag value is generated and written to the PSC bit 906 of the condition flag 926 (labeled WRCARRY in the diagrams below in Figure 10). In one embodiment, microinstructions 126 contain corresponding bits to indicate these three additional operations. In another embodiment, the microinstruction 126 indicates the three additional operations through the operation code of the microinstruction 126; action to indicate these three additional actions.

If an execution unit 424 executes a conditional ALU microinstruction 126 (in the diagrams below in FIG. 10, labeled ALUOP CC, CUALUOP CC, NCUALUOP CC) indicating its write condition flag 926 (labeled as WRFLAGS), it is executed by the execution unit. If the condition flag 924 read by 424 satisfies the condition specified by the microinstruction 126, the execution unit 424 will then set the SAT bit 904 to one; otherwise, the execution unit 424 will clear the SAT bit 904 to zero. Further, if any microinstruction 126 executed by the execution unit 424 instructs it to write the condition flag 926 and the microinstruction 126 is not a conditional ALU microinstruction 126, the execution unit 424 will then clear the SAT bit 904 to zero. Some conditional microinstructions 126 specify conditions based on ISA condition flags 902 (labeled as XMOV CC in the diagrams below in FIG. 10 ), while some conditional microinstructions 126 are based on SAT bits 904 (in the diagrams below in FIG. 10 ) marked as CMOV) to specify conditions, which are further explained in the following paragraphs.

If an execution unit 424 executes a shift microinstruction 126 instructing it to write the carry flag (labeled as WRCARRY), the execution unit 424 will then set the USE bit 908 to 1 and the shift microinstruction 126 generates The carry value is written to PSC bits 906; otherwise, execution unit 424 clears USE bits 908 to zero. Further, if an execution unit 424 executes any microinstruction 126 that instructs it to write the condition flag 926 and is not a shift microinstruction 126, the execution unit 424 will then clear the USE bit 908 to zero. The USE bit 908 is used by a subsequent conditional ALU microinstruction 126 to determine whether to update the architectural carry flag 902 with the value of the PSC bit value 906 or the carry flag generated based on the ALU operation performed by the conditional ALU microinstruction 126 The target value is updated. This operation is further explained in the following paragraphs. In another embodiment, the USE bit 908 is not present, but the hardware instruction translator 104 is used to directly generate the functional equivalent of the USE bit 908 as an indicator within the conditional ALU microinstruction 126 .

Please refer to FIG. 10 (including FIG. 10A and FIG. 10B ), which is a flowchart illustrating an embodiment of the operation of the hardware instruction translator 104 of FIG. 1 to translate the conditional ALU instruction 124 of the present invention. Basically, FIGS. 10A and 10B describe the manner in which the hardware instruction translator 104 decodes the conditional ALU instruction 124 to determine its type to translate it into the appropriate sequence of microinstructions 126 for execution by the execution pipeline 112 . Specifically, the hardware instruction translator 104 determines whether the conditional ALU instruction 124 updates the architectural condition flag 902, whether a pre-shift operation is performed on a source operand, whether the carry flag is used as an input to the ALU operation, and whether the ALU operation Is a carry update or a non-carry update operation. This operation, described further below, will indicate that the ALU operation updates only a subset of the framework condition flags 902 or updates all of the framework condition flags 902 . The process begins at step 1002.

At step 1002, hardware instruction translator 104 encounters a conditional ALU instruction 124, decodes it, and translates it into the appropriate sequence of microinstructions 126, as described in steps 1024, 1026, 1034, 1036, 1044, 1054, and 1056 . The conditional ALU instruction 124 instructs the microprocessor 100 to perform an arithmetic or logical operation on one or more source operands to produce a result and to write the result to the destination register. Some types of ALU operations specified by conditional ALU instructions 124 use the architectural carry flag 902 as input (eg, add with carry), although most types do not. The conditional ALU instruction 124 also specifies a condition corresponding to the architectural condition flag 902 of the ISA. If the architectural condition flag 902 satisfies the specified condition, the microprocessor 100 executes the conditional ALU instruction 124, that is, performs an ALU operation and writes the result to the destination register. Otherwise, the microprocessor 100 would treat the conditional ALU instruction 124 as a no-op instruction; in particular, the microprocessor 100 would not change the value in the destination register. Additionally, the conditional ALU instruction 124 may designate the architectural conditional flag 902 to be updated depending on the result of the ALU operation, or not to be updated. However, even if the conditional ALU instruction 124 specifies the architectural condition flag 902 to be updated, the microprocessor 100 will not change the value in the architectural condition flag 902 if the architectural condition flag 902 does not meet the specified condition. Finally, the conditional ALU instruction 124 may additionally designate one of the source operands of the ALU operation to be pre-shifted. Please refer to the description of step 1012 together. In one embodiment, the conditional ALU instructions 124 translated by the hardware instruction translator 104 are ARM ISA instructions. Specifically, in one embodiment, as shown in FIG. 10 , the ARM ISA data processing instructions and multiply instructions are translated by the hardware instruction translator 104 . In one embodiment, these instructions include, but are not limited to: AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, TST, TEQ, CMP, CMN, ORR, ORN, MOV, LSL, LSR, ASR, RRX , ROR, BIC, MVN, MUL, MLA, and MLS instructions. In steps 1024 , 1026 , 1034 , 1036 , 1044 , 1054 and 1056 , for the sake of illustration, the ARM ISA conditional ALU instruction 124 of the relevant type is shown in the first row, and the hardware instruction translator 104 translates the conditional ALU instruction 124 generated by Microinstructions 126 are displayed on subsequent lines. The subscript "CC" indicates that this instruction 124 is a conditional instruction. In addition, the type of ALU operation is exemplified by the specified source and destination operands. The programmer may designate a destination register to be the same as the register providing a source operand; in this case, hardware instruction translator 104 is configured to take advantage of this situation and optimize the sequence of microinstructions 126 to facilitate the execution of conditional ALU instructions 124. translate. This feature is described in Figure 21. Next, step 1004 is entered.

In step 1004 , the hardware instruction translator 104 determines whether the conditional ALU instruction 124 specifies the architectural condition flag 902 as requiring an update by the conditional ALU instruction 124 . That is, in some cases, the programmer may choose to update the conditional ALU instruction 124 of the architectural condition flag 902 according to the result of the ALU operation, while in other cases, the programmer may choose to update the conditional ALU instruction 124 regardless of the result of the ALU operation. , do not update the way the conditional ALU instruction 124 of the architectural conditional flag 902 is used. In the ARM ISA assembly language, the instruction subscript "S" indicates that the architectural condition flag 902 is to be updated, and the following diagrams in Figure 10 use this idiom. For example, step 1044 marks the ARM ISA conditional ALU instruction 124 as "ALUOP S" to indicate that the architectural conditional flag 902 is to be updated, and step 1024 marks the ARM ISA conditional ALU instruction 124 as "ALUOP" (ie , the difference is "S"), it means that the architectural condition flag 902 should not be updated. If the conditional ALU instruction 124 specifies the architectural condition flag 902 to be updated, flow proceeds to step 1042; otherwise, it proceeds to step 1012.

In step 1012, hardware instruction translator 104 determines whether the type of conditional ALU instruction 124 would specify a preshift operation for one of the operands of the ALU operation. The preshift operation can be performed from an immediate field to generate a constant source operand, or the preshift operation can be performed from a source operand provided from a register. The number of such preshift operations may be specified as a constant within the conditional ALU instruction 124 . Also, in the case of using register shift operands, the number of pre-shift operations can be specified by the value in the register. In the case of ARM ISA, an immediate value is pre-shifted according to an immediate shift amount to generate a constant source operand will be regarded as a modified immediate constant. The preshift operation produces a carry flag value. For some types of ALU operations, the architectural carry flag 902 is updated with the carry flag value generated by the shift operation, but for some types of ALU operations, the architectural carry flag 902 is updated by the ALU The value of the carry flag generated by the operation is updated. However, the carry flag value produced by the preshift operation is not used to confirm that the condition specified by the conditional ALU instruction 124 is satisfied, and more specifically, the current architectural carry flag 902 is used. It is worth noting that the ARM ISA MUL, ASR, LSL, LSR, ROR, and RRX instructions cannot specify a pre-shift operation, the processing of which will be described in steps 1024 , 1026 or 1044 . In addition, a preshift operation can be specified in the case where the MOV and MVN instructions specify a modified immediate constant operand, but in the case where the MOV and MVN instructions do not specify a modified immediate constant operand (ie, a register operand is specified) ), a pre-shift operation will not be specified, and its processing will be described in steps 1024, 1026 or 1044. As mentioned above, the preshift operation can be performed by an immediate field to generate a constant source operand, or the preshift operation can be performed by a source operand provided by a register. If the conditional ALU instruction 124 specifies a pre-shift operation, the flow proceeds to step 1032 ; otherwise, the flow proceeds to step 1022 .

In step 1022, the hardware instruction translator 104 determines whether the conditional ALU instruction 124 specifies an ALU operation using the carry flag. ARM ISA instructions 124 that use the carry flag, for example, include add with carry (ADC), reverse subtract with carry (RSC), and subtract with carry (subtract with carry, SBC) instruction, and an instruction that specifies a shift register operand and uses the carry flag to perform a shift operation, that is, an RRX shift type instruction. If the conditional ALU instruction 124 specifies an ALU operation using the carry flag, the flow proceeds to step 1026 ; otherwise, proceeds to step 1024 .

At step 1024, the hardware instruction translator 104 translates the non-flag update, non-preshift, non-use-carry conditional ALU instructions 124 into first and second microinstructions 126, namely (1) an ALU operation microinstruction 126 (designated ALUOP); and (2) a conditional move microinstruction 126 (designated XMOV). In one example of step 1024, the conditional ALU instruction 124 specifies a first source register (R1) and a second source register (R2), and performs an ALU operation on the first source register and the second source register (labeled as ALUOP) to generate a result, and a destination register (RD) to conditionally write the result. ALUOP microinstruction 126 and conditional ALU instruction 124 specify the same ALU and source operand. ALUOP microinstruction 126 performs an ALU operation on the two source operands and writes the result to a temporary register (designated T2). Conditional move microinstructions 126 specify the same state as conditional ALU instructions 124 . The conditional move microinstruction 126 receives the value written by the ALUOP microinstruction 126 in the scratch register and receives the old, or current, destination register (RD) value. Conditional move microinstructions 126 receive condition flags 924 and determine whether these flags satisfy the conditions. If the condition is met, the conditional move microinstruction 126 writes the temporary register value into the destination register (RD), otherwise it writes the old destination register value back to the destination register. It is worth noting that although the present embodiment specifies two source register operands, the present invention is not limited thereto, and one of these source operands may be a constant operand specified in the immediate field of a conditional ALU instruction 124, not provided by registers. The execution of microinstructions 126 is further illustrated in FIG. 20 . The term "old" as used in FIGS. 10A and 10B and subsequent figures refers to this flag or destination register value and, unless otherwise specified, refers to the value received by execution unit 424 when microinstruction 126 is executed. The foregoing description can also be expressed up to the current value. For destination registers, the old or current value system is received by the forwarding result bus of FIG. 1 , the rearrangement buffer 422 , or the architectural register file 106 . For flags, the old or current value is received by forwarding flag bus 928 , reorder buffer 422 , or architecture condition flag register 926 as described with respect to FIG. 9 . The process ends at step 1024.

In step 1026, the hardware instruction translator 104 translates the non-flag update, non-preshift, and carry-use conditional ALU instructions 124 into first and second microinstructions 126, namely (1) a carry-use ALU operation microinstruction 126 (designated ALUOPUC); and (2) a conditional move microinstruction 126 (designated XMOV). In one instance of step 1026, the conditional ALU instruction 124 is similar to that described for step 1024, except that the specified ALU operation uses the carry flag. The two microinstructions 126 are also similar to those described in step 1024; however, the ALUOPUC microinstruction 126 also receives the condition flag 924 to obtain the current value of the carry flag and applies it to ALU operations using carry. The execution of microinstructions 126 is detailed in FIG. 19 . The process ends at step 1026.

In step 1032, the hardware instruction translator 104 determines whether the conditional ALU instruction 124 specifies an ALU operation to use the carry flag. If the ALU operation uses the carry flag, the process proceeds to step 1036 ; otherwise, proceeds to step 1034 .

In step 1034, the hardware instruction translator 104 translates the non-flag update, pre-shift, non-carry conditional ALU instructions 124 into the first, second and third microinstructions 126, ie (1) a shift microinstruction 126 (designated SHF); (2) an ALU operation microinstruction 126; and (3) a conditional move microinstruction 126. In one example of step 134, the conditional ALU instruction 124 is similar to that described for step 1024; however, the conditional ALU instruction 124 also specifies a preshift operation with a shift amount on the second source operand (R2) , in the embodiment of step 1034 , the shift amount is stored in a third source register ( R3 ) specified by the conditional ALU instruction 124 . However, if the type of conditional ALU instruction 124 is to specify the shift amount as a constant within instruction 124, the third source register will not be used. This list of possible resulting preshift operations and conditional ALU instructions 124 may be specified as, but not limited to, logical shift left (LSL), logical shift right (LSR), arithmetic left shift ( arithmetic shift right (ASR), rotate right (ROR), and rotate right with extend (RRX). In one embodiment, the hardware instruction translator 104 outputs a shift microinstruction 126 to ensure that the shift values are generated according to the semantics of the ARM ISA, for example, in particular the ARM Architecture Reference Manual corresponding to individual ARM instructions. Description, and for example the content of pages A8-10 to A8-12, and A5-10 to A5-11. The shift microinstruction 126 and the conditional ALU instruction 124 specify the same pre-shift operation. The shift microinstruction 126 also specifies the same second source operand R2 and third source operand R3 as the conditional ALU instruction 124 . The shift microinstruction 126 performs a shift operation with a shift amount on the second source operand R2, and writes the result to a temporary register (labeled as T3). Although in step 1034 the conditional flag value generated by the shift microinstruction 126 is not used because the conditional ALU instruction 124 designates the architectural conditional flag 902 not to update, for example, in step 1056, the shift The shift flag values generated by the bit microinstruction 126 are used as described further in the following paragraphs. In addition, preshift operations may require rotating the old shift flag to the shifted result value; for example, extended right turn (RRX) preshift operations shift the carry indicator to the most significant bit in the result . In this case, although not shown in FIGS. 10A and 10B (except for step 1056 ), the shift microinstruction 126 also reads the condition flag 924 to obtain the current carry flag value. ALUOP microinstruction 126 is similar to that described in step 1024; however, this ALUOP microinstruction 126 receives the value of temporary register T3 instead of second source operand R2, and performs an ALU operation on first source operand R1 and temporary Register T3 is written to temporary register T2 with the result. The XMOV microinstruction 126 is similar to that described for step 1024. The execution of microinstructions 126 is described in more detail in FIG. 18 . The process ends at step 1034.

In step 1036, the hardware instruction translator 104 translates the non-flag update, preshift, and carry-use conditional ALU instruction 124 into the first, second and third microinstructions 126, ie (1) a shift microinstruction instruction 126; (2) a use carry ALU operation microinstruction 126; and (3) a conditional move microinstruction 126. In the example of step 1036, the conditional ALU instruction 124 is similar to that described in step 1034, except that the ALU operation specified by this instruction 124 uses the carry flag. The three microinstructions 126 are similar to those described in step 1034; however, the ALUOPUC microinstruction 126 also receives the condition flag 924 to obtain the current value of the carry flag for use in carry using the ALU operation. The execution of microinstructions 126 is described in more detail in FIG. 17 . The process ends at step 1036.

At step 1042, hardware instruction translator 104 determines whether the type of conditional ALU instruction 124 specifies a pre-shift for one of the ALU operands. If the conditional ALU instruction 124 specifies a pre-shift, the flow proceeds to step 1052 ; otherwise, the flow proceeds to step 1044 .

In step 1044, the hardware instruction translator 104 translates the flag update, non-preshifted conditional ALU instruction 124 into the first and second microinstructions 126, namely: (1) a conditional ALU operation microinstruction 126 (marked and (2) a conditional move microinstruction 126 (labeled as CMOV). In the example of step 1044, the conditional ALU instruction 124 is similar to the conditional ALU instruction 124 of step 1024, except that the architectural condition flag 902 is updated in this embodiment. Conditional ALU microinstruction 126 and conditional ALU instruction 124 specify the same conditions and source operands. Conditional ALU operation microinstruction 126 performs an ALU operation on the two source operands and writes the result to a temporary register (labeled T2). In addition, the conditional ALU operation microinstruction 126 receives the architectural condition flag 902 and confirms whether it satisfies the condition. Additionally, the conditional ALU operation microinstruction 126 writes to the conditional flags register 926 . Specifically, the conditional ALU operation microinstruction 126 writes the SAT bit 904 to indicate whether the architectural condition flag 902 is satisfied. In addition, if the condition is not satisfied, the conditional ALU operation microinstruction 126 writes the old conditional flag value into the architectural conditional flag 902; otherwise, if the condition is satisfied, the conditional ALU operation microinstruction 126 updates the architectural conditional flag according to the result of the ALU operation Mark 902. The update value of this architectural condition flag 902 is related to the type of ALU operation. That is, for some types of ALU operations, all the architectural condition flags 902 are updated with new values according to the results of the ALU operations; conversely, for some types of ALU operations, some architectural condition flags 902 (in one embodiment) , the Z and N flags) are updated with new values according to the result of the ALU operation, but the old values are reserved for other architectural condition flags 902 (in one embodiment, the V and C flags). The updating of the architectural condition flags 902 is described in more detail in FIG. 14 . The conditional move (CMOV) microinstruction 126 receives the value written to the temporary register (T2) by the ALUOP microinstruction 126 and receives the old or current value of the destination register (RD). The conditional move (CMOV) microinstruction 126 receives the conditional flag 924 and checks the SAT bit 904 to determine whether the conditional ALU operation microinstruction 126 indicates that the architectural conditional flag 902 satisfies the condition. If the condition is met, the conditional move (CMOV) microinstruction 126 writes the temporary register value to the destination register, otherwise the old destination register value is written back to the destination register. The execution of microinstructions 126 is described in more detail in FIG. 14 . It is worth noting that the ALU operation performed by the conditional ALU operation microinstruction 126 generated in step 1044 (and steps 1054 and 1056) may be an ALU operation using a conditional flag (similar to that described in steps 1026 and 1036). , and since microinstruction 126 reads flags (eg, the RDFLAGS pointer), execution unit 424 has a carry flag to perform this use-carry ALU operation. The process ends at step 1044.

In step 1052, the hardware instruction translator 104 determines whether the conditional ALU instruction 124 specifies an ALU operation of the type that would update the architectural carry flag 902. It is necessary for the hardware instruction translator 104 to distinguish whether the architectural carry flag 902 will be updated, because if the ALU operation does not update the architectural carry flag 902, the carry flag value generated by the preshift operation is not based on the ALU The condition flag value generated by the operation must be used to update the architectural carry flag 902 . In one embodiment, ARM ISA instructions 124 that specify an ALU operation that does not update the architectural carry flag 902, but specify a pre-shift operation, include but are not limited to AND, BIC, EOR, ORN, ORR, TEQ, and TST , and MOV/MVN instructions 124, which also specify an adjusted immediate constant by a non-zero rotation value. If the ALU operation updates the frame carry flag 902 , the process proceeds to step 1054 ; otherwise, proceeds to step 1056 .

In step 1054, the hardware instruction translator 104 translates the conditional ALU instructions 124 used for flag update, preshift, and carry into the first, second and third microinstructions 126, namely: (1) a shift microinstruction instruction 126; (2) a conditional carry update ALU operation microinstruction 126 (labeled as CU ALUOP CC); and (3) a conditional move microinstruction 126. In one example of step 1054, the conditional ALU instruction 124 is similar to that described for step 1034; however, this conditional ALU instruction 124 also specifies the architectural condition flag 902 to be updated. The shift microinstruction 126 is similar to that described for step 1034. The conditional carry-update ALU operation microinstruction 126 and the conditional ALU instruction 124 specify the same conditions. The conditional carry update ALU operation microinstruction 126 performs an ALU operation on the first source operand R1 and the temporary register T3, and writes the result to a temporary register (labeled as T2). In addition, the conditional carry update ALU operation microinstruction 126 receives the architectural condition flag 902 and confirms whether it satisfies the condition. In addition, the conditional carry update ALU operation microinstruction 126 is written to the conditional flags register 926 . Specifically, the conditional carry update ALU operation microinstruction 126 writes to the SAT bit 904 to indicate whether the architectural condition flag 902 satisfies the condition. In addition, if the condition is not satisfied, the conditional carry update ALU operation microinstruction 126 writes the old condition flag value into the architectural condition flag 902; otherwise, if the condition is satisfied, the conditional carry update ALU operation microinstruction 126 is based on the result of the ALU operation to update the architectural condition flags 902. The updating of the architectural condition flags 902 is described in more detail in FIG. 16 . The conditional move (CMOV) microinstruction 126 is similar to that described for step 1044. The process ends at step 1054.

In step 1056, the hardware instruction translator 104 translates the flag update, preshift, and non-carry update conditional ALU instructions 124 into the first, second and third microinstructions 126, ie (1) a shift microinstruction instruction 126; (2) a conditional non-carry update ALU operation microinstruction 126 (labeled as NCUALUOP CC); and (3) a conditional move microinstruction 126. In the example of step 1056, the conditional ALU instruction 124 is similar to that described in step 1054; however, the conditional ALU instruction 124 specifies a non-carry update ALU operation. Therefore, when the condition is met, the architectural carry flag 902 is updated with the pre-shift flag value. The shift microinstruction 126 is similar to that described in step 1034; however, the microinstruction 126 reads and writes the condition flags register 926. Specifically, the shift microinstruction 126 will: (1) write the conditional flag value generated by the preshift operation into the PSC bit 906; (2) set the USE bit 908 to indicate the conditional non-carry update ALU operation microinstruction Instruction 126 uses PSC 906 to update the architectural carry flag 902; and (3) writes the old architectural condition flag 902 back to the condition flags register 926, whereby the conditional non-carry update ALU operation microinstruction 126 can evaluate the architectural condition flag The old value of 902 to confirm whether it satisfies the condition. Conditional non-carry update ALU operation microinstructions 126 and conditional ALU instructions 124 specify the same conditions. The conditional non-carry update ALU operation microinstruction 126 performs an ALU operation on source operand R1 and temporary register T3 and writes the result to a temporary register (labeled as T2). Furthermore, the conditional non-carry update ALU operation microinstruction 126 receives the architectural condition flag 902 and confirms whether it satisfies the condition. Additionally, the conditional non-carry update ALU operation microinstruction 126 is written to the condition flags register 926 . Specifically, the conditional non-carry update ALU operation microinstruction 126 is written to the SAT bit 904 to indicate whether the architectural condition flag 902 is satisfied. In addition, if the condition is not satisfied, the conditional non-carry update ALU operation microinstruction 126 writes the old condition flag value into the architectural condition flag 902; otherwise, if the condition is satisfied, the conditional non-carry update ALU operation microinstruction 126 is based on The architectural condition flags 902 are updated as a result of the ALU operation. Specifically, the architectural overflow (V) flag 902 is written with the old overflow flag value. In addition, the architectural carry flag 902 is updated with the pre-shifted carry flag value at PSC bit 906 under the direction of USE bit 908, and the old carry flag value 924 otherwise. The updating of the architectural condition flags 902 is described in more detail in FIG. 15 . The CMOV microinstruction 126 is similar to that described for step 1044. In another embodiment, the USE bit 908 is not present, and the hardware instruction translator 104 directly generates the functional equivalent of the USE bit 908 as a pointer to the conditional non-carry update ALU operation microinstruction 126. Execution unit 424 checks this pointer to determine whether to update the architectural carry flag 902 with the pre-shifted carry flag value at PSC bit 906 or with the old carry flag value 924 . The process ends at step 1056.

In one embodiment, the hardware instruction translator 104 is configured to generate and provide an adjusted immediate constant rather than outputting a shift microinstruction 126 to do this. In this embodiment, the processing procedure is similar to that described for steps 1024, 1026 and 1044, rather than steps 1034, 1036 and 1054/1056. Furthermore, in this embodiment, the hardware instruction translator 104 also generates and provides the carry flag value by the pre-shift operation for the conditional ALU operation microinstruction 126 to update the architectural carry flag 902 .

Please refer to FIG. 11 , which is a flowchart showing the operation of executing a shift microinstruction 126 by the execution unit 424 of FIG. 4 of the present invention. The process begins at step 1102.

In step 1102, one of the execution units 424 of FIG. 4 receives a shift microinstruction 126, such as the microinstruction described in FIG. 10 and generated by the hardware instruction translator 104 in response to the encountered conditional ALU instruction 124 instruction. The execution unit 424 also receives source operands specified by the microinstruction 126 , including condition flag values 924 that may or may not be used by the microinstruction 126 . Next, proceed to step 1104 .

In step 1104, the execution unit 424 executes the shift operation specified by the shift microinstruction 126 on the operand specified by the shift microinstruction 126 to produce a result, and converts the result to Output to result bus 128 . In one embodiment, such shift operations may include, but are not limited to, a logical left (LSL), logical right (LSR), arithmetic right (ASR), right turn (ROR), and extended right (RRX) . In addition, the execution unit 424 generates a new conditional flag value based on the result of the shift operation. Specifically, the execution unit 424 generates a carry flag value based on the result of the shift operation. In one embodiment, in the case of a logical left (LSL) shift operation, the carry flag value is the Nth bit of an extended value, which is the M least significant bit zero concatenation Left-shifted operand (Mleast significant bit zeroes concatenated with the operand being left-shifted), where N is the number of bits in the original operand and M is the specified positive shift amount; shift in logical right (LSR) In the case of operation, the carry flag value is the (M-1)th bit of an extended value, and this extended value is zero-extended (M+N) bits of the original operand, where M is the specified positive shift amount, N is the number of bits of the original operand; in the case of an arithmetic right (ASR) shift operation, the carry flag value is the (M-1)th bit of an extended value that is sign-extended from the original operand (sign-extended)(M+N) bits, where M is the specific positive shift amount and N is the number of bits of the original operand; in the case of a right-turn (ROR) shift operation, the carry flag value coefficient operation The (N-1)th bit of the result after turning right, this operand is right-turned according to the specified non-zero shift amount modulo (mod) N, where N is the original operand The number of bits; in the case of an extended right (RRX) shift operation, the carry flag value is the bit zero of the original operand. Next, proceed to step 1106 .

In step 1106, the execution unit 424 determines whether the shift microinstruction 126 output by the hardware instruction translator 104 indicates that the execution unit 424 should write the carry flag, as in the instruction WRCARRY in step 1056 of FIG. 10B. Specifically, the shift microinstruction 126 indicates that the PSC bit 906 at the flag bus output 928 should be written with the carry flag value generated by the shift operation, and the USE bit 908 should be set so that subsequent The conditional non-carry update ALU operation microinstruction 126 takes effect to conditionally write the PSC bit 906 value to the architectural carry flag 902 . If the execution unit 424 should write the carry flag, the flow proceeds to step 1114 ; otherwise, the flow proceeds to step 1108 .

In step 1108, the execution unit 424 determines whether the shift microinstruction 126 output by the hardware instruction translator 104 indicates that the execution unit 424 should write a condition flag (labeled as WRFLAGS). Although none of the shift microinstructions in FIG. 10 indicate that the execution unit 424 should write the condition flag without the shift microinstruction 126 indicating that the PSC bit 906 (labeled WRCARRY) should be written, the hardware instruction translator This shift microinstruction 126 will still be generated by 104 when translating other ISA instructions 124 . If the execution unit 424 should write the condition flag, the flow proceeds to step 1112; otherwise, it terminates.

At step 1112, the execution unit 424 outputs a value on the flag bus 928 to clear the PSC bit 906, USE bit 908, and SAT bit 904 to zero, and writes the new frame condition flag 902 value generated at step 1104 into the frame Conditional flags 902 . The process ends at step 1114.

At step 1114, execution unit 424 outputs a value on flag bus 928 to write the carry flag value generated at step 1112 into PSC bit 906, set USE bit 908 to one, clear SAT bit 904 to zero, and start with The old frame condition flag 902 received in step 1102 is written into the numerical frame condition flag 902 . The process ends at step 1114.

Please refer to FIG. 12 (including FIG. 12A and FIG. 12B ), which shows a flowchart describing the operation of the execution unit 424 of FIG. 4 to execute a conditional ALU microinstruction 126 of the present invention. The process begins at step 1202.

In step 1202 , one of the execution units 424 of FIG. 4 receives a conditional ALU microinstruction 126 , as described in FIG. 10 , in the case of the microinstruction generated by the hardware instruction translator 104 in response to an encountered conditional ALU instruction 124 . The execution unit 424 also receives the source operand specified by the microinstruction, including the conditional flag value 924, whether or not it will be used by the microinstruction 126. It should be understood that the execution unit 424 also executes the unconditional ALU microinstruction 126 according to the processing procedure similar to that described in FIG. 12 , excluding the execution operations of steps 1209 , 1212 , 1214 and 1216 . The microinstruction may be Figure 10 illustrates the conditional microinstructions generated by the hardware instruction translator 104 in response to encountering a conditional ALU instruction 124. In addition, the execution unit 424 that executes the conditional ALU microinstruction 126 and the execution unit 424 that executes the associated shift microinstruction 126 and/or the XMOV/CMOV microinstruction 126 may be the same or different. Next, the flow proceeds to step 1204 .

At step 1204 , the execution unit 424 performs the ALU operation specified by the conditional ALU microinstruction 126 on the operand specified by the conditional ALU microinstruction 126 to generate a result and output the result to the result bus 128 . In addition, the execution unit 424 also generates a new value of the architectural condition flag 902 based on the result of the ALU operation. If the ALU operation uses the carry flag, the execution unit 424 uses the old value of the received architectural carry flag 924 instead of the new carry flag value generated by the ALU operation. Next, the flow proceeds to step 1206 .

In step 1206, the execution unit 424 confirms whether the architectural condition flag 924 received by the step 1202 satisfies the specified condition. This confirmation result will be used in subsequent steps 1212 and 1214 . Next, the flow proceeds to step 1208 .

In step 1208, execution unit 424 determines whether conditional ALU microinstruction 126 instructs execution unit 424 to write to conditional flags register 926, as in the instruction WRFLAGS in many of the steps of Figures 10A and 10B. If so, the process proceeds to step 1214; otherwise, the process proceeds to step 1209.

In step 1209 , if the result confirmed in step 1206 is that the condition is satisfied, the process proceeds to step 1211 ; otherwise, the process proceeds to step 1212 .

In step 1211 , since the condition is satisfied, the execution unit 424 outputs the result generated in step 1204 to the result bus 128 . However, the conditional ALU microinstruction 126 does not update the conditional flag register 926 because the conditional ALU microinstruction 126 is designated not to update the architectural conditional flag 902 . As previously described, the result and condition flag values output by the execution unit 424 to the result bus 128/928 are passed to the other execution units 424 of the execution pipeline 112 and written to the rearrangement buffer 422 relative to the conditional ALU microinstruction 126 project. It should be understood that even though the microinstruction 126 is designated not to update the architectural condition flag 902, the execution unit 424 still outputs some value to the flag result bus 928 to write to the rearrangement buffer 422 relative to the conditional ALU microinstruction 126. items, but these values will not be retired by the rearrangement buffer 422 to the destination register 106 and/or the condition flag register 926. That is to say, the confirmation of whether the value of the entry written to the rearrangement register 422 will eventually be retired is performed by the retirement unit of the execution pipeline 112 based on the type of the microinstruction 126, the occurrence of an exception event, a branch misprediction, or other Invalidation events are performed, rather than by the execution unit 424 itself. The process ends at step 1211.

In step 1212 , the execution unit 424 outputs the first source operand to the result bus 128 . It is worth noting that the various conditional ALU microinstructions 126 described in FIGS. 10A and 10B do not use this output first source operand when the condition is not satisfied. Specifically, the XMOV and CMOV microinstructions 126 of Figures 10A and 10B write back the old destination register value instead of the temporary register T2 value. However, in the descriptions of FIGS. 21A and 21B and subsequent figures, for the translation of conditional ALU instructions 124 in other formats, that is, the same source and destination conditional ALU instructions 124 (or other ISA instructions 124 ), the hardware instruction translator 104 When the conditional ALU microinstruction 126 is generated, the first source operand is also the destination register specified by the ISA instruction 124, so as to write back the value of the original destination register when the condition is not satisfied. As described in step 1211, the conditional ALU microinstruction 126 does not update the conditional flags register 926 because the conditional ALU microinstruction 126 is designated not to update the architectural conditional flags 902. The process ends at step 1212.

In step 1214 , if the conditions confirmed in step 1206 are satisfied, the process proceeds to step 1218 ; otherwise, the process proceeds to step 1216 .

In step 1216, execution unit 424 outputs the first source operand, clears USE bit 908, PSC bit 906, and SAT bit 904 to zero, and outputs the old architecture condition flag 924 value received in step 1202 to the flag bus 928, so that the conditional ALU instruction 124 as a whole can be regarded as a no-operation instruction to be executed (ie, the conditional ALU instruction 124 is not executed) without adjusting the value of the architectural condition flag 902. The process ends at step 1216.

In step 1218, execution unit 424 determines whether conditional ALU microinstruction 126 specifies a carry-update ALU operation. In one embodiment, the execution unit 424 decodes the opcode of the conditional ALU microinstruction 126 to make a validation result. In another embodiment, the hardware instruction translator 104 determines whether the ALU operation is the carry-update operation of step 1052 of FIG. 10A and provides a pointer to the execution unit 424 accordingly. In one embodiment, non-carry update ALU operations include, but are not limited to, operations performed by AND, BIC, EOR, ORN, ORR, TEQ, TST, MUL, MOV, MVN, ASR, LSL, LSR, ROR, and RRX ARM ISA instructions 124 the specified action. If the ALU operating system is a carry update operation, the process proceeds to step 1222 ; otherwise, the process proceeds to step 1224 .

At step 1222, the execution unit 424 outputs the result generated in step 1204, clears the USE bit 908 and the PSC bit 906 to zero, sets the SAT bit 904 to one, and outputs the new architecture condition flag value generated in step 1204 to the flag bus 928. It is worth noting that the processing of conditional ALU microinstructions 126 that do not update the overflow flag but specify a carry-update ALU operation (such as ASR, LSL, LSR, ROR, and RRX operations) is slightly different from that described in step 1222 . In particular, execution unit 424 outputs the old VFlag value instead of the new VFlag value. The process ends at step 1222.

At step 1224, the execution unit 424 checks the USE bit 908. If the USE bit 908 is set to one, the flow proceeds to step 1228; otherwise, the flow proceeds to step 1226. In another embodiment, as described above/below, the USE bit 908 is not present, and the execution unit 424 checks the pointer in the conditional ALU microinstruction 126 to determine whether to carry with the pre-shift in the PSC bit 906 Flag value to update the architectural carry flag 902, or use the old carry flag value 924.

In step 1226, execution unit 424 outputs the result generated in step 1204, clears USE bit 908 and PSC bit 906 to zero, sets SAT bit 904 to one, and outputs an architectural condition flag to flag bus 928 in the following manner: C The flags and V flags are written with the old C flag and V flag values received in step 1202; the N flag and Z flag are written with the new N flag and Z flag generated in step 1204, respectively Write the value. The process ends at step 1226.

In step 1228, execution unit 424 outputs the result generated in step 1204, clears USE bit 908 and PSC bit 906 to zero, sets SAT bit 904 to one, and outputs an architectural condition flag to flag bus 928 in the following manner: C Flag is written to the value of PSC bit 906 received in step 1202; V flag is written to the old V flag value received in step 1202; The N flag and Z flag values of . The process ends at step 1228.

In one embodiment, the value output on the flag bus 928 is different depending on whether the instruction mode pointer 132 indicates x86 or ARM. Therefore, the execution unit 424 executes the conditional ALU microinstruction 126 in different ways. Specifically, if the instruction mode pointer 132 indicates x86, the execution unit 424 does not distinguish whether the ALU operating mode is carry-update or non-carry-update, ignores the USE bit 908, and uses x86 semantics to update the condition code flags.

Please refer to FIG. 13 , which shows the operation of executing a conditional move microinstruction 126 by the execution unit 424 of FIG. 4 of the present invention. The process starts at step 1302.

At step 1302, one of the execution units 424 of FIG. 4 receives a conditional move microinstruction 126, a microinstruction (labeled as CMOV) generated by the hardware instruction translator 104 in response to encountering a conditional ALU instruction 124 as described in FIG. 10 . or XMOV). The execution unit 424 also receives the source operand specified by the microinstruction 126 , including the conditional flag value 924 , whether or not it will be used by the microinstruction 126 . Next, proceed to step 1304 .

At step 1304 , the execution unit 424 decodes the microinstruction 126 to determine whether it is an XMOV microinstruction 126 or a microinstruction 126 . If it is the CMOV microinstruction 126, the flow proceeds to step 1308; otherwise, the flow proceeds to step 1306.

At step 1306, the execution unit 424 validates the architectural condition flag 902 received at step 1302 and confirms whether the condition is satisfied. Next, proceed to step 1312.

At step 1308, the execution unit 424 examines the SAT bit 904 received by step 1302 and verifies that the condition is satisfied, as previously done by the corresponding conditional ALU microinstruction 126 that wrote the SAT bit 904, as shown in Figure 10 Steps 1044, 1054, and 1056 are described. Next, the flow proceeds to step 1312 .

At step 1312, if the conditions confirmed by step 1306 or 1308 are satisfied, the flow proceeds to step 1316; otherwise, it proceeds to step 1314.

At step 1314 , the execution unit 424 outputs the value of the first source operand to the result bus 128 . In FIG. 10, the value of the first source operand is the value of the old destination register, so that the conditional ALU instruction 124 as a whole can be regarded as a no-operation under the condition that the condition is not satisfied and the value of the destination register is not changed. instruction (ie, without executing the conditional ALU instruction 124). The process ends at step 1314.

In step 1316 , the execution unit 424 outputs the value of the second source operand to the result bus 128 . As shown in FIG. 10, the value of the second source operand is written into the temporary register by the relevant conditional ALU microinstruction 126, so that when the preset condition is satisfied, the result is written into the destination register to Assists in the execution of conditional ALU instructions 124 . The process ends at step 1316.

Please refer to FIG. 14 , which is a block diagram showing the operation of the execution pipeline 112 of FIG. 1 to execute a conditional ALU instruction 124 of the present invention. Specifically, the conditional ALU instruction 124 is a flag update, non-preshift, conditional ALU operation ISA instruction 124. The hardware instruction translator 104 translates the instruction 124 into the microinstruction 126 of step 1044 of FIG. 10 . The register configuration table 402 of FIG. 4 generates auxiliary information to the CMOV microinstruction 126 located in the temporary register T2, the value of the condition flag register 926 written by the conditional ALUOP microinstruction 126, and so on. The instruction scheduler 404 dispatches the microinstructions 126 to the appropriate reservation stations 406 in FIG. 4 . When the values of all source operands are available to the microinstruction 126 (whether from the forwarding bus 128 , the rearrangement buffer (ROB) 422 , or the register file 106 ), the instruction issue unit 408 acknowledges a microinstruction 126 Ready to be sent by its reservation station 406 to the corresponding execution unit for execution. The microinstruction 126 is executed according to the description of FIG. 12 (including FIG. 12A and FIG. 12B ) and FIG. 13 .

Execution unit 424 receives the conditional ALUOP microinstruction 126 generated in step 1044 from reservation station 406, the value of the source operand from registers R1 and R2 of register file 106 of FIG. 1, and the conditional value of FIG. 9 according to step 1202 of FIG. Flags register 926 (or from steering bus 128 and/or ROB 422) receives condition flags 924. The execution unit 424 performs an ALU operation on the registers R1 and R2 (if the ALU operation uses a carry operation, the operation is performed on the received C flag 902 ) to generate a result, which is written to the temporary register T2 according to step 1204 . In addition, (1) if the architectural condition flag 902 does not satisfy the specified condition (marked as NOT SATISFIED in FIG. 14 ), the execution unit 424 generates a new value of the condition flag 928 to write the condition flag according to step 1216 in FIG. 12B (2) If the architecture condition flag 902 satisfies the specified condition and the ALU operation is a non-carry update operation (marked as NCUALUOP SAT in FIG. 14 ), the execution unit 424 generates a new condition according to step 1226 in FIG. 12 and (3) if the architectural condition flag 902 satisfies the specified condition and the ALU operating system is a carry-update operation (labeled CU ALUOP SAT in FIG. 14 ), the execution unit 424 A new condition flag 928 value is generated to write to the condition flag register 926 according to step 1222 of FIG. 12 . The value of the temporary register T2 and the condition flag 928 are provided on the steering bus 128 for use by the CMOV microinstruction 126, the entry written to the rearrangement buffer 422 if not from the steering bus 128 is used by the CMOV microinstruction 126, and Not from the steering bus 128 or the rearrangement buffer 422, except in the event of an exception occurrence, branch misprediction, or other invalid event eventual retirement to the appropriate architectural state utilized by the CMOV microinstruction 126. In particular, the multiplexer 922 of FIG. 9 provides the operation to select the appropriate condition flag 924 to the execution unit 424.

The execution unit 424 receives the CMOV microinstruction 126 of step 1044 , the source operand values of the temporary register T2 and the destination register (RD), and the condition flag 924 generated according to the step 1302 of FIG. 13 . According to steps 1316 and 1314 of FIG. 13, when the SAT bit 904 is set, the execution unit 424 outputs the value of the source operand of the temporary register T2, and when the SAT bit 904 is cleared, the execution unit 424 outputs the source operation of the destination register RD number value. The resulting value is provided on the steering bus 128 for use by subsequent microinstructions 126, written to the entries in the rearrangement register 422, and finally retired to its The appropriate architectural state is utilized by microinstructions 126 .

As described in step 1222, the flag update condition ALU instruction 124 specifies a carry update ALU operation, but does not update the overflow flag, such as the ARM ISA ASR, LSL, LSR, ROR, and RRX instructions 124, and the processing procedures of these instructions 124 It is slightly different from that shown in Figure 14. In particular, execution unit 424 outputs the old VFlag value instead of the new VFlag value. Finally, as mentioned above, the flag update ARM ISA MUL and MOV/MVN (register) instructions 124 are both non-carry update instructions and cannot specify a pre-shift operation, so the procedure of step 1044 is performed. This is more explicitly described at step 1226 of Figure 12B.

It can be found in the foregoing that the ALU operation microinstruction 126 indicates through the SAT bit 904 whether the old condition flag 902 of the CMOV microinstruction 126 satisfies the specified condition, so that the ALU operation microinstruction 126 replaces the old value of the conditional flag 902, and When the conditions are met, processing is performed according to the appropriate value generated by the ALU operation result.

Please refer to FIG. 15 (including FIG. 15A and FIG. 15B ), which is a block diagram illustrating the execution of a conditional ALU instruction 124 by the execution pipeline 112 of FIG. 1 of the present invention. Specifically, the conditional ALU instruction 124 is a flag update, pre-shift, non-carry update conditional ALU operation ISA instruction 124, and the hardware instruction translator 104 translates this instruction 124 into the microcomputer shown in step 1056 of FIG. 10B. Instruction 126. The operations in FIG. 15 (including FIG. 15A and FIG. 15B ) are similar to the operations in FIG. 14 in many aspects, and similar operations are not repeated here, and only the differences are listed below. The register configuration table 402 of FIG. 4 generates auxiliary information to the NCUALUOP microinstruction 126 located in the temporary register T3, the value of the condition flags register 926 written by the shift microinstruction 126, and so on. Microinstructions 126 are executed as described in Figures 11, 12 and 13.

The execution unit 424 receives the shift microinstruction 126 generated in step 1056 from the reservation station 406, the source operand value from registers R2 and R3 of the register file 106, and the condition flag from the condition flag register 926 according to step 1102 of FIG. Target 924 (or by steering bus 128 and/or rearrangement buffer 422). The execution unit 424 performs a shift operation in the registers R2 and R3 (if the ALU operation is a carry operation, this operation is performed on the received C flag 902 ) to generate a result and write to the temporary register T3 according to step 1104 . In addition, the execution unit 424 generates a new value of the architectural condition flag 902 according to step 1104, and writes a new condition flag 928 according to step 1114 of writing the condition flag register 926 of FIG. 11 . The value of the temporary register T3 and the condition flag 928 are provided to the steering bus 128 for use by the NCUALUOP microinstruction 126, if not from the steering bus 128, the entry written to the rearrangement buffer 422 for use by the NCUALUOP microinstruction 126, and if not from the steering bus 128. The bus 128 or the rearrangement buffer 422 is finally exited to its appropriate state for use by the NCUALUOP microinstruction 126, except for exception occurrences, branch mispredictions, or other invalid events. In particular, the operating system of the multiplexer 922 of FIG. 9 selects the appropriate condition flags 924 to provide to the execution unit 424 .

The execution unit 424 receives the NCUALUOP microinstruction 126 generated in step 1056 from the reservation station 406, the source operand value from the register R1 and the temporary register T3 of the register file 106, and the condition flag 924 from the condition flag register 926 according to step 1202. . The execution unit 424 performs an ALU operation on the register R1 and the temporary register T3 (and also on the received C flag 902 when the ALU operation is a carry operation) to generate a result, and writes the temporary register T2 according to step 1204 . In addition: (1) if the architectural condition flag 902 does not satisfy the specified condition (marked as NOTSATISFIED in FIG. 15 ), the execution unit 424 generates a new value of the condition flag 928 according to step 1216 to write to the condition flag register 926; (2) If the architectural condition flag 902 satisfies the specified condition and the USE bit 908 is cleared (marked as SAT., USE==0 in FIG. 15 ), the execution unit 424 generates a new value of the condition flag 928 according to step 1226 of FIG. 12B to write the condition flag register 926; and (3) if the architecture condition flag 902 meets the specified condition and the USE bit 908 is set (labeled as SAT., USE==1 in FIG. 15), the execution unit 424 according to the Step 1228 generates a new condition flag 928 value to write to the condition flag register 926. The execution of the CMOV microinstruction 126 of FIG. 15 is similar to that described in FIG. 14 . In another embodiment, as previously described, the USE bit 908 is not present, and the execution unit 424 instead checks the pointer in the conditional ALU microinstruction 126 to confirm that the architecture was updated with the pre-shift carry flag value in the PSC bit 906 The carry flag 902 is still updated with the old carry flag value 924.

It can be found in the foregoing that the shift microinstruction 126 does not replace the old value of the condition flag 902, but writes the old value of the condition flag 902 back to the condition flag register 926. Therefore, the shift microinstruction 126 The conditional ALU operation microinstruction 126 receiving the result of the conditional flags register 926 may determine whether the old conditional flags 902 satisfy the condition specified by the ISA conditional ALU instruction 124 . On the other hand, if the shift microinstruction 126 replaces the old carry flag 902 with the newly generated carry flag value, the conditional ALU operation microinstruction 126 will not confirm whether the old conditional flag 902 satisfies the specified condition.

Please refer to FIG. 16 (including FIG. 16A and FIG. 16B ), which is a block diagram illustrating the execution of a conditional ALU instruction 124 by the execution pipeline 112 of FIG. 1 of the present invention. Specifically, the conditional ALU instruction 124 is a flag update, preshift, and carry update conditional ALU operation ISA instruction 124, and the hardware instruction translator 104 translates the instruction 124 into the microinstruction 126 according to step 1054 in FIG. 10 . . The operation of FIG. 16 is similar to the operation of FIG. 15 in many aspects, and the similar parts will not be repeated here, but only the differences will be described. The register configuration table 402 of FIG. 4 generates auxiliary information for the CU ALUOP microinstruction 126 that writes the value of the temporary register T3 to the shift microinstruction 126. However, since the shift microinstruction 126 does not write the condition flag register, this register configuration Tables do not produce information about them.

The execution unit 424 receives the shift microinstruction 126 generated in step 1054 from the reservation station 406 and receives the source operand value from the registers R2 and R3 of the register file 106 according to step 1102, but does not receive the condition flag 924 (unless the ALU operating system uses a carry operation). The execution unit 424 performs a shift operation on registers R2 and R3 (or on the received C flag 902 if the ALU operation is a carry operation) to generate a result written to temporary register T3 according to step 1104 . The value of temporary register T3 is provided to steering bus 128 for use by CU ALUOP microinstructions 126 , if not from steering bus 128 , the entry written to reorder buffer 422 for use by CU ALUOP microinstructions 126 , and if not from steering bus 128 Or the rearrangement buffer 422 is retired to its proper state for CU ALUOP microinstructions 126 to utilize, except for exception occurrences, branch mispredictions, or other invalid events.

The execution unit 424 receives the CUALUOP microinstruction 126 generated in step 1054 from the reservation station 406, receives the source operand value from the register R1 and the buffer register T3 of the register file 106, and receives the condition flag from the condition flag register 926 according to step 1202. 924. The execution unit 424 performs an ALU operation on the register R1 and the temporary register T3 (if the ALU operation uses a carry operation, then on the received C flag 902 ) to generate a result and write it into the temporary register T2 according to step 1204 . In addition: (1) if the architectural condition flag 902 does not satisfy the specified condition (marked as NOT SATISFIED in FIG. 16 ), the execution unit 424 generates a new value of the condition flag 928 according to step 1216 to write the condition flag register 926; and (2) if the architectural condition flag 902 satisfies the specified condition (marked as SATISFIED in FIG. 16 ), the execution unit 424 generates a new value of the condition flag 928 to write to the condition flag register 926 according to step 1222 in FIG. 12 . The execution of the CMOV microinstruction 126 of FIG. 16 is similar to that described in FIG. 14 .

Please refer to FIG. 17 , which is a block diagram showing the operation of the execution pipeline 112 of FIG. 1 to execute a conditional ALU instruction 124 of the present invention. Specifically, the conditional ALU instruction 124 is a non-flag update, pre-shift, and ISA instruction 124 operating with a carry conditional ALU. The hardware instruction translator 104 translates this instruction into the microinstruction described in step 1036 of FIG. 10 . 126. The operation according to FIG. 17 is similar to the operation of FIG. 16 in many aspects, the similar operations are not repeated here, and only the differences are listed below. Execution of the shift microinstruction 126 of FIG. 17 is similar to that described in FIG. 16 .

The execution unit 424 receives the ALUOPUC microinstruction 126 generated in step 1036 from the reservation station 406, the source operand value from the register R1 and the temporary register T3 of the register file 106, and the condition flag 924 from the condition flag register 926 according to step 1202. . Since the ALU operation uses a carry operation, the execution unit 424 performs an ALU operation on the register R1 , the temporary register T3 and the received C flag 902 to generate a result and write the temporary register T2 according to step 1204 . Execution unit 424 does not write to condition flag register 926 .

The execution unit 424 receives the XMOV microinstruction 126 generated in step 1036 , the source operand values of the temporary register T2 and the destination register RD, and the condition flag 924 generated according to the step 1302 of FIG. 13 . According to steps 1316 and 1314 of FIG. 13 , when the condition flag 924 satisfies the preset condition, the execution unit 424 outputs the value of the source operand of the temporary register T2 as its result, and when the condition flag 924 does not satisfy the preset condition , the execution unit 424 outputs the value of the source operand of the destination register RD as its result. The result value is provided to the steering bus 128 for use by subsequent microinstructions 126, the result value is written to the entry of the rearrangement buffer 422, and except for exception occurrences, branch mispredictions, or other invalid events, the result Values fall back to their appropriate architectural state.

Please refer to FIG. 18 , which is a block diagram illustrating a situation in which the execution pipeline 112 of FIG. 1 executes a conditional ALU instruction 124 of the present invention. Specifically, the conditional ALU instruction 124 is an ISA instruction 124 that is not a flag update, pre-shift, and does not use a carry conditional ALU operation, and the hardware instruction translator 104 translates this instruction 124 into step 1034 of FIG. 10 . Microinstructions 126. The operations performed according to FIG. 18 are similar in many aspects to those performed according to FIG. 17, wherein the similarities are not repeated, and only the differences are described. Execution of the shift microinstruction 126 of FIG. 18 is similar to that described in FIG. 16 . The execution of the ALUOP microinstruction 126 of FIG. 18 is similar to the execution of the ALUOPUC microinstruction 126 of FIG. 17, except that the ALUOP microinstruction 126 of FIG. 18 does not use the C flag 902 to generate its result. The execution of the XMOV microinstruction 126 of FIG. 18 is similar to the execution of the XMOV microinstruction 126 of FIG. 17 .

Please refer to FIG. 19 , which is a block diagram illustrating the execution of a conditional ALU instruction 124 by the execution pipeline 112 of FIG. 1 of the present invention. Specifically, the conditional ALU instruction 124 is a non-flag update, non-preshift, ISA instruction 124 using carry-conditional ALU operation, and the hardware instruction translator 104 translates this instruction 124 into the instruction shown in step 1026 of FIG. 10 . described microinstruction 126. The operation according to FIG. 19 is similar to that described in FIG. 17 in many aspects, and the similarities will not be repeated here, and only the differences will be described. The translation of the conditional ALU instruction 124 is a non-flag update, non-preshift, ISA instruction 124 using carry conditional ALU operations, and does not include a shift microinstruction 126 .

The execution unit 424 receives the ALUOPUC microinstruction 126 described in step 1026 from the reservation station 406 , the source operand value from registers R1 and R2 of the register file 106 , and the condition flag 924 from the condition flag register 926 according to step 1202 . Since the ALU operation uses a carry operation, the execution unit 424 performs an ALU operation on the registers R1 and R2 and the received C flag 902 to generate a result and write to the temporary register T2 according to step 1204 . Execution unit 424 does not write to condition flag register 926 . The execution of the XMOV microinstruction 126 of FIG. 19 is similar to the execution of the XMOV microinstruction 126 of FIG. 17 .

Please refer to FIG. 20 , which is a block diagram illustrating the execution of a conditional ALU instruction 124 by the execution pipeline 112 of FIG. 1 of the present invention. Specifically, the conditional ALU instruction 124 is an ISA instruction 124 that is not a flag update, non-preshift, and non-use carry conditional ALU operation, and the hardware instruction translator 104 translates this instruction into step 1024 in FIG. 10 . of microinstructions 126. The operation according to FIG. 20 is similar to the operation described in FIG. 19 in many aspects, and the same parts will not be repeated, but only the differences will be described. The execution of the ALUOP microinstruction 126 of FIG. 20 is similar to the execution of the ALUOPUC microinstruction 126 of FIG. 19, except that the ALUOP microinstruction 126 of FIG. 20 does not use the C flag 902 to generate its result. The execution of the XMOV microinstruction 126 of FIG. 20 is similar to the execution of the XMOV microinstruction 126 of FIG. 17 .

As can be seen in the foregoing, the described embodiments of the present invention avoid the drawbacks of allowing microinstructions 126 to specify an additional source operand. These disadvantages include, first, an additional read port in the general register file for each execution unit 424 that will execute the microinstruction 126 with additional source operands. Second, for each execution unit 424 that will execute the microinstruction 126 with additional source operands, an additional read port needs to be provided in the rearrangement buffer 422 . Third, more lines are used on the steering bus 128 for each execution unit 424 that will execute the microinstruction 126 with additional source operands. Fourth, an additional relatively large multiplexer is required for each execution unit 424 that will execute microinstructions 126 with additional source operands. Fifth, Q additional label comparators need to be used, where:

Q=∑i=1ton,(R[i]*P[i]*J[i])

where n is the number of execution units 424 , R[i] is the number of items 406 provided by the reservation station 406 to the [i]th execution unit 424 , and P[i] is executable by the [i]th execution unit 424 The maximum number of source operands that a microinstruction can specify, and J[i] is the number of execution units 424 that can lead to the [i]th execution unit 424 . Sixth, additional rename lookup operations are required in register configuration table 402 for additional source operands. Seventh, the reservation station 406 needs to be extended to handle additional source operands. These extra costs in speed, power and space are not welcome.

SAME-SOURCE-DESTINATION Optimized Example

Please refer to FIG. 21 , which is a flowchart illustrating the operation of the hardware instruction translator 104 of FIG. 1 to translate the conditional ALU instruction 124 of the present invention. Basically, the operation of the hardware instruction translator 104 according to FIG. 21 is similar in many respects to the operation described with respect to FIG. 10, especially corresponding to the various steps that need to make decisions, and therefore the same is given here to these steps. 's number.

Please refer to FIG. 21 , step 1002 of FIG. 10 is replaced by step 2102 . In step 2102, the conditional ALU instruction 124 encountered by the hardware instruction translator 104 is different from that encountered in step 1002 because the conditional ALU instruction 124 encountered in step 2102 specifies one of the source registers as the destination register. The hardware instruction translator 104 is configured to recognize this condition and optimize the microinstructions 126 it outputs. In particular, the hardware instruction translator 104 decodes and translates the conditional ALU instructions 124 of the same origin and destination as described in steps 1024 , 1026 , 1034 , 1036 , 1044 , 1054 and 1055 (step 10XX ) of FIG. 10 . 126 sequence of microinstructions. This different sequence of microinstructions 126 is described in steps 2124, 2126, 2134, 2136, 2144, 2154 and 2156 (step 21XX) of FIG. 21 in place of its corresponding step 10XX. In particular, the microinstructions 126 in the microinstruction 126 sequence of each step in step 21XX are one instruction less than the corresponding microinstruction 126 sequence in step 10XX. Specifically, the sequence of step 21XX does not include the CMOV or XMOV microinstructions 126, and the operation of selectively writing the original destination register value or the result value is performed by the conditional ALU microinstruction 126 at the end of the sequence. This operation is explained more clearly in the following paragraphs.

In step 2124, the hardware instruction translator 104 translates the conditional ALU instruction 124 with the same source and destination non-flag update, non-preshift, and non-carry use into a single microinstruction 126, that is, a conditional ALU operation microinstruction 126 (marked for ALUOP CC). In the instance of step 2124, the conditional ALU instruction 124 is similar to that described for step 1024, except that the first source operand is the destination register (RD). Therefore, the conditional ALU instruction 124 specifies a first source register (RD) and a second source register (R2), and an ALU operation (labeled as ALUOP) is performed on the first source register RD and the second source register R2 to generate A result, and the destination register (RD) is the same as the first source register, and the execution result is conditionally written into the destination register. Conditional ALUOP microinstructions 126 and conditional ALU instructions 124 specify the same ALU operations and conditions. The execution unit 424 of the execution condition ALUOP microinstruction 126 receives the old or current value of the destination register (RD), and at the same time receives the value of the second source operand R2 according to step 1202, and executes the ALU operation on these two according to step 1204. Source operands to produce a result. The execution unit 424 also receives the condition flag 924 and checks the condition flag 924 according to step 1204 to confirm whether it satisfies the specified condition. If yes, the execution unit 424 outputs the result according to step 1211 , otherwise it outputs the old destination register value according to step 1212 . The execution of the conditional ALUOP microinstruction 126 is shown in FIG. 28 as a block diagram. The process ends at step 2124.

In step 2126, the hardware instruction translator 104 translates the conditional ALU instruction 124 with the same source destination, non-flag update, non-preshift, and use carry, into a single microinstruction 126, that is, a carry conditional ALU operation microinstruction 126 ( Labeled as ALUOPUC CC). In the instance of step 2126, the conditional ALU instruction 124 is similar to that described in step 2124, except that the ALU operation it specifies uses the carry flag, and the instruction is also similar to that described in step 1026, except that the first source The operand is the destination register (RD). The conditional ALUOPUC microinstruction 126 is similar to that described in step 2124; however, the ALU operation it specifies uses the carry flag. The execution of the conditional ALUOPUC microinstruction 126 as shown in the block diagram of FIG. 27 is similar to the execution of the conditional ALUOPUC microinstruction 126 of step 2124, except that the execution unit 424 uses the carry flag to perform the ALU operation. The process ends at step 2126.

In step 2134, the hardware instruction translator 104 translates the conditional ALU instruction 124 with the same source and destination non-flag update, pre-shift, and non-use carry into the first and second microinstructions 126, namely: (1) one shift and (2) an ALUOP microinstruction 126. In the instance of step 2134, the conditional ALU instruction 124 is similar to that described in step 1034, except that the first source operand is the destination register (RD), and this instruction is similar to that described in step 2124, except that the conditional ALU Instruction 124 also specifies a pre-shift operation on the second source operand (R2) with a shift amount that, in the example of step 2134, is stored in the third source specified by conditional ALU instruction 124 register (R3). However, if the conditional ALU instruction 124 is of the type that specifies the shift amount as a constant within the instruction 124, the third source register will not be used. The shift microinstruction 126 is similar to that described in step 1034, and the manner in which the execution unit 424 executes the shift microinstruction 126 is similar to that described in step 1034 and FIG. Although in step 2134, because the conditional ALU instruction 124 indicates that the architectural condition flag 902 will not be updated, the carry flag value generated by the shift microinstruction 126 is not used, however, as in step 2156, by The carry flag value generated by the shift microinstruction 126 is used. Furthermore, this preshift operation would require the old carry flag to be rotated to the shifted result value; for example, an RRX preshift operation would shift the carry flag to the most significant bit of the result. In this case, although not shown in Figure 21 (except for step 2156), when the execution unit 424 executes the shift microinstruction 126, it also reads the condition flag 924 to obtain the current carry flag value. Conditional ALUOP microinstruction 126 and its execution are similar to those described in step 2124; however, this microinstruction receives the value of temporary register T3 instead of the value of register R2, and performs an ALU operation on register R1 and temporary register T3 to produce a result Write to the destination register. The execution of the shift microinstruction 126 and the conditional ALUOP microinstruction 126 are shown in FIG. 26 . The process ends at step 2134.

In step 2136, the hardware instruction translator 104 updates the conditional ALU instruction 124 of the same source destination non-flag update, pre-shift, and use carry to the first and second micro-instructions 126, namely: (1) a shift micro-instruction instruction 126; and (2) an ALUOP microinstruction 126 (designated as ALUOPUC CC) using the carry conditional arithmetic and logic unit. In the example of step 2136, the conditional ALU instruction 124 is similar to that described in step 2134, except that the specified ALU operation uses the carry flag, and the instruction is similar to that described in step 1036, except that the first source operates Number System Destination Register (RD). The two microinstructions 126 and their execution are similar to those described in step 2134; however, the ALUOPUC microinstruction 126 also receives the condition flag 924 to obtain the current value of the carry flag for use in carry using the ALU operation. The execution of the shift microinstruction 126 and the conditional ALUOPUC microinstruction 126, as shown in Figure 25, is similar to the execution of the shift microinstruction 126 and the conditional ALUOP microinstruction 126 in step 2134, except that the execution unit 424 uses the carry flag to perform ALU operations. The process ends at step 2136.

In step 2144, the hardware instruction translator 104 translates the same source destination flag update, non-preshifted conditional ALU instruction 124 into a single microinstruction 126, that is, a conditional ALU operation microinstruction 126 (labeled as ALUOP CC). In the example of step 2144, the conditional ALU instruction 124 is similar to the conditional ALU instruction 124 of step 2124, except that the architectural conditional flag 902 is updated, and is similar to that described in step 1044, except that the first source operand coefficient destination register. The conditional ALU operation microinstruction 126 of step 2144 and its operation are similar to those described in step 2124, except that the ALU operation microinstruction 126 of step 2144 also updates the architectural condition flag 902 and is similar to the conditional ALU operation microinstruction 126 of step 1044 , except that its first operand is the destination register instead of register R1 and its destination register is the destination register instead of temporary register T2. The execution unit 424 executes the conditional ALU microinstruction 126. The execution unit 424 receives the destination register RD and the register R2 as source operands according to step 1202, and executes the specified ALU operation on the two source operands according to step 1204 to generate a result . The execution unit 424 also receives the framework condition flag 902 and confirms whether it satisfies the specified condition according to step 1206 . If so, the execution unit 424 selects to output the result of the ALU operation to write to the destination register RD according to step 1222 or 1226 according to whether the ALU operation is a carry update operation, otherwise, output the old value of the destination register RD according to step 1216. In addition, the execution unit 424 selects to write the condition flag register 926 according to steps 1216 , 1222 or 1226 according to whether the condition is satisfied and whether the ALU operation is a carry update operation. If the condition is not satisfied, the execution unit 424 writes the old condition flag value into the frame condition flag 902 according to step 1216; on the contrary, if the condition is satisfied, the execution unit 424 performs the conditional carry ALU operation according to step 1222, The architectural condition flag 902 is updated based on the result of the ALU operation, and in the case of an unconditional carry ALU operation, according to step 1226 . The execution of the conditional arithmetic and logic unit ALUOP microinstruction 126 is presented in FIG. 22 . It is worth noting that the ALU operation performed by the conditional ALU operation microinstruction 126 generated in step 2144 (and steps 1054 and 1056) may be an ALU operation using a carry flag (similar to that described in steps 1026 and 1036), And since the microinstruction 126 will read the flag (indicated by RDFLAGS), the execution unit 424 has the carry flag to perform the carry using the ALU operation. The process ends at step 2144.

In step 2154, the hardware instruction translator 104 translates the conditional ALU instructions 124 used for the same source destination flag update, pre-shift, and carry into the first and second microinstructions 126, namely (1) a shift microinstruction 126; and (2) a conditional carry update ALU operation microinstruction 126 (labeled CU ALUOP CC). In the instance of step 2154, the conditional ALU instruction 124 is similar to that described in step 2134, except that the conditional ALU instruction 124 also specifies that the architectural condition flag 902 is to be updated, and is similar to that described in step 1054, except that the first A source operand is the destination register. The shift microinstruction 126 is similar to that described for step 1034, and the manner in which the execution unit 424 executes the shift microinstruction 126 is similar to that described for step 1034 of FIG. The CU ALUOP microinstruction 126 and its execution are similar to the conditional ALU microinstruction 126 of step 2124, except that the CU ALUOP microinstruction 126 of step 2144 also updates the architectural condition flag 902, and is similar to the conditional ALU microinstruction 126 of step 1054 , except that its first operand is a destination register instead of register R1, and its destination register is a destination register instead of temporary register T2. The execution unit 424 executing the CU ALUOP microinstruction 126 receives the destination register RD and the temporary register T3 as source operands according to step 2102, and executes the specified ALU operation on the destination register and the temporary register T3 according to step 1204 to generate a result. In addition, the execution unit 424 receives the framework condition flag 902 according to step 1202 and confirms whether it satisfies the specified condition according to step 1206 . In addition, according to whether the condition is satisfied, the execution unit 424 updates the condition flag register 926 according to step 1216 or 1222. If the condition is not satisfied, the execution unit 424 writes the old condition flag value into the architectural condition flag 902; otherwise, if the condition is satisfied, the execution unit 424 updates the architectural condition flag 902 based on the result of the ALU operation. The execution of the shift microinstruction 126 and the conditional ALUOP microinstruction 126 is shown in FIG. 24 . The process ends at step 2154.

In step 2156, the hardware instruction translator 104 translates the conditional ALU instruction 124 with the same source destination flag update, to be shifted, and not to carry update into the first and second microinstructions 126, namely: (1) a shift microinstruction 126; and (2) a conditional non-carry update ALU operation microinstruction 126 (labeled as NCU ALUOP CC). In the example of step 2156, the conditional ALU instruction 124 is similar to that described in step 2154, except that the conditional ALU instruction 124 specifies a non-carry update ALU operation, and is similar to that described in step 1056, except that the first source operand system destination register. Therefore, when the conditions are met, the architectural carry flag 902 is updated with this pre-shift carry flag value. The shift microinstruction 126 is similar to that described in step 2134; however, the shift microinstruction 126 reads and writes the condition flags register 926. Specifically, the execution unit 424 that executes the shift microinstruction 126: (1) writes the carry flag value generated by the preshift operation into the PSC bit 906; (2) sets the USE bit 908 to indicate the conditional NCUALUOP microinstruction instructs 126 to update the architectural carry flag 902 with the PSC bit 906; and (3) writes the old architectural condition flag 902 back to the condition flags register 926 according to step 1114, whereby the NCUALUOP microinstruction 126 can evaluate the architectural condition flag 902 to confirm whether it meets the specified conditions. The NCUALUOP microinstruction 126 and the conditional ALU instruction 124 specify the same conditions. The execution unit 424 executing the NCUALUOP microinstruction 126 performs an ALU operation on the destination register and the temporary register T3 according to step 1204 to generate a result. In addition, the execution unit 424 receives the architectural condition flag 902 and confirms whether it satisfies the condition according to step 1206 . In addition, the execution unit 424 chooses to write the condition flag register 926 according to steps 1216, 1226 or 1228 depending on whether the condition is satisfied and whether the USE bit 908 is set. Specifically, if the condition is not satisfied, the execution unit 424 will write the old condition flag value into the framework condition flag 902 according to step 1216; and when the condition is satisfied, the execution unit 424 will check whether the USE bit 908 is set , select according to step 1226 or 1228, and update the architecture condition flag 902 based on the result of the ALU operation. Specifically, the architectural overflow (V) flag 902 is written with the old overflow flag value 924, and the N and Z flags are written with new values based on the result. Furthermore, if the USE bit 908 so indicates, the architectural carry flag 902 is updated with the pre-shifted carry flag value at the PSC bit 906 according to step 1228, otherwise it is updated with the old carry flag value 924 according to the step 1226. The execution of the shift microinstruction 126 and the NCUALUOP microinstruction 126 is shown in FIG. 23 . The process ends at step 2156.

The advantage of this approach is that when the conditional ALU instruction 124 specifies that one of the destination and source registers is the same, the hardware instruction translator 104 can optimize and reduce the generated sequence of microinstructions 126 by one microinstruction 126 . First, it can increase the lookahead function of the microprocessor 100 to increase the usage of the execution unit 424 by utilizing the parallel processing of the instruction level of the program to be executed. Since the reduction in the number of microinstructions 126 means that there will be more free slots in the rearrangement buffer 422 for additional microinstructions 126, a larger pool of microinstructions 126 can be created to complete the issue preparation for subsequent execution. can be used to improve this look-ahead function. Second, because the hardware instruction translator 104 can only output microinstructions 126 to a predetermined number of slots per clock cycle, and at least in one embodiment, the hardware instruction translator 104 must be at the same time All microinstructions 126 required to implement a given ISA instruction 124 are output in one pulse cycle. Therefore, reducing the number of microinstructions 126 generated by the translation of a conditional ALU instruction 124 can also reduce the average number of empty microinstruction slots 126 per cycle. number, and at the same time helps to increase the look-ahead function of the microprocessor 100 and the use of the execution unit 424 .

Conditional non-branch instruction prediction

The above embodiments describe the technology of translating a conditional non-branch instruction, ie, a conditional ALU instruction, into a microinstruction in a pipelined microprocessor with limited read port-limited. The first microinstruction performs an ALU operation and writes the result to a scratch register. The second microinstruction receives the result from the temporary register and the current value of the destination register, and writes the result to the destination register when the condition is satisfied, and writes the current value back to the destination register when the condition is not satisfied. Similarly, the embodiment described in US Provisional Application 61/473,062 is to translate a conditional non-branch instruction, referred to herein as a conditional load instruction, into a microinstruction in a pipelined microprocessor with limited read ports. . This instruction translator translates the conditional load instruction into two microinstructions: (1) a load microinstruction that obtains the condition code and flag at the same time, and does not update its architectural state (eg page table) when the condition is not satisfied query for the side effects of a memory write generated or generate an exception) and load a dummy value into the scratch register, but, if the condition is met, load the scratch register with the real value from memory; and (2) a conditional move microinstruction, Receives the current value of the destination register, and if the condition is not true, moves this current value back to the destination register, and when the condition is true, moves the value from the temporary register to the destination register.

Although this solution is an improvement over conventional techniques, this approach incurs additional costs, namely delays related to the second microinstruction and the second microinstruction's dependencies with the first microinstruction. Second, instruction slots in other structures of the microprocessor, such as microinstruction queues, reorder buffers, reservation stations, and execution units, are also utilized by the second microinstruction. In addition, the presence of the second microinstruction reduces the average number of instructions issued by the instruction translator, issued by the instruction issue unit, and retired by the instruction retirement unit per clock cycle, thereby limiting the processing capability of the microprocessor.

The present invention provides a solution with higher performance, which incorporates a prediction mechanism, similar to the branch prediction method, to predict the direction of the conditional non-branch instruction, that is, predict whether the condition is satisfied, and then determine whether the conditional non-branch instruction needs to be executed. branch instruction. This workaround allows the conditional translator to issue a single microinstruction, rather than multiple microinstructions, based on prediction information. The microprocessor also has a mechanism for recovering from mispredicted states.

Embodiments with both static and dynamic prediction mechanisms are described below. The static prediction mechanism is similar to static branch prediction. A dynamic (or historically based) prediction mechanism looks at the program counter/instruction pointer value of a conditional non-branch instruction when fetching the conditional non-branch instruction from the instruction cache, which works similarly to branch target memory address caching (branch target address cache, BTAC).

In the static prediction mechanism, the static predictor looks at this operation and/or the condition code specified by the conditional non-branch instruction (eg: ALU operation is add, condition code is EQUAL), and predicts whether to execute based on existing data (profiling data) this action. For example, when a conditional non-branch instruction is executed a significant percentage of the time based on a combination of operations and condition codes and empirical data, the static predictor predicts that the instruction will be executed, and the instruction translator will issue a single non-branch instruction. Conditional microinstructions, such as:

addcc dst,src1,src2

The condition code and flag are provided to the microinstruction (ie, addcc), so the execution unit can confirm whether the prediction is correct and generate a misprediction indicator when the prediction is wrong.

Conversely, where a combination of operations and condition codes and empirical data show that a substantial percentage of the time a conditional non-branch instruction will not be executed, the static predictor predicts that the instruction will not be executed, and the instruction translator issues a single non-branch instruction. Operation (nop) microinstructions, such as:

Nopcc

Likewise, the condition codes and flags are provided to microinstructions (ie, nopcc), so that the execution unit can generate a misprediction indicator when necessary.

In the case where the ratio of go/no-go is not large enough to justify the static prediction, the instruction translator reverts to the previously less efficient multi-microinstruction solution, eg: the translator issues two microinstructions:

add tmp,src1,src2

movcc dst, src-dst, tmp//src-dst is the current dst reg value

In the dynamic prediction mechanism, a BTAC-like architecture, also referred to here as the conditional ALU direction cache (CADC), retrieves the direction history information of previously executed conditional non-branch instructions and their program counters/instructions The pointer value is used to predict the direction of the subsequent fetched conditional non-branch instruction based on the hit situation of the fetched address value in the historical information of the CADC entry. This CADC provides its predictions to the instruction translator. The instruction translator issues microinstructions based on predictions made by the aforementioned static predictor.

The recovery mechanism clears the pipeline of the conditional non-branch instruction and all subsequent instructions (more precisely, the microinstructions from which it is translated), or all at least directly or indirectly related to the conditional non-branch instruction. instruction, and then replay (replay) all cleared instructions. In repeated execution of conditional non-branch instructions, the translator will tend to issue multiple microinstructions.

One embodiment of the present invention uses both static and dynamic predictors, and records historical data on which predictor is more accurate for each program counter/instruction pointer value. According to the known two-level hybrid branch prediction method, the historical data can be used to dynamically select one of the two predictors to provide the final prediction.

It is worth noting that there is a penalty for misprediction of conditional non-branch instructions (i.e. clearing the pipeline and repeating execution of conditional non-branch instructions and subsequent instructions or at least directly and indirectly related instructions), this penalty varies and is application code and/or a function of the dataset. Therefore, the solution of predicting conditional non-branch instructions may be a less efficient solution for some mixed states of application code and/or data sets.

A non-branch instruction is defined here. This instruction is not written into the program counter of the microprocessor, so the microprocessor will fetch and execute the following instructions of the non-branch instruction. The program counter is used in the ARM architecture, and other architectures use different components to replace the program counter. For example, the x86 ISA uses the instruction pointer, while other ISAs use the instruction address register. There is a distinct difference between a non-branch instruction and a branch instruction that writes an address to the program counter/instruction pointer so that the microprocessor points to that address. The microprocessor will begin fetching instructions from the address written to the program counter/instruction pointer by the branch instruction, and then execute the fetched instruction. This operation is significantly different from fetching and executing the subsequent instruction of the branch instruction, because fetching and executing the subsequent instruction of the branch instruction is the default operation of the microprocessor, and it is also the operation when a non-branch instruction is encountered. Examples of conditional non-branch instructions include conditional ALU instructions and conditional load/store instructions.

Please refer to FIG. 29 , which shows a block diagram of the microprocessor 100 for predicting unconditional branch instructions according to the present invention. The microprocessor 100 of FIG. 29 is similar to the microprocessor 100 of FIG. 1 and includes similar elements to those of FIG. 1 and FIG. , instruction issue unit 408 , execution unit 424 and reorder buffer 422 . Execution unit 424 contains one or more units to execute what are referred to herein as microinstructions 126 . Additionally, the execution unit 424 may execute the no-op microinstruction 126 . The do not operate microinstruction 126 instructs the execution unit 424 not to perform the operation. Further, the no-op microinstruction 126 referred to herein includes a condition, or condition code, specified by the conditional ALU instruction 124 that translates the no-op microinstruction 126 . There will be further explanations about not operating the microinstruction 126 in the following pages. Microprocessor 100 also includes architectural registers, scratchpad 126 and flag 926 of FIG. 9 .

The microprocessor 100 of FIG. 29 also includes a dynamic predictor 2932, a static predictor 2936, and a predictor selector 2934. These elements are coupled to the instruction translator 104 and are used to predict the direction (executed or not executed) of a conditional ALU instruction 124 (of FIG. 2). The fetch address 134 of FIG. 1 is also provided to the dynamic predictor 2932 and the predictor selector 2934.

Dynamic predictor 2932 and predictor selector 2934 each include a cache with multiple entries. Each entry caches the memory address of a previously executed ARM conditional ALU instruction 124. That is, when the microprocessor 100 retires a conditional ALU instruction 124, the dynamic predictor 2932 and the predictor selector 2934 are inspected to determine whether it contains an entry with the address of the conditional ALU instruction 124. If so, the entry will be updated according to the correct direction of the conditional ALU instruction 124 indicated by a historical data update pointer 2974; if not, an entry will be configured in each of the dynamic predictor 2932 and the predictor selector 2934 for the conditional ALU Instruction 124. Although the dynamic predictor 2932 and predictor selector 2934 of FIG. 1 are independent, in one embodiment, the two elements are integrated into a single cache array. That is, each entry of this single array contains the trend prediction of the dynamic predictor 2932 and the selection field of the predictor selector 2934, which will be further explained in the following pages.

Each entry of the dynamic predictor 2932 stores the address of a conditional ALU instruction 124, and each entry has a field to store the trend prediction of the conditional ALU instruction 124. The orientation prediction is updated in response to the correct orientation of the conditional ALU instruction 124 to retire at the address. Trend forecasts can contain a variety of different formats. For example, a trend prediction may include a single bit to indicate whether it is performed or not. This bit is set to a specific value if the predicted trend is to be executed, or to another value if it is not executed. As another example, the trend prediction may include a multi-bit counter. When the predicted trend is executed, the multi-bit counter will be incremented as much as possible, and if not executed, the multi-bit counter will be decremented as much as possible. If the counter value is greater than the median value, the prediction is executed, and if the counter value is smaller than the median value, the prediction is not executed.

The fetch address 134 is provided to the dynamic predictor 2932 each time an instruction block is fetched from the instruction cache 102 . The dynamic predictor 2932 looks at the fetch address 134 to see if it matches a valid tag in its cache array, ie hits a valid tag or not. If the fetch address 134 is not hit, the dynamic prediction output terminal 2982 of the dynamic predictor 2932 outputs a value indicating no prediction (NP). If the fetch address 134 is hit, the dynamic predictor 2932 outputs a value at its dynamic prediction output 2982, indicating that the executed (E) direction or a not executed (NE) direction is based on the memory stored in the matching entry. Depending on the value of the predicted field. In one embodiment, the dynamic prediction output 2982 of the dynamic predictor 2932 may output a value indicating no prediction (NP) even if the fetch address 134 is hit. For example, in the case where the historical data shows that the probability that the conditional ALU instruction 124 will be executed or not executed is almost equal, that is, the probability that the condition will be satisfied or not satisfied is almost equal. This trend prediction 2982 is provided to the instruction translator 104 .

Each entry of predictor selector 2934 also contains a field to store the selector of conditional ALU instruction 124 for each address stored in that entry, the selector indicating whether dynamic predictor 2932 or static predictor 2936 is more likely to be correct Predict the direction of the conditional ALU instruction 124 . The selector is updated in response to the retirement of this conditional ALU instruction 124 at the address, specifically as indicated by the history update indicator 2974 (indicating that the prediction was made by the dynamic predictor 2932 or the static predictor 2936) correct direction and information to be updated. Selectors can contain a variety of different formats. For example, this selector may include a single bit to represent the dynamic predictor 2932 or the static predictor 2936. This bit is set to a specific value when the dynamic predictor 2932 correctly predicts the direction, and to another value when the static predictor 2936 correctly predicts the direction, and remains if both correctly predict the direction The previously selected predictor. To give another example, the selector may include a multi-bit counter. When the dynamic predictor 2932 correctly predicts the direction, the multi-bit counter will increase as much as possible, and if the static predictor 2936 correctly predicts the direction, the multi-bit counter will be decremented as much as possible. If the direction is correctly predicted, the value of the counter is not updated. A counter value greater than the median value predicts that the dynamic predictor 2932 will correctly predict the trend, and a counter value smaller than the median value predicts that the static predictor 2936 will correctly predict the trend.

Each time an instruction block is fetched by the instruction cache 102, the instruction address 134 is provided to the predictor selector 2934 to examine the fetch address 134 to confirm whether it matches a valid tag of its cache array, ie, hits a valid tag or miss. If the fetch address 134 is not hit, the prediction select output 2984 of the predictor selector 2934 outputs a value indicating no prediction (NP). If the fetch address 134 hits, the predictor selector 2934 outputs a value at its predict select output 2984 to indicate the dynamic predictor 2932(D) or the static predictor 2936 according to the select field value stored in the matching entry. In one embodiment, even if the fetch address 134 hits, the select prediction output 2984 of the predictor selector 2934 may still output a value indicating no prediction. For example, historical data shows that neither the dynamic predictor 2932 nor the static predictor 2936 is likely to predict correctly. This predictive selection 2984 is provided to the instruction translator 104 .

The static predictor 2936 receives the instruction 124 fetched from the instruction cache 102 and analyzes the condition code of the instruction 124 and/or the special ALU function it specifies to predict the direction of the conditional ALU instruction 124 . The static predictor 2936 basically includes a lookup table containing E, NE, or NP indicators associated with each possible condition code/ALU function combination. For one embodiment, these E, NE, or NP metrics are configured within static predictor 2936 based on empirical data written to ARM instruction set architecture program execution. Static prediction 2986 is provided to instruction translator 104 . In one embodiment, the static predictor 2936 is integrated within the instruction translator 104 .

The instruction translator 104 uses the aforementioned predictions 2982/2984/2986 to translate the conditional ALU instruction into the microinstruction 126, which will be further explained in the following sections corresponding to Figures 30 and 31. These predictions 2982/2984/2986 are passed down the pipeline of the microprocessor 100 along with the conditional ALU instruction 124 for use by the execution unit 424 to confirm whether each predictor 2932/2934/2936 correctly predicted the conditional ALU instruction 124 towards. In one embodiment, the dynamic predictor 2932 , the predictor selector 2934 and the static predictor are determined when the instruction block fetched from the instruction cache 102 per clock cycle contains multiple conditional ALU instructions 124 . The 2936 produces multiple predicted 2982/2984/2986 per clock cycle.

In one embodiment, the microarchitecture of the microprocessor 100 is similar in many aspects to the microarchitecture of the VIA Nano ^™ processor produced by VIA Electronics, Taiwan, however, the microprocessor 100 of this embodiment is modified to support ARM instruction set architecture. The microarchitecture of the VIA Nano ^™ processor is a high performance non-sequential execution superscalar microarchitecture to support the x86 instruction set architecture. The processor is modified as described herein to additionally support the ARM microarchitecture, particularly detailed in the following sections, corresponding to the ARM conditional ALU instruction 124 of FIG. 2 .

The register allocation table 402 represents the result of a conditional move microinstruction 3046 (refer to FIG. 30 for a detailed description) associated with an ALU microinstruction 3044 (refer to FIG. 30 for a detailed description), both of which are executed by the instruction translator 104. Issued when a conditional ALU instruction 124 is translated under certain conditions. These specific conditions are described below when a conditional ALU instruction 124 has no available prediction, or a conditional ALU instruction is mispredicted and repeated.

Temporary registers 106 store the non-architectural state of microprocessor 100 . Temporary registers 106 may be utilized by the microarchitecture to temporarily store intermediate values required to execute instructions of the instruction set architecture. Further, microinstructions issued by instruction translator 104 may designate scratch registers 106 as source and/or destination operand locations. In particular, the ALU microinstruction 3044 of FIG. 30 may designate a temporary register 106 as its destination register, and a related conditional move microinstruction 3046 designates the same temporary register 106 as one of its source registers. This will be further explained in the following sections.

At least one execution unit 424 has an arithmetic logic unit (ALU) (not shown) for executing various microinstructions, including the ALU microinstruction 3044 shown in FIG. 30 and an unconditional ALU microinstruction with a condition code (CC). 3045. In addition, at least one execution unit 424 is used to execute the conditional move microinstruction 3046 and the do not operate microinstruction 3047 with a condition code (CC) shown in FIG. 30 . For the conditional move microinstruction 3046 of FIG. 30, the unconditional ALU microinstruction 3045 with the condition code, or the do not operate microinstruction 3047 with the condition code, the execution unit 424 receives the condition code value a224, a254, or a274 (please 30) as the input value and the current value of the flag 926. The execution unit 424 confirms whether the value of the flag 926 satisfies the condition specified by the condition code a224, a254 or a274. Therefore, the execution unit 424 can confirm the correct direction of the conditional ALU instruction 124 and determine whether the dynamic predictor 2932 and/or the static predictor 2936 mispredicts the direction of the conditional ALU instruction 124, and the judgment result is represented by a misprediction A misprediction indication 2976 is provided to the rearrangement buffer (ROB) 422. In addition, the execution unit 424 judges whether the predictors 2932 and 2936 selected by the predictor selector 2934 correctly predict the trend, and the judgment result is used to update the dynamic predictor 2932 and the predictor selector 2934 . As far as the conditional move microinstruction 3046 in FIG. 30 is concerned, if the condition is satisfied, the execution unit 424 moves the value of the temporary register 106 specified by the field a226 of the source register 1 to the structure specified by the destination register field a232 of FIG. 30 . register 106. If the condition is not satisfied, the value of the architectural register 106 specified by the field a228 of the source register 2, that is, the value of the original destination register, is moved to the architectural register 106 specified by the destination register field a232.

Reorder buffer 422 receives results from execution unit 424 that contain an indication of whether the direction of conditional ALU instruction 124 was mispredicted. If this trend is not mispredicted, the rearrangement buffer 422 is generated by executing the ALU operation specified by the opcode a202 of the conditional ALU instruction 124 on the source operand specified by the field a206 of the source register 1 and the source register 2. The result is to update the architectural state of the microprocessor 100, which is to use this result to update the flag 926 and the architectural register 106 specified by the destination register field a208 of the conditional ALU instruction, which is reflected in the conditional move microinstruction of FIG. 30. The destination register field a232 of the 3046 is the same as the destination register field a258 of the unconditional ALU microinstruction with the opcode. However, if the direction is mispredicted, the rearrangement buffer 422 will generate a true value for a mispredicted indicator 2976. The misprediction pointer 2976 is provided to the instruction translator 104, whereby, by repeatedly executing the mispredicted conditional ALU instruction 124, the instruction translator 104 knows that multiple microinstructions ( multiplemicroinstruction) technology. The misprediction indicator 2976 is also provided to other related pipeline units, such as the register allocation table 402 and the instruction issue unit 408, so that it can clear micro-instructions when necessary. The rearrangement buffer 422 also generates a historical data update value 2974 to update the dynamic predictor 2932 and the predictor selector 2934 according to the result of the conditional ALU instruction 124, that is, the trend prediction result.

Please refer to FIG. 30 , which shows a block diagram of the translation of the conditional ALU instruction 124 by the instruction translator 104 of FIG. 29 . As described herein, the instruction translator 104 of FIG. 29 may translate the conditional ALU instruction 124 into three different sets of microinstructions, depending on the environment in which the translator 104 is assigned to translate the conditional ALU instruction 124, as shown in FIG. 30 . , the conditional ALU instruction 124 is predicted to be executed (E), predicted not to be executed (NE), or not predicted (NP). In one embodiment, the conditional ALU instruction 124 is a conditional ALU instruction defined by the ARM instruction set architecture.

The conditional ALU instruction 124 includes an opcode field a202, a condition code field a204, a source register 1 and source register 2 fields a206, and a destination register field a208. Opcode field a202 contains a value to distinguish this conditional ALU instruction from other instructions within the instruction set architecture.

The condition code field a204 specifies a condition under which, depending on whether the current value of the flag 926 satisfies the condition, the destination register will be selectively updated with the result of the ALU microinstruction 3044 described below. According to an embodiment compatible with the ARM instruction set architecture, the condition code field a204 is assigned to the upper four bits (ie, bits [31:28]) of the conditional ALU instruction 124, enabling sixteen different possible values for encoding. For the architecture version dependent value (0b1111), this instruction cannot be predicted by the architecture version, but is used to indicate the unconditional instruction extension space of other architecture versions.

table 3.

Field a206 of source register 1 and source register 2 specifies the immediate value and architectural register 106 holding the input operand, and the ALU operation (eg: add, subtract, multiply, divide, and, or, etc.) specified by opcode a202 will A result will be generated according to its execution. When the condition is met, the result will be conditionally loaded into the architectural register 106 specified by the destination register field a208.

In the case of no prediction (NP), the instruction translator 104 translates the conditional ALU instruction 124 into an ALU microinstruction 3044 and a conditional move microinstruction 3046 for the execution unit 424 to execute.

The ALU microinstruction 3044 includes an opcode field a212, fields a216 of source register 1 and source register 2, and a destination register field a218. The opcode field a212 contains a value to distinguish the ALU microinstruction 3044 from other microinstructions of the microinstruction set architecture of the microprocessor 100 . The ALU function specified by opcode a202 of conditional ALU instruction 124 is communicated to opcode field a212 of ALU microinstruction 3044 . Field a216 of source register 1 and source register 2 specifies the immediate value and the architectural register 106 that holds the operand. The ALU operation specified by opcode a212 will be performed on the operands to produce a result, which will be loaded into the architectural or scratch register 106 specified by destination register field a218. In the case of no prediction, when the instruction translator 104 translates the conditional ALU instruction 124, the instruction translator 104 fills the ALU microinstruction with the same value as the field a206 of the source register 1 and the source register 2 of the conditional ALU instruction 124 Field a216 of source register 1 and source register 2 of 3044. When the instruction translator 104 translates the conditional ALU instruction 124, the instruction translator 104 fills in the destination register field a218 to designate a temporary register 106 to receive the result of the ALU operation.

The conditional move microinstruction 3046 includes an opcode field a222, a condition code field a224, a source register 1 field a226, a source register 2 field a228, and a destination register field a232. Opcode field a222 contains a value to distinguish this conditional move microinstruction 3046 from other microinstructions of the microinstruction set architecture of microprocessor 100 . The condition code field a224 specifies a condition to selectively execute the move operation according to whether the current value of the flag 926 satisfies the condition of the condition code field a204 of the conditional ALU instruction 124 . In fact, when translating the conditional ALU instruction 124, the instruction translator 104 populates the condition code field a224 of the conditional move microinstruction 3046 with the same value as the condition code field a204 of the conditional ALU instruction 124. Field a226 of source register 1 specifies an architectural or scratch register 106 to indicate that the first source operand of this register will be provided to the conditional move microinstruction 3046; and field a228 of source register 2 specifies an architectural or scratch register 106 to indicate that the second source operand of this register will be provided to the conditional move microinstruction 3046. When the instruction translator 104 translates the conditional ALU instruction 124, the instruction translator 104 fills the source register 1 field a226 with the same value it fills in the destination register field a218 of the ALU microinstruction 3044. Instruction translator 104 also fills field a228 of source register 2 with the same value it fills in destination register field a208 of conditional ALU instruction 124 . That is, the field a228 of the source register 2 causes the conditional move microinstruction 3046 to receive the current value of the destination register, so that when the condition is not satisfied, the current value can be written back to the destination register. The instruction translator 104 fills the destination register field a232 with the same value as the destination register field a208 of the conditional ALU instruction, so that the current value of the destination register field specified by the conditional ALU instruction 124 is not changed when the condition is not satisfied. The value loading to the destination register is to load the value of the temporary register holding the result of the ALU microinstruction 3044 into the destination register when the condition is satisfied.

In one embodiment, without prediction (NP), the instruction translator 104 translates the conditional ALU instruction 124 into the microinstruction 126 described in FIGS. 10-28. As mentioned above, the microinstruction group 126 will change with the conditional ALU instruction 124, such as: whether one of the source registers is the destination register, whether it is a flag update instruction, whether a pre-shift is specified, whether the current carry is used or not The flag value, and in the case of a flag update preshift, whether this ALU operation updates the carry flag. In particular, in the case of a partial preshift conditional ALU instruction 124, the microinstruction group will contain three microinstructions 126 as shown in FIG. 10 instead of two microinstructions 126 as shown in FIG. 30 . Secondly, when the conditional ALU instruction 124 designates one of the source registers as the destination register, the number of microinstructions 126 included in the microinstruction group is reduced by one, as compared with FIG. 21 and FIG. 10 . Furthermore, this microinstruction group does not contain the conditional move microinstruction 126, but the conditional move function is provided by the conditional ALU microinstruction 126. As a result, in some instances, the microinstruction group contains only a single microinstruction 126 as shown in FIG. 21 , rather than two microinstructions 126 as shown in FIG. 30 . In addition, in the case of the flag update conditional ALU instruction 124, the conditional move microinstruction 126 included in the microinstruction group is slightly different from the conditional move microinstruction 126 shown in FIG. 30 . In particular, in order to confirm whether the condition is satisfied, the conditional move microinstruction (CMOV) 126 described in steps 1044, 1054 and 1056 of FIG. 10 checks a non-architectural flag, which is determined by the previous microinstruction in the microinstruction set. The instruction 126 is updated based on whether the architectural flag satisfies the condition. In contrast, the conditional move microinstruction 126 of FIG. 30 checks the architectural flag to confirm whether the condition is met. Finally, while the ALU microinstruction 126 of Figure 30 is an unconditional ALU microinstruction 126, the ALU microinstruction 126 of Figures 10 and 21 may be a conditional ALU microinstruction 126 in some cases.

When executed (E), the instruction translator 104 translates the conditional ALU instruction 124 into a non-conditional ALU microinstruction 3045 with a condition code for the execution unit 424 to execute. The unconditional ALU microinstruction 3045 with condition code includes an opcode field a252, a condition code field a254, fields a256 of source register 1 and source register 2, and a destination register field a258. The opcode field a252 contains a value to distinguish the unconditional ALU microinstruction 3045 with a condition code from other microinstructions within the microinstruction set architecture of the microprocessor 100 . The ALU function specified by the opcode a252 of the conditional ALU instruction 124 is communicated to the opcode field a252 of the non-conditional ALU microinstruction 3045 with the condition code. Fields a256 of source register 1 and source register 2 specify immediate values and architectural register 106 holds the operands with which the ALU operation specified by opcode a252 will be performed and produce a result. The result will be loaded into the architectural or scratch register 106 specified by the destination register field a258. In the case of execution, the instruction translator 104 fills the source register 1 and the source of the unconditional ALU microinstruction 3045 with the condition code with the same values as the source register 1 and the source register 2 of the conditional ALU instruction 124. Field a256 of register 2. When translating the conditional ALU instruction 124 , the instruction translator 104 fills the condition code field a254 of the non-conditional ALU microinstruction 3045 with the condition code with the same value as the condition code field a204 of the conditional ALU instruction 124 . The condition code a254 is used by the execution unit 424 to confirm whether the direction of the associated conditional ALU instruction 124 is mispredicted. When translating the conditional ALU instruction 124 , the instruction translator 104 fills the destination register field a258 with the same value as the destination register field a208 of the conditional ALU instruction 124 . Therefore, since the associated conditional ALU instruction 124 is predicted to execute, the unconditional ALU microinstruction 3045 with the condition code is an unconditional microinstruction that is executed regardless of whether the condition is met. However, the prediction of this non-conditional ALU microinstruction 3045 with a condition code is similar to a predicted branch instruction, since its execution prediction still needs to be reviewed, and in the case of a misprediction, the destination register will not be updated with the ALU result Instead, the architectural register 106 specified by field a258 is cleared, and the associated conditional ALU instruction 124 is repeatedly executed, this time without prediction. Conversely, if the execution prediction is correct, the architectural register 106 specified by the destination register field a258 is updated with the ALU result. In one embodiment, in addition to the non-conditional ALU microinstruction 126 with condition code of FIG. 30, when the conditional ALU instruction 124 specifies a preshift operation as described in FIGS. 10-28, the instruction translator 104 will In addition, a shift microinstruction 126 is translated for the conditional ALU instruction 124, and the shift microinstruction 126 precedes the non-conditional ALU microinstruction 126 with the condition code. For example, this shift microinstruction 126 is similar to the shift microinstruction described in step 1034 of FIG. 10, while the non-conditional ALU microinstruction 126 with condition code of FIG. 30 is modified to designate the scratch register as its The source operand register, this temporary register is the destination register of the shift microinstruction 126 . In the presence of a misprediction, this shift microinstruction 126 will be cleared in step 3134 of Figure 31 (described below), except for the non-conditional ALU microinstruction 126 with a condition code.

In the case of no execution (NE), the instruction translator 104 translates the conditional ALU instruction 124 into a no-operation microinstruction 3047 with a condition code for the execution unit 424 to execute. The no-op microinstruction 3047 with condition code includes an opcode field a272 and a condition code field a274. The opcode field a272 contains a value to distinguish the no-op microinstruction 3047 with the condition code from other microinstructions within the microinstruction set architecture of the microprocessor 100 . When translating the conditional ALU instruction 124, the instruction translator 104 fills the condition code field a274 of the no-op microinstruction 3047 with the condition code with the same value as the condition code field a204 of the conditional ALU instruction 124. The condition code a274 is used by the execution unit 424 to determine whether the course of the associated conditional ALU instruction 124 has been mispredicted. The no-op microinstruction 3047 with the condition code does nothing but cause the execution unit 424 to start to check the direction prediction for the conditional ALU instruction.

Please refer to FIG. 31 (including FIG. 31A and FIG. 31B ), which is a flowchart showing an embodiment of the microprocessor 100 of FIG. 29 executing a conditional ALU instruction 124 of FIG. 30 of the present invention. The process begins at steps 3102, 3104, and 3106 simultaneously.

In step 3102 , an instruction block containing the conditional ALU instruction 124 of FIG. 30 is fetched according to the fetch address 134 of the instruction cache 102 as shown in FIG. 29 . Next, go to step 3108.

In step 3104, the dynamic predictor 2932 looks at the fetch address 134 and provides the dynamic predictor 2982 to the instruction translator 104 of FIG. Next, go to step 3108.

At step 3106, the predictor selector 2934 looks at the fetch address 134 and provides a predictor selector 2984 to the instruction translator of FIG. 29. Next, go to step 3108.

At step 3108, the static predictor 2936 receives the conditional ALU instruction 124 and, after evaluation, provides a static prediction 2984 to the instruction translator 104 of FIG. 29 . Next, go to step 3112.

At step 3112, instruction translator 104 encounters conditional ALU instruction 124 and receives predictions 2982/2984/2986 from dynamic predictor 2932, predictor selector 2934, and static predictor 2936, based on which instruction translator 104 generates This conditional ALU instruction 124 trend prediction. Next, go to step 3114.

In step 3114, the instruction translator 104 confirms whether the conditional ALU instruction 124 it predicted in step 3112 was executed. If so, the flow goes to step 3116; otherwise, it goes to step 3118 for judgment.

At step 3116, the instruction translator 104 issues an unconditional ALU microinstruction 3045 with a condition code as shown in FIG. 30 based on the execution prediction. Next, go to step 3126.

At step 3118, the instruction translator 104 confirms whether the conditional ALU instruction 124 it predicted at step 3112 will not be executed. If so, the flow goes to step 3122; otherwise, it goes to step 3124.

In step 3122, the instruction translator 104 issues a no-op microinstruction 3047 with a condition code as shown in FIG. 30 based on the no-execution prediction. Next, go to step 3126.

At step 3124, in the absence of prediction, the instruction translator 104 issues the ALU microinstruction 3044 and the conditional move microinstruction 3046 as shown in FIG. 30 . Next, go to step 3126.

At step 3126, the execution unit 424 executes the microinstructions 126 issued by the instruction translator 104 at steps 3116, 3122 or 3124. Without prediction, execution unit 424 executes ALU microinstruction 3044 by executing the ALU function specified by opcode field a212 on the source operand specified in field a216 to generate a result, which is output to the result bus 128 and is assigned to the entry of the ALU microinstruction 3044 by the write rearrangement buffer, expecting to be able to write to the scratch register 106 specified by field a218 later. Once the result of the ALU microinstruction 3044 is available, the conditional move microinstruction 3046 can be sent to the execution unit 424 to confirm whether the flag 926 meets the condition specified by the condition code 244 . If so, the result of the ALU microinstruction 3044 (either from the steering bus or from the temporary register 106) will be output to the result bus 128 and written to the rearrangement buffer configured to the entry of the conditional move microinstruction 3046, which is expected to be written later into the architectural register 106 specified by field a232. However, if the condition is not satisfied, the original value of the architectural register 106 specified by the field a228 of the source register 2, that is, the architectural register specified by the destination register field a208 of the conditional ALU instruction 124, will be output to the result bus and be The write rearrangement buffer is allocated to the entry of the conditional move microinstruction 3046, and is expected to be later written to the architectural register 106 specified by field a232. The execution unit 242 also assigns a correct prediction to the reorder buffer (because the instruction translator 104 generates ALU microinstructions 3044 and conditional move microinstructions 3046 in response to no prediction). That is to say, in the case of no prediction, since there is no prediction, there will never be a misprediction. In the case of speculative execution, the execution unit 424 executes the unconditional ALU microinstruction 3045 with the condition code to generate a result by executing the ALU function specified by the opcode field a252 on the source operand specified by the field a256, This result is output to the result bus 128 and written to the rearrangement buffer allocated to the entry of the unconditional ALU microinstruction with the condition code, which is expected to be written to the architectural register 106 specified by field a258. The execution unit 424 also confirms whether the flag 926 satisfies the condition specified by the condition code a254, and provides an indicator to the rearrangement buffer 422 accordingly. Further, the execution unit 424 will only indicate a misprediction to the reorder buffer 422 when the flag 926 does not satisfy the condition specified by the condition code a254, because the instruction translator 104 would generate a Unconditional ALU microinstruction 3045 for condition code, otherwise indicates correct prediction. In the case of no execution, the execution unit 424 will not perform any operation in response to the execution of the no-operation microinstruction 3047 with the condition code. In addition, the execution unit 424 confirms whether the flag 926 satisfies the condition specified by the condition code a274 and provides an indicator to the rearrangement buffer 422 accordingly. Further, the execution unit 424 will indicate a misprediction to the rearrangement buffer 422 only when the flag satisfies the condition specified by the condition code a254. This is because the instruction translator 104 will generate a misprediction when the prediction is not executed. The condition code does not operate the microinstruction 3047, otherwise it indicates a correct prediction. Next, the decision step 3128 is entered.

At decision step 3128, the reorder buffer 422 determines whether the course of the conditional ALU instruction 124 was mispredicted based on the misprediction pointer 2976 received from the execution unit 242. If yes, the process goes to step 3134; if not, goes to step 3132.

At step 3132, the reorder buffer 422 updates the architectural state of the microprocessor 100 with the result of the conditional ALU instruction 124, ie, the architectural registers 106 and the flags 926 are updated. Further, since reorder buffer 422 must retire instructions in program order, reorder buffer 422 will conditionally move microinstructions 3046 (in the unpredicted case), non-conditional ALU microinstructions 3045 with condition codes (in the In the case of speculative execution), or when a no-op microinstruction 3047 with a condition code (in the case of speculative non-execution) becomes the oldest microinstruction in the microprocessor 100, the architectural state is updated. Next, go to step 3136.

In step 3134, the rearrangement buffer 422 generates a true value in the misprediction indicator 2976, so that the microinstructions generated by the translation of the conditional ALU instruction 124 and all microinstructions associated therewith are cleared. In addition, generating a true value in the misprediction indicator 2976 also causes the conditional ALU instruction 124 to repeat execution. That is, the instruction translator 104 translates the conditional ALU instruction 124 again, but this time according to the no-prediction principle of step 3124. According to another embodiment, when the conditional ALU instruction 124 is repeatedly executed, the instruction translator 104 inverts the correct prediction and translates according to the inverted prediction. That is to say, if the predicted execution is a misprediction, the instruction translator 104 will execute the translation according to the principle of the predicted execution. If the predicted execution is a misprediction, the instruction translator will execute the translation according to the predicted execution principle. However, it is worth noting that this embodiment is prone to livelock situations.

At step 3136, the rearrangement buffer 422 provides the historical data update pointer 2974 with the appropriate value to the dynamic predictor 2932 and predictor selector 2934, and based on the execution unit 424 evaluating the correct direction and predicting information flowing along the pipeline 2982/2984 /2986 to update the dynamic predictor 2932 and predictor selector 2934.

It can be found from the foregoing that the microprocessor 100 of the present invention translates a conditional ALU instruction 124 into a single microinstruction instead of multiple microinstructions, that is, when the trend can be predicted, it will have a great advantage.

First, the present invention can reduce one or more microinstructions that need to occupy additional instruction slots in the resources of the non-sequential execution microprocessor 100 . These resources include register allocation table 402 , reorder buffers, reservation stations (not shown), and execution units 424 . Therefore, the present invention can reduce and simplify the resources required to be used, and the energy consumed by these resources can also be reduced.

Second, the average number of instruction set architecture (eg, ARM instructions) program instructions that the instruction translator 104 can translate per clock cycle will increase. It is assumed that the instruction translator 104 can translate up to three ARM instructions per clock cycle, but a maximum of three micro-instructions can only be issued per clock cycle, and the instruction translator 104 must release the associated instructions in the same clock cycle. An additional restriction on all microinstructions of this ARM instruction, that is, the instruction translator 104 cannot issue a microinstruction associated with an ARM instruction in the first clock cycle, and issue a microinstruction associated with the ARM instruction in the next clock cycle. The second microinstruction. Assume the following ARM instruction sequence, where CAI is a conditional ALU instruction 124 and the "Rx" value is a general-purpose register:

CAI EQ R1, R2, R3

CAI NE R4,R5,R6

CAI CS R7,R8,R9

In processors that do not have predictors 2932/2934/2936 (or have but do not predict), the instruction translator 104 must take three clock cycles to translate the three CAI instructions. However, in processors with predictors 2932/2934/2936 for prediction, the instruction translator can translate all three CAI instructions on the same clock cycle. Furthermore, this advantage is still valid in the case of mixing non-CAI instructions, ie other ARM instructions. For example, suppose that the CAI instruction is followed by an ARM instruction D that will be translated into two microinstructions, and the direction of the CAI instruction is predicted by the predictor 2932/2934/2936, and one will be translated into two microinstructions. ARM instruction E is followed by CAI instruction, an ARM instruction F followed by ARM instruction E which will be translated into a single microinstruction. In this case, the instruction translator can translate ARM instructions D and CAI instructions on the same clock cycle, and then translate ARM instructions E and F in the next clock cycle. That is, four ARM instructions are translated in two clock cycles. In contrast, without the functionality provided by this embodiment, the instruction translator 104 would need three clock cycles to translate the four instructions. Similar advantages can also be found in instruction issue unit 408 and reorder buffer 422 .

Third, the latency of the conditional ALU instruction 124 can be expected to be reduced when the direction is predicted by the predictors 2932, 2934, and 2936, so that the instruction translator 104 only needs to issue a single microinstruction.

Fourth, there are no additional micro-instructions in the rearrangement buffer and the reservation station, which can improve the look-ahead capability of the microprocessor, thereby improving the parallel processing capability of the processor for the instruction level of the executed program, thereby improving the execution unit. 424 is utilized to improve the throughput of the microprocessor 100 . Further, omitting the second uops may reserve more space in the reorder buffer for uops. The advantage of this feature is that it produces a larger pool of microinstructions for sending microinstructions to execution unit 424 for execution. The microinstruction cannot be sent for execution until it is "completed preparation", which means that in this microinstruction, all the source operands from the previous microinstruction can be sent out only when all the source operands from the previous microinstruction are available. Therefore, the larger the microinstruction pool in which the microprocessor 100 looks for the prepared microinstruction, the greater the chance of finding it, and thus the greater chance of the execution unit 424 being utilized. This is often referred to as the look-ahead capability of a microprocessor, which is to take full advantage of the instruction-level parallel processing capability of the program to be executed by the microprocessor. The greater the look-ahead capability, the more generally the utilization of the execution unit 424 will be improved. Therefore, the microprocessor 100 of the present invention has the potential to improve its look-ahead capability by translating the conditional ALU instruction 124 into a single microinstruction rather than multiple microinstructions.

Although the micro-architecture of the aforementioned embodiment supports the ARM instruction set architecture conditional ALU instruction, it also supports the x86 instruction set architecture, it is worth noting that the present invention can also be applied to other embodiments, that is, supports different ARM instruction set architectures. Conditional ALU instructions for other instruction set architectures. Secondly, it should be noted that the present invention can also be applied to the situation where there is no pre-existing micro-architecture or the instruction set architecture supported by the pre-existing micro-architecture is not the x86 instruction set architecture. In addition, it should be noted that the invention described herein is a broad processor concept that supports conditional ALU instructions of an instruction set architecture by predicting the direction of conditional ALU instructions in the pipeline in advance prior to execution of the instruction. For one embodiment, it is similar to a branch prediction technique, which confirms the fetched instruction stream and issues different microinstruction sequences depending on the presence or absence of direction prediction. Furthermore, although the embodiments described herein include both dynamic predictors and static predictors, the present invention may also be applied to embodiments having only static predictors or only dynamic predictors. Second, the present invention can also be applied to embodiments with multiple dynamic and/or static predictors, wherein the predictor selector is selected from multiple dynamic and static predictors. Furthermore, the present invention can also be applied to the embodiment in which the dynamic predictor is integrated into a branch prediction array, such as a branch target address cache. The disadvantage of this embodiment is that the space used to store the target address of a branch instruction at each entry is wasted because the target address of a conditional ALU instruction does not need to be predicted. Based on instruction mixing in the program, although there may be interference or pinning between branch instructions and conditional ALU instructions, this embodiment may still have the following advantages: the storage space of the integrated cache is more efficiently used, and the integrated An array may have more entries than the sum of the entries of the individual arrays.

Although the foregoing embodiments are directed to conditional non-branch instructions that are conditional ALU instructions, the present invention can also apply predictors to predict other types of conditional non-branch instructions. For example, conditional load instructions can be predicted. For speculative execution, the instruction translator generates an unconditional load microinstruction with a condition code. This unconditional load microinstruction with condition code contains the condition specified by the conditional load instruction, enabling the execution pipeline to detect misprediction. If the execution pipeline detects a misprediction, it avoids performing any architectural state update operations, such as updating a page table walk in memory when a load causes a translation lookaside buffer (TLB) miss, or when a load results in a A schema exception event is generated when the exception state occurs. Additionally, if load misses occur in the cache, the execution pipeline avoids generating transfers on the processor bus to fill the missed cache lines. If the prediction result is unpredicted, the instruction translator will generate a microinstruction set to conditionally execute the load operation. In one embodiment, if the prediction result is no prediction, the microinstruction set may be in a manner similar to that described in US Patent Provisional Application 61/473,062.

Although the above embodiments relate to ARM ISA conditional non-branch instructions, the present invention can also utilize a predictor to predict conditional non-branch instructions that apply to other ISAs. For example, conditional non-branch instructions of the x86 ISA such as CMOVcc and SETcc can be predicted.

Corrected immediate value applied to instruction translation

The ARM instruction set architecture defines a data processing instruction set that allows an instruction to specify an immediate source operand, also referred to herein as an "immediate operand instruction". The immediate source operand is a 32-bit value produced by right-rotating an 8-bit value by twice a 4-bit value. The 8-bit value is specified in the field marked immed_8 in the instruction, and the 4-bit value is specified in the field marked rotate_imm in the instruction. therefore

Immediate operand value = immed_8>>(2*rotate_imm)

A method of processing immediate operand instructions within an existing microarchitecture is to have the instruction translator generate two microinstructions. The first microinstruction performs a rotation operation on the immed_8 value twice the value of rotate_imm to generate a result, and the second microinstruction receives the result of the first microinstruction as a source operation for executing the ALU function specified by the immediate operand instruction number. For this embodiment, refer to FIGS. 10 and 21 . For example, in step 1034 of FIG. 10 , the instruction translator generates SHF microinstructions to perform a shift operation (in this embodiment, a rotation operation) to generate a shifted result to write into a temporary register, and then The ALUOP microinstruction can use the shift result produced by the SHF microinstruction in the scratch register. This shift operation may be performed on an immediate value specified in an immediate operand instruction (eg, corresponding to steps 1012 and 1024 of FIG. 10 ). However, compared with the method of using an instruction translator to generate only a single microinstruction, the application of this method to a non-sequential processor may have the following disadvantages.

First, this extra microinstruction occupies an extra instruction slot in various resources of the non-sequential processor, such as register allocation table, rearrangement buffer, reservation station and extra instruction slot or entry in the execution unit, thus requiring Larger and more complex resources, the energy consumption will also be higher.

Second, some functional units are limited by the maximum number of instructions that can be executed per clock cycle. For example, according to an embodiment, the instruction translator can issue a maximum number of instructions per clock cycle (for example, three micro-instructions per clock cycle), and the issue unit can issue an execution unit per clock cycle. The unit has a maximum limit on the number of instructions (such as four microinstructions per clock cycle), and the number of instructions that the retirement unit can retire per clock cycle has its maximum limit (for example, three microinstructions per clock cycle) . Therefore, the generation of additional micro-instructions within these functional units reduces the average number of instructions that can be issued, issued or retired per clock cycle, thereby limiting the performance of the processor.

Third, the immediate operand instruction will not retire until its constituent microinstructions are executed, because the second microinstruction is related to the result of the first microinstruction, so the second microinstruction cannot Sent to the execution unit. These all cause additional delays to the total execution time of immediate operand instructions.

Fourth, the presence of additional microinstructions in the rearrangement buffer and/or reservation station reduces the look-ahead capability of the processor, thereby reducing the processor's ability to execute programs using instruction-level parallel processing, thereby reducing execution unit utilization , reducing the overall performance of the processor.

The embodiments described herein have the potential to perform better when executing immediate operand instructions. The combination of the immed_8 field and the rotate_imm field is referred to herein as an "immediate field". In particular, the instruction translator knows a predetermined subset of immediate field values and the associated 32-bit immediate operand values resulting from each corresponding immediate field value. When the instruction translator encounters an immediate operand instruction, the instruction translator checks whether the specified immediate field value falls within the predicted subset. If so, the instruction translator issues the correct 32-bit immediate operand to the immediate operand bus and, along with the immediate operand instruction, is passed down the pipeline for execution. If the immediate field value does not fall within the predetermined subset, the instruction translator takes a less efficient approach, ie, issuing two microinstructions. The relative frequency of different immediate field values can be generated by executing the application software and observing, and selecting the few most frequently observed immediate field values as a preset set of immediate field values to maintain their size, power consumption, and complexity of the instruction translator degree is within a certain range.

Please refer to the block diagram of FIG. 32 , which shows the situation in which the microprocessor 100 of the present invention processes the modified immediate constant during the instruction translation process. The microprocessor 100 of FIG. 32 is similar to the microprocessor of FIG. 1 and includes elements similar to those shown in FIGS. 1-4, including an instruction cache 102, an instruction translator 104, configuration registers 122, registers Configuration table 402 , instruction issuing unit 408 and execution unit 424 . Execution unit 424 includes one or more units for executing microinstructions 126 described below. Further, execution unit 424 includes one or more units to execute rotate right (ROR) microinstructions 3344 (also referred to herein as shift microinstructions), ALU microinstructions 3346, and immediate ALU microinstruction 3348. The microprocessor 100 also includes the architectural and temporary registers 106 and flags 926 shown in FIG. 33 . The instruction cache 102 fetches the immediate operand instruction 124 shown in FIG. 33 .

In one embodiment, the microarchitecture of the microprocessor 100 is similar in many aspects to the microarchitecture of the VIA Nano ^™ processor produced by Taiwan's VIA Electronics, but the microprocessor 100 of this embodiment is modified to support ARM Instruction set architecture. The microarchitecture of the VIA Nano ^™ processor is a high performance non-sequential execution superscalar microarchitecture to support the x86 instruction set architecture. The processor is modified as described herein to enable additional support for the ARM microarchitecture, in particular Support for ARM immediate operand instructions 124 is described in detail in the relevant section of FIG. 33 . Further, when the instruction translator 104 encounters an immediate operand instruction 124, and the value of the specified immediate field b207 (please refer to FIG. 33 ) falls within the set of known values of the instruction translator 104 In response to a predetermined subset, an immediate operand 3366 is issued on an immediate operand bus. The immediate operand 3366 is passed down the stages of the microprocessor 100 pipeline until it reaches the execution unit 424 .

The register configuration table 402 receives the microinstructions 164 from the instruction translator 104 and generates relevant information of each microinstruction 164 correspondingly. Further, the register configuration table 402 indicates that the ALU microinstruction 3346 (refer to FIG. 33 ) is associated with the result of the ROR microinstruction 3344 (refer to FIG. 33 ), and the instruction translator 104 translates an immediate operand instruction, When the specified immediate field value b207 does not fall within a predetermined subset formed by the value of the immediate field b207, the two micro-instructions will be issued together. In addition, as shown in FIG. 34 (including FIGS. 34A and 34B ), in the event that the instruction translator 104 additionally issues a conditional move microinstruction 126 (such as that described in FIG. 10 ), the register allocation table 402 will indicate that this condition Move microinstruction 126 is associated with the result of ALU microinstruction 3346.

Temporary registers 106 store the non-architectural state of microprocessor 100 and may be used by the micro-architecture to temporarily store intermediate values required to execute instructions 124 of the instruction set architecture. Further, microinstructions 126 issued by instruction translator 104 designate temporary registers 106 as source and/or destination operand locations. The ROR microinstruction 3344 shown in FIG. 33 designates a temporary register 106 as its destination register, while the ALU microinstruction 3346 designates the same temporary register 106 as one of its source registers. This will be explained in more detail in the following sections.

At least one execution unit 424 includes an arithmetic logic unit (not shown) for executing various microinstructions. These microinstructions include the ROR microinstruction 3344, the ALU microinstruction 3346, and the immediate ALU microinstruction 3348 shown in FIG. In the case of immediate ALU microinstruction 3348, execution unit 424 receives as its input the value of immediate operand 3366 from instruction translator 104. The execution unit 424 performs the ALU function specified by the opcode field b212, which is identical to the ALU function specified by the immediate operand instruction 124, and the instruction executes on the immediate operand 3366 and a second source operand above. In the case of ALU microinstruction 3346, execution unit 424 executes the ALU function specified by opcode field b212, which is the same as the ALU function specified by immediate operand instruction 124, and which executes from two sources On top of the operands, one of the two source operands is from scratch register 106, and the associated ROR microinstruction 3344 writes its result into this register. In the case of the ROR microinstruction 3344, the execution unit 424 rotates an 8-bit value to the right by twice as much as a 4-bit value to generate a 32-bit immediate value and write to a temporary register 106 for subsequent correlation The ALU microinstruction 3344 uses. The aforementioned 8-bit value is the same as the value specified by the immed_8 field b208 of the immediate operand instruction 124 , and the aforementioned 4-bit value is the same as the value specified by the rotate_imm field b209 of the immediate operand instruction 124 .

Please refer to FIG. 33, which is a block diagram showing that the present invention selectively translates an immediate operand instruction 124 into a ROR microinstruction 3344 and an ALU microinstruction 3346, or into an immediate ALU microinstruction 3348 an embodiment of. As described herein, instruction translator 104 translates immediate operand instruction 124 into an immediate ALU microinstruction 3348 for execution units when the value specified by immediate field b207 falls within a predetermined subset known to instruction translator 104 424 is executed, whereby the instruction translator 104 issues a corresponding evaluated immediate operand value 3366. As shown in FIG. 32, when the value specified by the immediate field b207 does not fall within the predetermined subset, the instruction translator 104 translates the immediate operand instruction 124 into a ROR microinstruction 3344 followed by an ALU microinstruction 3044 for the execution unit 424 execute. In one embodiment, the immediate operand instruction 124 is an immediate operand instruction defined by the ARM instruction set architecture. In ARM parlance, it is an instruction with a data processing immediate encoding function.

The immediate operand instruction 124 includes an opcode field b202, a source register 1 field b204, a destination register field b206, an immed_8 field b208, and a rotate_imm field b209. As shown in FIG. 33, the combination of the immed_8 field b208 and the rotate_imm field b209 constitutes the immediate field b209. The opcode field b202 contains a value to distinguish the immediate operand instruction 124 from other instructions of the instruction set architecture, and the value specifies an ALU function to perform on the source operand. For an ARM immediate operand instruction 124, the ALU functions include, for example, add (ADD), add with carry (ADC), logical AND (logical AND, AND), logical bit clear ( logical bit clear, BIC), compare negative (CMN), compare (compare, CMP), logical exclusive-OR (logical exclusive-OR, EOR), move (move, MOV), reverse move (move not, MVN), logic OR (ORR), reverse subtract (RSB), reverse subtract with carry (RSC), subtract with carry (SBC), subtract ( subtract, SUB), test equivalence (TEQ) and test (test, TST). Field b204 of source register 1 specifies an architectural register 106 or a temporary register 106 from which the source operand received by the execution unit 424 is derived. The destination register field b206 specifies either an architectural register 106 or a temporary register 106, and the result is written to the specified register. The aforementioned immed_8 field b208 holds an 8-bit constant that is rotated right by twice the value of the aforementioned 4-bit rotate_imm field b209 to generate an immediate source operand. The immediate operand instruction 124 may include a conditional ALU instruction, as described above in the embodiments of FIGS. 9-28. For example, the immediate operand instruction 124 may be an ARM NCUALUOP instruction 124 as described in step 1056, which specifies a modified immediate constant as its source operand, rather than a register.

The ROR microinstruction 3344 includes an opcode field b222, a destination register field b226, and two source operand fields for specifying source operands. As shown in Figure 33, they are marked as immed_8 field b228 and rotate_imm field b229, respectively. to execute the immediate operand instruction 124. The opcode field b222 contains a value for distinguishing the ROR microinstruction 3344 from other microinstructions of the microinstruction set architecture of the microprocessor 100 . The destination register field b226 specifies an architectural register 106 or a destination register 106 into which the result of the ROR microinstruction 3344 will be written. When the instruction translator 104 translates the immediate operand instruction 124 and the value specified by the immediate field b207 does not fall into the predetermined subset, the instruction translator 104 will use the immed_8 field b208 of the immediate operand instruction to correspond to the rotate_imm field b209 The value is filled in the immed_8 field b228 and the rotate_imm field b229, and the instruction translator 104 will fill in the destination register field b226 to designate a temporary register 106 to receive the result of the ALU function, which will be subsequently used by the ALU microinstruction 3344 as a its source operand. In addition to the foregoing, the ROR microinstruction 3344 may also include a shift microinstruction 126 (designated SHF from FIG. 10 onwards) to specify a modified immediate constant, which is described in greater detail in FIGS. 10 and 11 . For example, if the translated immediate operand instruction 124 is the ARM NCUALUOP instruction 124 that specifies a modified immediate constant as described in step 1056 , the ROR microinstruction 3344 may be the SHF microinstruction 126 in step 1056 .

The ALU microinstruction 3346 includes an opcode field b232, a source register 1 field b234, a source register 2 field b235, and a destination register field b236. The opcode field b232 contains a value to distinguish the ALU microinstruction 3346 from other microinstructions of the microinstruction set architecture of the microprocessor 100, and the ALU function it specifies to execute on the source operand is the same as The immediate operand instruction 124 translates the resulting ALU function. Field b234 of source register 1 specifies an architectural register 106 or a temporary register 106 from which the first source operand will be provided to the ALU microinstruction 3346, and field b235 of source register 2 specifies an architectural register 106 or is a temporary register 106 from which the second source operand will be provided to the ALU microinstruction 3346. The destination register field b236 specifies an architectural register 106 or a temporary register 106. The result of the ALU microinstruction 3346 will be Write to the specified register. When the instruction translator 104 translates the immediate operand instruction 124 and the value specified by the immediate field b207 does not fall into the predetermined subset, the instruction translator 104 fills the field b234 of the source register 1 to specify a register which is the same as the immediate source operation The source operand 1 of the number instruction 124 is the same as that specified by field b204, the instruction translator 104 will fill in the destination register field b236 to specify a register, which is the same as that specified by the destination register field b206 of the immediate source operand 124, the instruction Translator 104 also fills in field b235 of source register 2 to designate a temporary register 106 that is the same as that designated by destination register field b226 of ROR microinstruction 3344. As previously mentioned, the ALU microinstructions 3346 may include any of the ALU operation microinstructions 126, designated ALUOP, ALUOPUC, CALUOP, and NCALUOP, respectively, as well as the conditional versions of the microinstructions detailed in Figures 10 and 12. For example, if the translated immediate operand instruction 124 is the ARM NCUALUOP instruction 124 described in step 1056, and the modified immediate constant specified by this specification does not fall within the predetermined subset, the ALU microinstruction 3346 will Possibly the NCUALUOP microinstruction 126 in step 1056.

Immediate ALU microinstruction 3348 includes an opcode field b212, a source register 1 field b214, a destination register field b216, and an immediate-32 field b218. For one embodiment, the immediate-32 field b218 is the immediate operand 3366 received by the execution unit 424 executing the immediate ALU microinstruction 3348 . That is, an operand multiplexer (not shown) operates to select the immediate operand 3366 to be provided to the execution unit 424 that receives the immediate ALU microinstruction 3348. The opcode field b212 contains a value to distinguish the ALU microinstruction 3348 from other microinstructions in the microinstruction set architecture of the microprocessor 100, and the ALU function it specifies to execute on the source operand is the same as the immediate operand Instruction 124 translates the resulting ALU function. Field b214 of the source register 1 specifies an architectural register 106 or a temporary register 106 from which a first source operand will be provided to the ALU microinstruction 3346, and the destination register field b216 specifies an architectural register 106 or a temporary register 106, the result of the immediate ALU microinstruction 3348 will be written to this designated register. When the instruction translator 1045 translates the immediate operand instruction 124 and the value specified by the immediate field b207 falls within the predetermined subset, the instruction translator 104 fills the field b214 of the source register 1 to specify a register, which is the same as the immediate operand instruction 124 specified by field b204 of source operand 1, instruction translator 104 fills in destination register field b216 to specify a register that is identical to that specified by destination register field b206 of immediate operand instruction 124. As previously mentioned, the immediate ALU microinstructions 3346 may include any ALU operation microinstructions 126, labeled ALUOP, ALUOPUC, CALUOP, and NCALUOP, respectively, including the conditional versions of the microinstructions detailed in Figures 10 and 12 to specify an immediate source operand. For example, if the translated immediate operand instruction 124 is the ARM NCUALUOP instruction 124 described in step 1056, and the specified modified immediate constant falls within a predetermined subset, the immediate ALU microinstruction 3348 may be step 1056 The NCUALUOP microinstruction 126 within the instruction translator 104 will not issue the SHF microinstruction 126 of step 1056 to provide the aforementioned advantages associated with using the instruction translator 104 to process the immediate postfix constant.

Please refer to FIG. 34 , which is a flowchart showing an embodiment of the operation of the microprocessor 100 of FIG. 32 to execute an immediate operand instruction of FIG. 33 of the present invention. The process begins at step 3402.

In step 3402, instruction translator 104 encounters an immediate operand instruction 124 of FIG. 33, and checks immediate field b207 with a predetermined subset of values (for an ARM immediate operand instruction 124, that is located in the lower 12 bits). Next, a decision step 3404 is entered.

In decision step 3404, instruction translator 104 determines whether the value of immediate field b207 falls within the predetermined subset of values. If so, go to step 3406; otherwise, go to step 3414.

At step 3406, the instruction translator 104 issues a single immediate ALU microinstruction 3348 as shown in FIG. 33 in response to the immediate operand instruction 124. In one embodiment, if the immediate operand instruction 124 is a conditional ALU instruction 124 specifying a source-destination shared register, the immediate ALU microinstruction 3348 will include the ALUs described in steps 2134, 2136, 2154 and 2156 of FIG. 21 . One of the microinstructions 126, but does not contain the aforementioned SHF microinstructions. If the conditional ALU instruction 124 does not specify a source-destination shared register, the instruction translator 104 will issue an immediate ALU microinstruction 3348 and a conditional move microinstruction 126 ( XMOV and CMOV), but does not contain the aforementioned SHF microinstructions. In this case, the association information of the conditional move microinstruction 126 generated by the register allocation table 402 will indicate that the conditional move microinstruction 126 is associated with the result of the immediate ALU microinstruction 3348. Next, step 3408 is entered.

At step 3408, the instruction issue unit 408 issues the immediate ALU microinstruction 3348 to the execution unit 424. Next, go to step 3412.

In step 3412, the execution unit 424 receives from the immediate operand bus the value of the 32-bit immediate operand 3366 transmitted through the pipeline, and the source operand specified by field b214 of source register 1. The process of executing the immediate ALU microinstruction 3348 by the execution unit 424 is to execute the ALU function specified by the opcode field b212 on the 32-bit immediate operand 3366 and other source operands to generate the result to the result bus 128 for the destination register field b216 The specified architectural register 106 is the same as the architectural register 106 specified by the destination register field b 206 of the immediate operand instruction 124 for subsequent retirement operations. If, in step 3406, the instruction translator 104 issues a conditional move microinstruction 126, the result of the immediate ALU microinstruction 3348 is destined to be a temporary register 106 rather than the destination register 106 specified by the immediate operand instruction 124, and , in order to respond to the execution unit 424 in step 3412 to complete the operation of the immediate ALU microinstruction, as described above, especially in FIGS. 10 to 20 , the instruction issuing unit 408 will issue the conditional move microinstruction 126 to the execution unit 424, and the execution unit 424 will This conditional move microinstruction 126 is executed to produce the result of the immediate operand instruction 124 . The process ends at step 3412.

In step 3414 , the instruction translator 104 issues two microinstructions, namely a ROR microinstruction 3344 and an ALU microinstruction 3346 in FIG. 33 , in response to the immediate operand instruction 124 . In one embodiment, if the immediate operand instruction 124 is a conditional ALU instruction 124 specifying a modified immediate constant, the ROR microinstruction 3344 would include steps 1034, 1034, 1054, and 1056 in FIG. Steps 2134, 2136, 2154 and 2154 describe the SHF microinstruction 126. For example, if the translated immediate operand instruction 124 is the ARM NCUALUOP instruction 124 in step 1056 and the specified modified immediate constant does not fall within the predetermined subset, the ROR microinstruction 3344 may be step 1056 SHF microinstructions in 126. In one embodiment, if the conditional operand instruction 124 is a conditional ALU instruction 124 that specifies a source-destination shared register, the ALU microinstruction 3346 may include the ALU described in steps 2134, 2136, 2154 and 2156 of FIG. 21 . One of the microinstructions 126. If the immediate operand conditional ALU instruction 124 does not specify a source-destination common register, the instruction translator 104 will issue the ALU microinstruction 3346 and a conditional move microinstruction 126 as described in steps 1034, 1036, 1054 and 1056 of FIG. (XMOV and CMOV). Next, go to step 3416.

At step 3416, the register configuration table 402 generates dependency information for the ALU microinstruction 3346, indicating that the ALU microinstruction 3346 is associated with the result of the ROR microinstruction 3344. If, in step 3414, the instruction translator 104 issues a conditional move microinstruction 126, the register configuration table 402 will generate the association information of the conditional move microinstruction 126, indicating that the conditional move microinstruction 126 is associated with the result of the ALU microinstruction 3346. . Next, go to step 3418.

In step 3418 , the instruction issue unit 408 issues the ROR microinstruction 3344 to the execution unit 424 . Therefore, the execution unit 424 receives the values of the immed_8 field b208 and the rotate_imm field b209 specified by the immediate operand instruction 124 . Next proceeds to decision step 3412.

In step 3422, the execution unit 424 executes the ROR microinstruction 3344 to generate an immediate operand result, which is written to the scratch register 106 specified by the destination register field b226. Next, go to step 3424.

In step 3424 , in response to the execution unit 424 completing the operation of the ROR microinstruction 3344 in step 3422 , the instruction issuing unit will issue the ALU microinstruction 3346 to the execution unit 424 . Therefore, the execution unit 424 (integer unit 124) receives the result of the ROR microinstruction 3344 generated in step 3422 and the operand value specified by the field b234 of the source register 1 of the ALU microinstruction 3346, the operand value and the immediate operand The architectural register 106 specified by the field b204 of the source register 1 of the instruction 124 is the same. Next proceeds to decision step 3426.

In step 3426, the execution unit 424 executes the process of the ALU microinstruction 3346, which executes the ALU function specified by the opcode field b232 on the two source operands to generate a result that is provided to the result bus 128 for the destination register field b236. The specified architectural register 106 is used in subsequent retirement steps, and this architectural register 106 is the same as the architectural register 104 specified by the destination register field b 206 of the immediate operand instruction 124 . If, in step 3414, the instruction translator 104 issues a conditional move microinstruction 126, the result of the ALU microinstruction 3346 is destined to be a temporary register 106 rather than the destination register 106 specified by the immediate operand instruction, and, in response to the execution The unit 424 completes the operation of the ALU microinstruction 3346 in step 3426, and the instruction issuing unit 408 will issue the conditional move microinstruction 126 to the execution unit 424, and as described above, especially in Figures 10 to 20, the execution unit 424 will execute the conditional move Microinstruction 126 to produce the result of immediate operand instruction 124 . The process ends at step 3426.

As can be seen from the foregoing, the microprocessor 100 of the present invention translates the immediate operand instruction 124 into a single immediate ALU microinstruction 3346 under certain circumstances, rather than a plurality of microinstructions. In some cases, namely when the immediate field b 207 falls within a predetermined subset of values, and the instruction translator 104 can directly issue the value of the corresponding evaluated immediate operand 3 366, a considerable contribution may be provided .

First of all, the present invention can reduce one microinstruction from occupying an extra instruction slot in each resource of the non-sequential execution processor, such as the register allocation table 402 , the rearrangement buffer 422 , the reservation station 406 and the extra instruction slot in the execution unit 424 Or entrance, so resources can be reduced and simplified, and energy consumption can also be reduced.

Second, the average number of instructions for programs of instruction set architectures (eg, ARM instructions) that can be translated by the instruction translator 104 in each clock cycle can be increased. For example, it is assumed that the instruction translator 104 can translate up to three ARM instructions per clock cycle, but can only issue up to three microinstructions per clock cycle, and it must also comply with the same clock cycle. The restriction on issuing all microinstructions associated with this ARM instruction, that is, the instruction translator 104 cannot issue a microinstruction associated with an ARM instruction in a first clock cycle, and at the same time issue a microinstruction associated with an ARM instruction in the next clock cycle. The second microinstruction of this ARM instruction. Suppose the ARM instruction sequence is as follows, where IOI is an immediate operand instruction 124, such as a conditional ALU instruction, which specifies a destination register, which is also a source register, and the "Rx" value is a general-purpose register:

IOI R1, R1, immediate field value A

IOI R3, R3, immediate field value B

IOI R5, R5, immediate field value C

In the case where the immediate field values A, B, and C do not fall within the predetermined subset, the instruction translator 104 must take three clock cycles to translate the three IOI instructions. However, in the event that the immediate field values A, B, and C fall within a predetermined subset, the instruction translator 104 may only need one clock cycle to translate the three IOI instructions. In addition, this advantage can also be confirmed in other examples mixed with non-IOI instructions, ie other ARM instructions. For example, suppose an ARM instruction D is translated into two microinstructions, followed by an IOI instruction that specifies an immediate field value that falls within a predetermined subset, followed by an IOI instruction An ARM instruction E, which is translated into two microinstructions, followed by an ARM instruction F, which is translated into a single microinstruction. In this case, the instruction translator 104 can translate the ARM instructions D and IOI instructions in a single clock cycle, and then translate the ARM instructions E and F in the next clock cycle, that is, four ARM instructions in two clock cycles complete the translation within. In contrast, without the functions described in this embodiment, the instruction translator 104 would require three clock cycles to translate the four instructions. Similar advantages exist for the instruction issue unit 408 and the retirement unit 422 . Similar advantages also occur in the case of four-wide instruction translators and conditional ALU instructions that do not specify a destination register and a source register at the same time. In this case, two instructions can be in the same Translation is performed within the clock cycle. If there is no function described in this embodiment, two clock cycles are required.

Third, in the case where the value of immediate field b207 falls within a predetermined subset, and the instruction translator 104 can issue a single microinstruction (or two instead of three), because the second (or third) The disappearance of the microinstruction can reduce the latency of the immediate operand instruction 124 .

Fourth, there are no additional micro-instructions in the rearrangement buffer and/or the reservation station, which can improve the look-ahead capability of the processor, thereby improving the capability of the microprocessor 100 to execute programs using the parallel processing of the instruction hierarchy, and increasing the capacity of the execution unit 424. The utilization rate improves the overall performance of the microprocessor 100 . Further, reducing the second microinstruction may free up more space in the reorder buffer for microinstructions, which may result in a larger pool of microinstructions that can be dispatched to the execution unit 424 for execution. The microinstruction cannot be sent for execution until it is "completed preparation", which means that in this microinstruction, all the source operands from the previous microinstruction can be sent out only when all the source operands from the previous microinstruction are available. Therefore, the larger the microinstruction pool in which the microprocessor 100 looks for the prepared microinstruction, the greater the chance of finding it, and thus the greater chance of the execution unit 424 being utilized. This is often referred to as the look-ahead capability of a microprocessor, which is to take full advantage of the instruction-level parallel processing capability of the program to be executed by the microprocessor. The greater the look-ahead capability, the more generally the utilization efficiency of the execution unit 424 will be improved. Therefore, the microprocessor 100 of the present invention can translate the immediate operand instruction 124 into a single immediate ALU microinstruction 3348 according to the value of the immediate field b207 instead of multiple microinstructions, thus potentially improving its look-ahead capability.

Although the immediate operand instruction in the foregoing embodiment is an ARM instruction with data processing immediate encoding function, this technique can also be applied to translate immediate operand instructions of other instruction set architectures; secondly, it should be noted that the present invention can also Applies when there is no pre-existing microarchitecture, or where the pre-existing microarchitecture supports an instruction set architecture other than the x86 instruction set architecture. Furthermore, it is worth noting that the invention described herein is a broad processor concept that translates an operand instruction into a random operation depending on whether the immediate field value specified by the immediate operand instruction falls within a predetermined subset. Different microinstruction sequences of the microarchitecture are executed sequentially to support immediate operand instructions of an instruction set architecture.

In another embodiment, instruction translator 104 generates immediate operand 3266 of FIG. 32 to all values of immediate field b207 of immediate operand instruction 124 of FIG. 33 . That is, all values within the predetermined subset of values of immediate field b207 are possible values of immediate field b207. The following is the Verilog hardware description language encoding for this embodiment.

Only the above are only preferred embodiments of the present invention, and should not limit the scope of the present invention, that is, any simple equivalent changes and modifications made according to the scope of the claims of the present invention and the content of the description of the invention, All still fall within the scope covered by the claims of the present invention. For example, software may perform the functions, manufacture, modeling, simulation, description, and/or testing of the devices and methods described herein. This can be achieved by general programming languages (eg C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, etc., or other existing programs. The software may be provided on any known computer-usable medium, such as magnetic tape, semiconductor, magnetic disk, optical disk (eg, CD-ROM, DVD-ROM, etc.), network, or other communication medium. Embodiments of the apparatus and methods described herein may be incorporated into a semiconductor intellectual property core, such as a microprocessor core (eg, implemented in a hardware description language) and translated into hardware through the fabrication of integrated circuits. Furthermore, the apparatus and methods described herein may also include a combination of hardware and software. Therefore, any embodiments described herein are not intended to limit the scope of the invention. Furthermore, the present invention can be applied to a microprocessor device of a general general-purpose computer. Finally, those skilled in the art can use the concepts and embodiments disclosed in the present invention as a basis to design and adjust different structures to achieve the same purpose, which does not go beyond the scope of the present invention.

Only the above are only preferred embodiments of the present invention, and should not limit the scope of the present invention, that is, any simple equivalent changes and modifications made according to the scope of the claims of the present invention and the content of the description of the invention, All still fall within the scope covered by the claims of the present invention. Furthermore, it is not necessary for any embodiment of the invention or the scope of the claims to achieve all of the objects or advantages or features disclosed herein. Furthermore, the abstract section and headings are provided only to aid in patent document searching and are not intended to limit the scope of the claims of the present invention.

【References of related applications】

This application is a partial continuation of the US patent application in the same application, and these cases are incorporated by reference in this case in their entirety:

case number application date 13/224,310 (CNTR.2575) 09/01/2011 13/333,520 (CNTR.2569) 12/21/2011 13/333,572 (CNTR.2572) 12/21/2011 13/333,631 (CNTR.2618) 12/21/2011

This application is cited for priority in the following U.S. provisional patent applications, each of which is incorporated herein by reference in its entirety:

case number application date 61/473,062 (CNTR.2547) 04/07/2011 61/473,067 (CNTR.2552) 04/07/2011 61/473,069 (CNTR.2556) 04/07/2011 61/537,473 (CNTR.2569) 09/21/2011 61/541,307 (CNTR.2585) 09/30/2011 61/547,449 (CNTR.2573) 10/14/2011 61/555,023 (CNTR.2564) 11/03/2011 61/604,561 (CNTR.2552) 02/29/2012

US official patent application

13/224,310 (CNTR.2575) 09/01/2011

is to cite the priority of the following U.S. provisional applications:

61/473,062 (CNTR.2547) 04/07/2011 61/473,067 (CNTR.2552) 04/07/2011 61/473,069 (CNTR.2556) 04/07/2011

The following three official U.S. applications

13/333,520 (CNTR.2569) 12/21/2011 13/333,572 (CNTR.2572) 12/21/2011 13/333,631 (CNTR.2618) 12/21/2011

They are all continuations of the following U.S. formal applications:

13/224,310 (CNTR.2575) 09/01/2011

And cite the priority of the following U.S. provisional applications:

61/473,062 (CNTR.2547) 04/07/2011 61/473,067 (CNTR.2552) 04/07/2011 61/473,069 (CNTR.2556) 04/07/2011 61/537,473 (CNTR.2569) 09/21/2011

This application is related to the following U.S. official patent applications:

13/413,258 (CNTR.2552) 03/06/2012 13/412,888 (CNTR.2580) 03/06/2012 13/412,904 (CNTR.2583) 03/06/2012 13/412,914 (CNTR.2585) 03/06/2012 13/413,346 (CNTR.2573) 03/06/2012 13/413,300 (CNTR.2564) 03/06/2012 13/413,314 (CNTR.2568) 03/06/2012

Claims (19)

1. a microprocessor having an instruction set architecture defining an instruction including an immediate field having a first portion specifying a first value and a second portion specifying a second value, the instruction directing the microprocessor to perform an operation with a fixed value as one of source operands, the fixed value being obtained by rotating/shifting the first value by a number of bits based on the second value, the microprocessor comprising:

an instruction translator for translating the instruction into at least one immediate ALU micro-instruction, wherein the immediate ALU micro-instruction is encoded in a different instruction encoding than that defined by the instruction set architecture; and

an execution pipeline that executes micro instructions generated by the instruction translator to generate results defined by the instruction set architecture;

wherein the instruction translator, but not the execution pipeline, generates the fixed value as a source operand for the immediate ALU micro-instruction based on the first and second values for execution by the execution pipeline.

2. The microprocessor of claim 1, wherein the instruction translator translates the instruction into different microinstructions based on whether a value of the immediate field falls within a predetermined subset of values.

3. The microprocessor of claim 1, wherein the execution pipeline comprises:

a plurality of execution units that execute the microinstructions to generate the result; and

an issue unit issues the fixed value generated by the instruction translator to at least one of the execution units as the source operand of the immediate ALU micro instruction executed by the at least one of the execution units.

4. The microprocessor of claim 1, wherein the execution pipeline comprises:

a plurality of execution units that execute the microinstructions to generate the result;

wherein, this microprocessor still includes:

one or more first buses for transmitting execution results of the microinstructions from the execution unit back to the execution unit as source operands of other microinstructions; and

a second bus providing the fixed value generated by the instruction translator to the execution pipeline, wherein the second bus is different from the one or more first buses.

5. The microprocessor of claim 4, further comprising:

a plurality of registers to receive results of the execution of the microinstructions from the execution unit, wherein the fixed value generated by the instruction translator is not written into the registers by the microprocessor.

6. The microprocessor of claim 1, wherein the fixed value is obtained by rotating/shifting the first value by twice the number of bits of the second value.

7. The microprocessor of claim 1, wherein the instruction set architecture of the microprocessor defines a plurality of instructions each including an immediate field, including data processing instructions of the advanced reduced instruction set machine (ARM) Instruction Set Architecture (ISA) that specify a modified immediate constant.

8. The microprocessor of claim 7, wherein the data processing instruction of the ARM instruction set architecture specifying a modified immediate constant comprises a conditional ALU instruction specifying a modified immediate constant.

9. A method for processing a microprocessor, the method performed by a microprocessor having an instruction set architecture defining an instruction, the instruction including an immediate field having a first portion specifying a first value and a second portion specifying a second value, the instruction directing the microprocessor to perform an operation on a fixed value as a source operand, the fixed value being obtained by rotating/moving the first value by a number of bits based on the second value, the method comprising:

translating the instruction into at least one immediate ALU microinstruction encoded in an instruction encoding manner different from that defined by the instruction set architecture, wherein the translating is performed by an instruction translator of the microprocessor; and

executing the microinstructions generated by the instruction translator to generate a result defined by the instruction set architecture, wherein the executing step is performed by an execution pipeline of the microprocessor;

wherein the fixed value is generated by the instruction translator, but not the execution pipeline, as a source operand to the immediate ALU micro-instruction based on the first and second values for execution by the execution pipeline.

10. The method of claim 9, wherein the translating step includes translating the instruction into different micro instructions based on whether a value of the immediate field falls within a predetermined subset of values.

11. The method of claim 9, wherein the fixed value is obtained by rotating/shifting the first value by twice the number of bits of the second value.

12. The method of claim 9, wherein the instruction set architecture of the microprocessor defines a plurality of instructions each including an immediate field, including data processing instructions of the advanced reduced instruction set machine ARM instruction set architecture ISA, the data processing instructions specifying a modified immediate constant.

13. A microprocessor having an instruction set architecture that defines an instruction that includes an immediate field having a first portion specifying a first value and a second portion specifying a second value, the instruction directing the microprocessor to perform an operation with a fixed value as one of source operands, the fixed value being obtained by rotating/shifting the first value by a number of bits based on the second value, the microprocessor comprising:

an instruction translator for translating the instruction into micro instructions; and

an execution pipeline that executes the microinstructions generated by the instruction translator to generate a result defined by the instruction set architecture;

wherein when a value of the immediate field falls within a predetermined subset of values:

the instruction translator translates the instruction into at least one immediate ALU micro-instruction;

the instruction translator, but not the execution pipeline, generating the fixed value according to the first value and the second value; and

the execution pipeline executing the immediate ALU microinstruction using the fixed value generated by the instruction translator as one of the source operands; and

wherein when the value of the immediate field does not fall within the predetermined subset of values:

the instruction translator translates the instruction into at least a first micro instruction and a second micro instruction;

the execution pipeline, other than the instruction translator, generating the fixed value by executing the first micro instruction; and

the execution pipeline executes the second micro instruction by using the fixed value generated by the execution of the first micro instruction as one of the source operands.

14. The microprocessor of claim 13, wherein the execution pipeline comprises:

a register allocation table for generating the association between the second micro instruction and the fixed value generated by the first micro instruction.

15. The microprocessor of claim 13, wherein all of the microinstructions are defined by a microarchitecture of the microprocessor and are encoded with an instruction encoding different than the instruction set architecture definition.

16. The microprocessor of claim 13, wherein the first micro instruction is a shift/rotate micro instruction.

17. A method for processing a microprocessor, the method performed by a microprocessor having an instruction set architecture defining an instruction, the instruction including an immediate field having a first portion specifying a first value and a second portion specifying a second value, the instruction directing the microprocessor to perform an operation on a fixed value as a source operand, the fixed value being obtained by rotating/shifting the first value by a number of bits based on the second value, the microprocessor including an instruction translator and an execution pipeline, the method comprising:

determining, by the instruction translator, whether a value of the immediate field falls within a predetermined subset of values;

when the value of the immediate field falls within the predetermined subset of values:

translating the instruction into at least an immediate ALU micro-instruction using the instruction translator;

generating the fixed value according to the first value and the second value using the instruction translator instead of the execution pipeline; and

executing the immediate ALU microinstruction using the fixed value generated by the instruction translator as one of the source operands using the execution pipeline; and

wherein when the value of the immediate field does not fall within the predetermined subset of values:

translating the instruction into at least a first micro instruction and a second micro instruction by using the instruction translator;

generating the fixed value by executing the first micro instruction using the execution pipeline instead of the instruction translator; and

the second micro instruction is executed using the execution pipeline by using the fixed value generated by the first micro instruction execution as one of the source operands.

18. The method of claim 17, further comprising:

generating an association between the second micro instruction and the fixed value generated by the execution of the first micro instruction, wherein the generating the association is performed by a register allocation table of the microprocessor.

19. The method of claim 17, wherein all of the microinstructions are defined by a microarchitecture of the microprocessor and are encoded with an instruction encoding different than the instruction set architecture definition.

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