CN107834829A - A kind of adaptive reflux comparator - Google Patents

Abstract

A kind of adaptive reflux comparator, belongs to electronic circuit technology field.Including biasing circuit, adaptive offset voltage generation circuit and comparator, biasing circuit provides bias voltage for adaptive offset voltage generation circuit and comparator, the input connecting valve converter of adaptive offset voltage generation circuit, according to the adaptive generation offset voltage of its input signal, again by further exporting suitable reflux control signal after comparator, so that switch converters are in the case of various outputs, inductive current is all without there is the phenomenon of reflux.It is of the invention not appear in the problem of reflux occurs for inductive current under some output voltages compared with traditional reflux comparator, the efficiency of switch converters can be effectively improved.

Description

An Adaptive Countercurrent Comparator

technical field

The invention belongs to the technical field of electronic circuits and relates to an adaptive reverse current comparator.

Background technique

In many DC-DC converter applications, in order to prevent the inductor current from flowing backward, a reverse current comparator is added to determine whether the reverse current occurs. At the same time, due to the transmission delay between the output of the reverse current comparator and the power tube, the usual practice is to introduce a fixed offset OFFSET voltage in the reverse current comparator, so that after the reverse current signal passes through the transmission delay, it can be accurately inductance Turn off the power tube when the current is equal to zero to prevent backflow. However, when the output voltage needs to work stably under various voltages, the fixed offset OFFSET voltage cannot meet the application requirements. This is because different output voltages correspond to different inductor current change rates, and each output voltage corresponds to Different offset OFFSET voltage to achieve ideal zero-crossing shutdown. If a fixed offset OFFSET voltage is used, it will cause the inductor current to reverse flow under certain output voltages, which will further lead to problems such as reduced efficiency.

Contents of the invention

What the present invention aims to solve is to propose an adaptive backflow comparator aiming at the above problems.

To achieve the above object, the present invention adopts the following technical solutions:

An adaptive reverse current comparator, comprising a bias circuit, an adaptive offset voltage generation circuit and a comparator, the input end of the bias circuit is connected to a power supply voltage, and the output end of the bias circuit outputs a first bias voltage VB and a second bias voltage VB setting voltage;

The adaptive offset voltage generation circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a Nine resistors R9, the first PMOS transistor MP1, the second PMOS transistor MP2 and the first NMOS transistor MN1,

The first resistor R1 and the eighth resistor R8 are connected in series, and the connection point thereof serves as the first input end of the adaptive offset voltage generation circuit, the other end of the first resistor R1 is connected to the source of the first PMOS transistor MP1, and the eighth resistor R8 The other end of is connected to the gate of the first NMOS transistor MN1 and grounded after passing through the ninth resistor R9;

One end of the second resistor R2 is used as the second input end of the adaptive offset voltage generating circuit, and the other end thereof is connected to the source of the second PMOS transistor MP2;

The fifth resistor R5 and the sixth resistor R6 are connected in series, the series connection point is connected to the first bias voltage VB, and the other end of the fifth resistor R5 is connected to the gate of the first PMOS transistor MP1 and the drain of the first NMOS transistor MN1, The other end of the sixth resistor R6 is connected to the gate of the second PMOS transistor MP2;

The source of the first NMOS transistor MN1 is grounded after passing through the seventh resistor R7, the drain of the first PMOS transistor MP1 is used as the first output terminal of the adaptive offset voltage generating circuit and is grounded after passing through the third resistor R3, and the second PMOS The drain of the tube MP2 is used as the second output terminal of the adaptive offset voltage generating circuit and grounded after passing through the fourth resistor R4;

The first input end of the comparator is connected to the first output end of the adaptive offset voltage generation circuit, the second input end is connected to the second output end of the adaptive offset voltage generation circuit, and the bias voltage end is connected to The output terminal of the second bias voltage is used as the output terminal of the adaptive anti-current comparator.

Specifically, the gate voltage VOUT_drop of the first NMOS transistor MN1 is adjusted by changing the ratio between the eighth resistor R8 and the ninth resistor R9.

Specifically, the first bias voltage VB satisfies the following formula:

VB＞2×(VOUT_drop_max-Vt)+Io×R5

Wherein, VOUT_drop_max is the maximum value of the gate voltage VOUT_drop of the first NMOS transistor MN1, Vt is the threshold voltage of the first NMOS transistor MN1, and Io is the current flowing through the seventh resistor R7.

The beneficial effects of the present invention are: the offset OFFSET voltage required by the reverse current comparator can be adaptively generated effectively according to the change of the output voltage of the DC-DC converter, so that the DC-DC converter has ideal reverse current limiting performance; Compared with the traditional anti-current comparator, the self-adaptive anti-current comparator provided by the invention does not have the problem of inductive current anti-current under certain output voltages, and can effectively improve the efficiency of the DC-DC converter.

Description of drawings

FIG. 1 is a structural block diagram of an adaptive reverse current comparator provided by the present invention.

FIG. 2 is a schematic diagram of the relationship between the offset voltage OFFSET of the adaptive offset voltage generating circuit and the voltage VOUT of the first input terminal.

FIG. 3 is a structural diagram of an adaptive offset voltage generation circuit in the present invention.

FIG. 4 is a waveform diagram of an adaptive offset voltage generation circuit in the present invention.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

An adaptive anti-current comparator proposed by the present invention is suitable for DC-DC switching converters. For different switching converters, the input terminal of the adaptive anti-current comparator is connected to the conduction circuit when the inductor current drops in the switching converter. The two ends of the power tube, taking the BOOST converter as an example, as shown in Figure 1, is a structural block diagram of an adaptive reverse current comparator applied to the BOOST converter as shown in Figure 1, and the output voltage VOUT of the BOOST converter is connected to the self-adaptive The first input terminal of the reverse current comparator, the common drain terminal of the upper power transistor MP and the lower power transistor MN in the BOOST converter (that is, the switching node SW of the BOOST converter) is connected to the second input terminal of the adaptive reverse current comparator. The adaptive offset voltage generating circuit will adaptively generate the offset OFFSET voltage according to the input signal. In this embodiment, the offset OFFSET voltage is defined as the first input voltage VOUT and the second output voltage SW_COMP when the first output voltage VOUT_COMP is equal to the second output voltage SW_COMP. The difference between the second input voltage SW. The bias circuit provides a bias voltage for the adaptive offset voltage generation circuit and the comparator, its input end is connected to the power supply voltage, and its output end outputs the first bias voltage VB to the adaptive offset voltage generation circuit and the second bias voltage to the comparator device. The first input end of the comparator is connected to the first output end of the adaptive offset voltage generating circuit, the second input end is connected to the second output end of the adaptive offset voltage generating circuit, and the output end is used as the output of the adaptive anti-current comparator The terminal outputs an adaptive anti-flow control signal. After the above steps, in the BOOST converter circuit, after the voltages of the SW point and the VOUT point are input to the adaptive reverse current comparator, the adaptive reverse current comparator can adaptively adjust the offset OFFSET voltage according to the input information, and further output The proper reverse flow judgment signal makes the inductor current not reverse flow phenomenon under various output conditions of the BOOST converter.

As shown in Figure 2, it is an explanatory diagram of the relationship between the offset OFFSET voltage and the first input voltage VOUT in this embodiment. In the BOOST converter circuit, when the current power tube is turned off, the circuit enters the dead time, and the SW point first rises to VOUT+0.7 V, where 0.7V is the conduction voltage drop of the general body diode, the specific value can be determined according to the actual body diode conduction voltage drop; the small platform in Figure 2 is caused by the conduction of the upper power transistor body diode during the dead time. Then the upper power tube is turned on, the inductor current drops gradually, and the voltage at the SW point drops accordingly. When the voltage at the SW point is equal to the VOUT voltage, the inductor current drops to zero. Since the reverse current signal needs to pass a certain delay D_delay before it can be transmitted to the power tube, the reverse current comparator needs to set a certain offset OFFSET voltage to make the reverse current control signal turn off the power tube in advance of the D_delay time, so that the BOOST converter does not appear inductance The phenomenon of current reverse flow. As shown in Figure 2, when the VOUT voltage is different, the slope K of the voltage drop at the corresponding SW point is also different, where K is proportional to (VOUT-VIN)×Ron/L, VIN is the input voltage of the BOOST circuit, and Ron is the power The on-resistance of the tube, L is the inductance in the BOOST topology. Therefore, due to the difference in the K value, the OFFSET voltage should also change adaptively when the VOUT voltage changes. And the change should be proportional to VOUT-VIN.

Figure 3 is a schematic structural diagram of the adaptive offset voltage generating circuit of the present invention, including a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, The seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the first PMOS transistor MP1, the second PMOS transistor MP2 and the first NMOS transistor MN1, the first resistor R1 and the eighth resistor R8 are connected in series, and the series connection point is used as the The first input end of the adaptive offset voltage generating circuit is connected to the output voltage VOUT of the BOOST converter, the other end of the first resistor R1 is connected to the source of the first PMOS transistor MP1, and the other end of the eighth resistor R8 is connected to the first NMOS transistor MN1 The gate of the second resistor R2 is grounded after passing through the ninth resistor R9; one end of the second resistor R2 is used as the second input end of the adaptive offset voltage generating circuit to connect to the switching node SW of the BOOST converter, and the other end is connected to the second PMOS transistor MP2 The source of the fifth resistor R5 and the sixth resistor R6 are connected in series, the series point is connected to the first bias voltage VB, and the other end of the fifth resistor R5 is connected to the gate of the first PMOS transistor MP1 and the first NMOS transistor MN1 The drain of the sixth resistor R6 is connected to the gate of the second PMOS transistor MP2; the source of the first NMOS transistor MN1 is grounded after passing through the seventh resistor R7, and the drain of the first PMOS transistor MP1 serves as the adaptive The first output terminal of the offset voltage generating circuit outputs the first output voltage VOUT_COMP and is grounded after passing through the third resistor R3, and the drain of the second PMOS transistor MP2 is used as the second output terminal of the adaptive offset voltage generating circuit to output the second output The voltage SW_COMP is grounded after passing through the fourth resistor R4.

The adaptive offset voltage generation module adaptively generates the corresponding offset OFFSET voltage according to the change of the VOUT signal at the first input terminal and the SW signal at the second input terminal, and superimposes it on the voltage VOUT_COMP output from the first output terminal. The adaptive offset voltage The output signal of the generation module is used as the input signal of the comparator module; when VOUT_COMP<SW_COMP, the comparator outputs the reverse flow control signal.

The voltage VOUT_drop at the gate of the first NMOS transistor MN1, the voltage VOUT of the first input terminal of the adaptive offset voltage generation module, and the first bias voltage VB have the following relationship, wherein the voltage VOUT_drop is the voltage VOUT after stepping down by a certain ratio Voltage, the voltage value of VOUT_drop will change with the change of VOUT according to this ratio, and the ratio can be adjusted through the eighth resistor R8 and the ninth resistor R9; the first bias voltage VB should satisfy formula (1) to ensure the first The NMOS tube MN1 works in the saturation region.

VB＞2×(VOUT_drop_max-Vt)+Io×R5 (1)

Wherein, VOUT_drop_max is the maximum value of VOUT_drop, Vt is the threshold voltage of the first NOMS transistor MN1, and Io is the current flowing through the seventh resistor R7. The minimum value of VOUT_drop VOUT_drop_min>Io×R7+Vt.

FIG. 4 is a waveform diagram of an adaptive offset voltage generating circuit. The first NMOS transistor MN1 and the seventh resistor R7 in this circuit generate an adaptive current Io, and the product of the adaptive current Io and the fifth resistor R5 is an adaptive offset OFFSET voltage. The first NMOS transistor MN1 and the seventh resistor R7 have a structure with a negative feedback resistor on the source, and the input voltage VOUT_drop is the voltage after VOUT is stepped down or boosted by a certain ratio, and the threshold voltage of the first NMOS transistor MN1 is subtracted from VOUT_drop The relationship between Vt and the adaptive current Io is approximately linear, so VOUT_drop minus the threshold voltage of the first NMOS transistor MN1 also has an approximately linear relationship with the offset OFFSET voltage, as shown in Figure 4 in stage ①. When VOUT_drop increases with the increase of VOUT, since the first bias voltage VB is a fixed value, when VOUT_drop>VB/2+Vt-(Io×R5)/2, the first NMOS transistor MN1 will enter the linear region , the above-mentioned waveform is non-linear, and the final offset OFFSET voltage tends to VB, as shown in Figure 4 in stage ②.

Those skilled in the art can make various other specific modifications and combinations based on the technical revelations disclosed in the present invention without departing from the essence of the present invention, and these modifications and combinations are still within the protection scope of the present invention.

Claims (3)

1. a kind of adaptive reflux comparator, it is characterised in that including biasing circuit, adaptive offset voltage generation circuit and ratio Compared with device, the input connection supply voltage of the biasing circuit, its output end exports the first bias voltage (VB) and the second biasing Voltage；

The adaptive offset voltage generation circuit includes first resistor (R1), second resistance (R2), 3rd resistor (R3), the 4th Resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9), One PMOS (MP1), the second PMOS (MP2) and the first NMOS tube (MN1),

First resistor (R1) and the series connection of the 8th resistance (R8), its series connection point as the adaptive offset voltage generation circuit the One input, the other end of first resistor (R1) connect the source electrode of the first PMOS (MP1), and the other end of the 8th resistance (R8) connects Connect the grid of the first NMOS tube (MN1) and be grounded afterwards by the 9th resistance (R9)；

Second input of the one end of second resistance (R2) as the adaptive offset voltage generation circuit, the connection of its other end The source electrode of second PMOS (MP2)；

5th resistance (R5) and the series connection of the 6th resistance (R6), its series connection point connect first bias voltage (VB), the 5th resistance (R5) the other end connects the grid of the first PMOS (MP1) and the drain electrode of the first NMOS tube (MN1), the 6th resistance (R6) it is another One end connects the grid of the second PMOS (MP2)；

The source electrode of first NMOS tube (MN1) is grounded afterwards by the 7th resistance (R7), described in the drain electrode conduct of the first PMOS (MP1) First output end of adaptive offset voltage generation circuit is simultaneously grounded afterwards by 3rd resistor (R3), the second PMOS (MP2) Drain as adaptively second output end of offset voltage generation circuit and be grounded afterwards by the 4th resistance (R4)；

First output end of the first input end connection adaptive offset voltage generation circuit of the comparator, it is second defeated Enter the second output end of the end connection adaptive offset voltage generation circuit, the second biased electrical described in its biased electrical press bond Pressure, output end of its output end as the adaptive reflux comparator.

2. adaptive reflux comparator according to claim 1, it is characterised in that by changing the 8th resistance (R8) and the The ratio of nine resistance (R9) adjusts the first NMOS tube (MN1) grid voltage (VOUT_drop).

3. adaptive reflux comparator according to claim 2, it is characterised in that first bias voltage (VB) meets Following formula：

VB ＞ 2 × (VOUT_drop_max-Vt)+Io × R5

Wherein, VOUT_drop_max be the first NMOS tube (MN1) grid voltage (VOUT_drop) maximum, Vt first The threshold voltage of NMOS tube (MN1), Io are the electric current for flowing through the 7th resistance (R7).