CN107819052A - A kind of efficiently crystal silicon non crystal heterogeneous agglomeration battery structure and preparation method thereof - Google Patents
A kind of efficiently crystal silicon non crystal heterogeneous agglomeration battery structure and preparation method thereof Download PDFInfo
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 30
- 239000010703 silicon Substances 0.000 title claims abstract description 30
- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 239000013078 crystal Substances 0.000 title claims 17
- 238000005054 agglomeration Methods 0.000 title claims 8
- 230000002776 aggregation Effects 0.000 title claims 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 129
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 7
- 238000007650 screen-printing Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 239000004332 silver Substances 0.000 claims description 5
- 238000005245 sintering Methods 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 229910000077 silane Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 4
- 230000008021 deposition Effects 0.000 claims 4
- 238000004140 cleaning Methods 0.000 claims 1
- 235000008216 herbs Nutrition 0.000 claims 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- HJELPJZFDFLHEY-UHFFFAOYSA-N silicide(1-) Chemical compound [Si-] HJELPJZFDFLHEY-UHFFFAOYSA-N 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 210000002268 wool Anatomy 0.000 claims 1
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract description 11
- 230000003287 optical effect Effects 0.000 abstract description 3
- 239000010408 film Substances 0.000 description 13
- 238000007740 vapor deposition Methods 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000004050 hot filament vapor deposition Methods 0.000 description 4
- 238000001755 magnetron sputter deposition Methods 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
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- H10F10/161—Photovoltaic cells having only PN heterojunction potential barriers comprising multiple PN heterojunctions, e.g. tandem cells
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- H10F71/121—The active layers comprising only Group IV materials
- H10F71/1221—The active layers comprising only Group IV materials comprising polycrystalline silicon
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Abstract
本发明公开了一种晶硅/非晶硅异质结电池结构及其制备方法。它包括硅衬底层以及硅衬底层上层的上本征非晶硅层和硅衬底层下层的下本征非晶硅层，上本征非晶硅层的上层由下往上依次设置有受光面第一掺杂非晶硅层、受光面第二掺杂非晶硅层和上TOC层，下本征非晶硅层的下层由上往下依次设置有第三掺杂非晶硅层和下TOC层。采用上述的结构和方法后，由于设置的两层受光面掺杂非晶硅层并且通过在制备过程中通过调整工艺参数实现受光面双掺杂非晶硅层，使其膜层同时具有优异的光学性能和电学性能，由此在不影响HJT电池受光面掺杂非晶硅导电性的情况下，提高了该掺杂非晶硅层的带隙，提高了光的利用率，从而了提高HJT电池的光电转换效率。
The invention discloses a crystalline silicon/amorphous silicon heterojunction cell structure and a preparation method thereof. It includes a silicon substrate layer, an upper intrinsic amorphous silicon layer on the upper layer of the silicon substrate layer, and a lower intrinsic amorphous silicon layer on the lower layer of the silicon substrate layer. The upper layer of the upper intrinsic amorphous silicon layer is sequentially provided with a light-receiving surface from bottom to top. The first doped amorphous silicon layer, the second doped amorphous silicon layer and the upper TOC layer on the light-receiving surface, and the lower layer of the lower intrinsic amorphous silicon layer are provided with the third doped amorphous silicon layer and the lower layer from top to bottom. TOC layer. After adopting the above-mentioned structure and method, since the two light-receiving surfaces are doped with amorphous silicon layers and the double-doped amorphous silicon layers on the light-receiving surfaces are realized by adjusting the process parameters during the preparation process, the film layer has excellent properties at the same time. Optical properties and electrical properties, thus without affecting the conductivity of the doped amorphous silicon layer on the light-receiving surface of the HJT cell, the band gap of the doped amorphous silicon layer is improved, and the utilization rate of light is improved, thereby improving the HJT The photoelectric conversion efficiency of the battery.
Description
技术领域technical field
本发明涉及一种晶硅/非晶硅异质结电池结构及其制备方法，属于太阳能电池制造技术领域。The invention relates to a crystalline silicon/amorphous silicon heterojunction cell structure and a preparation method thereof, belonging to the technical field of solar cell manufacturing.
背景技术Background technique
随着太阳能电池技术的发展，高效电池的开发越来越受重视，其中用非晶硅本征层（a-Si:H(i)）钝化的硅基异质结太阳电池（HJT电池）是重点的研究方向之一；众所周知，硅基异质结太阳电池不仅有高的转化效率、高的开路电压，而且具有低的温度系数、无光致衰减（LID）、无电致衰减（PID）、低的制备工艺温度等优势，另外硅基异质结电池在保证高转化效率的同时，硅片厚度可减薄至100μm，有效减少了硅料耗量，并可用来制备可弯曲电池组件。With the development of solar cell technology, more and more attention has been paid to the development of high-efficiency cells, among which silicon-based heterojunction solar cells (HJT cells) passivated with amorphous silicon intrinsic layer (a-Si:H(i)) It is one of the key research directions; as we all know, silicon-based heterojunction solar cells not only have high conversion efficiency, high open circuit voltage, but also have low temperature coefficient, no light-induced degradation (LID), no electrical degradation (PID) ), low manufacturing process temperature and other advantages. In addition, silicon-based heterojunction cells can ensure high conversion efficiency while the thickness of silicon wafers can be reduced to 100 μm, which effectively reduces the consumption of silicon materials and can be used to prepare bendable battery components. .
然而，对于HJT电池而言，非晶硅起到钝化、形成p-n结的关键作用，对于HJT电池的转换效率起到决定性作用，因此，制备性能优异的非晶硅薄膜是获得高效HJT电池的关键技术，现有技术中，由于HJT电池中非晶硅主要有本征非晶硅和掺杂非晶硅，受光面掺杂非晶硅层由于要保证良好的导电性，通常含氢量较少，带隙较小，因而光的透过率较低，影响光的利用率。However, for HJT cells, amorphous silicon plays a key role in passivation and the formation of p-n junctions, and plays a decisive role in the conversion efficiency of HJT cells. Therefore, the preparation of amorphous silicon thin films with excellent performance is the key to obtaining high-efficiency HJT cells. Key technology, in the prior art, since the amorphous silicon in the HJT battery mainly includes intrinsic amorphous silicon and doped amorphous silicon, the doped amorphous silicon layer on the light-receiving surface usually has a relatively high hydrogen content to ensure good conductivity. Less, the band gap is smaller, so the light transmittance is lower, which affects the utilization of light.
发明内容Contents of the invention
本发明要解决的技术问题是提供一种在不影响导电性的情况下，提高光的利用率，从而提高光电转换效率的晶硅/非晶硅异质结电池结构及其制备方法。The technical problem to be solved by the present invention is to provide a crystalline silicon/amorphous silicon heterojunction cell structure and a preparation method thereof, which can improve the utilization rate of light without affecting the conductivity, thereby improving the photoelectric conversion efficiency.
为了解决上述技术问题，本发明的晶硅/非晶硅异质结电池结构，包括硅衬底层以及硅衬底层上层的上本征非晶硅层和硅衬底层下层的下本征非晶硅层，上本征非晶硅层的上层由下往上依次设置有受光面第一掺杂非晶硅层、受光面第二掺杂非晶硅层和上TOC层，下本征非晶硅层的下层由上往下依次设置有第三掺杂非晶硅层和下TOC层。In order to solve the above-mentioned technical problems, the crystalline silicon/amorphous silicon heterojunction battery structure of the present invention includes a silicon substrate layer and an upper intrinsic amorphous silicon layer on the upper layer of the silicon substrate layer and a lower intrinsic amorphous silicon layer on the lower layer of the silicon substrate layer layer, the upper layer of the upper intrinsic amorphous silicon layer is sequentially provided with the first doped amorphous silicon layer on the light receiving surface, the second doped amorphous silicon layer on the light receiving surface and the upper TOC layer, and the lower intrinsic amorphous silicon layer The lower layer of the layer is sequentially provided with a third doped amorphous silicon layer and a lower TOC layer from top to bottom.
所述受光面第一掺杂非晶硅层和受光面第二掺杂非晶硅层的厚度均为2-10 nm。The thicknesses of the first doped amorphous silicon layer on the light receiving surface and the second doped amorphous silicon layer on the light receiving surface are both 2-10 nm.
所述受光面第一掺杂非晶硅层的禁带宽度为1.7-1.9 eV，所述受光面第二掺杂非晶硅层的禁带宽度为1.5-1.7 eV。The forbidden band width of the first doped amorphous silicon layer on the light receiving surface is 1.7-1.9 eV, and the forbidden band width of the second doped amorphous silicon layer on the light receiving surface is 1.5-1.7 eV.
所述上本征非晶硅层和下本征非晶硅层的厚度均为5-15 nm，所述第三掺杂非晶硅层的厚度为5-20 nm，所述上TOC层和下TOC层的厚度均为70-120 nm。Both the thickness of the upper intrinsic amorphous silicon layer and the lower intrinsic amorphous silicon layer are 5-15 nm, the thickness of the third doped amorphous silicon layer is 5-20 nm, and the upper TOC layer and The thickness of the lower TOC layer is 70-120 nm.
一种如上述的晶硅/非晶硅异质结电池制备方法，包括以下步骤：A method for preparing a crystalline silicon/amorphous silicon heterojunction cell as described above, comprising the following steps:
A、对N型单晶硅片进行制绒处理，形成金字塔绒面，去除杂质离子及进行表面清洁；A. Perform texturing treatment on N-type monocrystalline silicon wafers to form a pyramid textured surface, remove impurity ions and clean the surface;
B、通过气相沉积制备正背面的上本征非晶硅层和下本征非晶硅层，上本征非晶硅层和下本征非晶硅层的厚度为5-15nm；B. Prepare the upper intrinsic amorphous silicon layer and the lower intrinsic amorphous silicon layer on the front and back sides by vapor deposition, the thickness of the upper intrinsic amorphous silicon layer and the lower intrinsic amorphous silicon layer is 5-15nm;
C、在下本征非晶硅层表面使用气相沉积制备n型非晶硅层，即第三掺杂非晶硅层，其厚度为5-20nm；C, using vapor deposition on the surface of the lower intrinsic amorphous silicon layer to prepare an n-type amorphous silicon layer, that is, the third doped amorphous silicon layer, the thickness of which is 5-20nm;
D、在上本征非晶硅层表面使用气相沉积制备两层p型掺杂非晶硅层，作为受光面，即受光面第一p型掺杂非晶硅层、受光面第二p型掺杂非晶硅层，其厚度均为2-10 nm，厚度优选为5 nm，另外，受光面第一掺杂非晶硅层的禁带宽度为1.7-1.9 eV，优选为1.8 eV，受光面第二掺杂非晶硅层的禁带宽度为1.5-1.7 eV，优选为1.6 eV；D. Prepare two layers of p-type doped amorphous silicon layer by vapor deposition on the surface of the upper intrinsic amorphous silicon layer as the light-receiving surface, that is, the first p-type doped amorphous silicon layer on the light-receiving surface, and the second p-type doped amorphous silicon layer on the light-receiving surface The doped amorphous silicon layer has a thickness of 2-10 nm, and the thickness is preferably 5 nm. In addition, the band gap of the first doped amorphous silicon layer on the light-receiving surface is 1.7-1.9 eV, preferably 1.8 eV. The band gap of the second doped amorphous silicon layer is 1.5-1.7 eV, preferably 1.6 eV;
E、使用磁控溅射方法沉积上TCO导电膜（TOC层）和下TCO导电膜，厚度为70-120nm；E. Use the magnetron sputtering method to deposit the upper TCO conductive film (TOC layer) and the lower TCO conductive film, with a thickness of 70-120nm;
F、通过丝网印刷形成正背面银金属电极，主栅宽度为0.1-2mm，主栅数目为2-20，正背面银副栅线宽度为20-70μm，线数为80-250；F. Form the front and back silver metal electrodes by screen printing, the width of the main grid is 0.1-2mm, the number of main grids is 2-20, the width of the front and back silver auxiliary grids is 20-70μm, and the number of lines is 80-250;
G、烧结使金属与硅之间形成良好的欧姆接触；G. Sintering makes good ohmic contact between metal and silicon;
H、进行测试电池的电性能。H, to test the electrical performance of the battery.
上述的晶硅/非晶硅异质结电池结构及其制备方法，使用等离子体增强化学气相沉积（PECVD）或热丝化学气相沉积（HWCVD）制备两层所述受光面掺杂非晶硅膜。The above crystalline silicon/amorphous silicon heterojunction cell structure and its preparation method, using plasma enhanced chemical vapor deposition (PECVD) or hot wire chemical vapor deposition (HWCVD) to prepare two layers of the light-receiving surface doped amorphous silicon film .
上述的晶硅/非晶硅异质结电池结构及其制备方法，双层受光面非晶硅膜在一次工艺过程中完成，使用硅烷、氢气、掺杂气体（含有硼或磷元素的气体）反应生成。The above-mentioned crystalline silicon/amorphous silicon heterojunction cell structure and its preparation method, the double-layer light-receiving surface amorphous silicon film is completed in one process, using silane, hydrogen, and doping gas (gas containing boron or phosphorus elements) The reaction is generated.
采用上述的结构和方法后，由于设置的两层受光面掺杂非晶硅层并且通过在制备过程中通过调整工艺参数实现受光面双掺杂非晶硅层，使其膜层同时具有优异的光学性能和电学性能，由此在不影响HJT电池受光面掺杂非晶硅导电性的情况下，提高了该掺杂非晶硅层的带隙，提高了光的利用率，从而了提高HJT电池的光电转换效率。After adopting the above-mentioned structure and method, since the two light-receiving surfaces are doped with amorphous silicon layers and the double-doped amorphous silicon layers on the light-receiving surfaces are realized by adjusting the process parameters during the preparation process, the film layer has excellent properties at the same time. Optical properties and electrical properties, thus without affecting the conductivity of the doped amorphous silicon layer on the light-receiving surface of the HJT cell, the band gap of the doped amorphous silicon layer is improved, and the utilization rate of light is improved, thereby improving the HJT The photoelectric conversion efficiency of the battery.
附图说明Description of drawings
图1为本发明晶硅/非晶硅异质结电池结构的结构示意图。FIG. 1 is a schematic structural view of the crystalline silicon/amorphous silicon heterojunction cell structure of the present invention.
具体实施方式Detailed ways
下面结合附图和具体实施方式，对发明晶硅/非晶硅异质结电池结构及其制备方法作进一步详细说明。The inventive crystalline silicon/amorphous silicon heterojunction battery structure and its preparation method will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
如图所示，本发明的晶硅/非晶硅异质结电池结构，包括硅衬底层1以及硅衬底层上层的上本征非晶硅层2和硅衬底层下层的下本征非晶硅层3，上本征非晶硅层2的上层由下往上依次设置有受光面第一掺杂非晶硅层4、受光面第二掺杂非晶硅层5和上TOC层6，受光面第一掺杂非晶硅层4和受光面第二掺杂非晶硅层5的厚度均为2-10 nm，受光面第一掺杂非晶硅层4的禁带宽度为1.7-1.9 eV，受光面第二掺杂非晶硅层5的禁带宽度为1.5-1.7eV，下本征非晶硅层3的下层由上往下依次设置有第三掺杂非晶硅层7和下TOC层8，上本征非晶硅层2和下本征非晶硅层3的厚度均为5-15 nm，第三掺杂非晶硅层7的厚度为5-20 nm，上TOC层6和下TOC层8的厚度均为70-120 nm，另外，上TOC层和下TOC层的表面还分别具有通过丝网印刷形成正背面银金属电极。As shown in the figure, the crystalline silicon/amorphous silicon heterojunction battery structure of the present invention includes a silicon substrate layer 1, an upper intrinsic amorphous silicon layer 2 on the upper layer of the silicon substrate layer, and a lower intrinsic amorphous silicon layer on the lower layer of the silicon substrate layer. Silicon layer 3, the upper layer of the upper intrinsic amorphous silicon layer 2 is sequentially provided with the first doped amorphous silicon layer 4 on the light receiving surface, the second doped amorphous silicon layer 5 on the light receiving surface and the upper TOC layer 6, The thicknesses of the first doped amorphous silicon layer 4 on the light receiving surface and the second doped amorphous silicon layer 5 on the light receiving surface are both 2-10 nm, and the band gap of the first doped amorphous silicon layer 4 on the light receiving surface is 1.7- 1.9 eV, the band gap of the second doped amorphous silicon layer 5 on the light-receiving surface is 1.5-1.7 eV, and the lower layer of the lower intrinsic amorphous silicon layer 3 is sequentially provided with a third doped amorphous silicon layer 7 from top to bottom and the lower TOC layer 8, the thickness of the upper intrinsic amorphous silicon layer 2 and the lower intrinsic amorphous silicon layer 3 is 5-15 nm, the thickness of the third doped amorphous silicon layer 7 is 5-20 nm, the upper Both the TOC layer 6 and the lower TOC layer 8 have a thickness of 70-120 nm. In addition, the surfaces of the upper TOC layer and the lower TOC layer also have front and back silver metal electrodes formed by screen printing.
一种上述晶硅/非晶硅异质结电池制备方法，包括以下步骤：A method for preparing the aforementioned crystalline silicon/amorphous silicon heterojunction cell, comprising the following steps:
A、对N型单晶硅片进行制绒处理，形成金字塔绒面，去除杂质离子及进行表面清洁；A. Perform texturing treatment on N-type monocrystalline silicon wafers to form a pyramid textured surface, remove impurity ions and clean the surface;
B、通过气相沉积制备正背面的上本征非晶硅层和下本征非晶硅层，上本征非晶硅层和下本征非晶硅层的厚度为5-15nm；B. Prepare the upper intrinsic amorphous silicon layer and the lower intrinsic amorphous silicon layer on the front and back sides by vapor deposition, the thickness of the upper intrinsic amorphous silicon layer and the lower intrinsic amorphous silicon layer is 5-15nm;
C、在下本征非晶硅层表面使用气相沉积制备n型非晶硅层，即第三掺杂非晶硅层，其厚度为5-20nm；C, using vapor deposition on the surface of the lower intrinsic amorphous silicon layer to prepare an n-type amorphous silicon layer, that is, the third doped amorphous silicon layer, the thickness of which is 5-20nm;
D、在上本征非晶硅层表面使用气相沉积制备两层p型掺杂非晶硅层，作为受光面，即第一掺杂非晶硅层4、第二掺杂非晶硅层5，其厚度均为2-10 nm；D. Prepare two layers of p-type doped amorphous silicon layers by vapor deposition on the surface of the upper intrinsic amorphous silicon layer, as the light-receiving surface, that is, the first doped amorphous silicon layer 4 and the second doped amorphous silicon layer 5 , the thickness of which is 2-10 nm;
E、使用磁控溅射方法沉积上下TCO导电膜，厚度为70-120nm；E. Use the magnetron sputtering method to deposit the upper and lower TCO conductive films with a thickness of 70-120nm;
F、通过丝网印刷形成正背面银金属电极，主栅宽度为0.1-2mm，主栅数目为2-20，正背面银副栅线宽度为20-70μm，线数为80-250；F. Form the front and back silver metal electrodes by screen printing, the width of the main grid is 0.1-2mm, the number of main grids is 2-20, the width of the front and back silver auxiliary grids is 20-70μm, and the number of lines is 80-250;
G、烧结使金属与硅之间形成良好的欧姆接触；G. Sintering makes good ohmic contact between metal and silicon;
H、进行测试电池的电性能。H, to test the electrical performance of the battery.
另外，需要说明的是受光面掺杂非晶硅在制备过程中是使用等离子体增强化学气相沉积（PECVD）或热丝化学气相沉积（HWCVD）制备受光面掺杂非晶硅膜，双层受光面非晶硅膜可在一次工艺过程中完成，使用硅烷、氢气、掺杂气体（含有硼或磷元素的气体）反应生成。In addition, it should be noted that the doped amorphous silicon film on the light-receiving surface is prepared by plasma-enhanced chemical vapor deposition (PECVD) or hot-wire chemical vapor deposition (HWCVD) during the preparation process. The surface amorphous silicon film can be completed in one process, using silane, hydrogen, and doping gas (gas containing boron or phosphorus) to react.
下面结合具体对比例对本发明的实际效果作如下对比说明：Below in conjunction with specific comparative examples, the actual effect of the present invention is compared and explained as follows:
对比例：Comparative example:
A、对N型厚度为180μm的单晶硅片进行制绒处理，形成金字塔绒面，去除杂质离子及进行表面清洁；A. Perform texturing treatment on N-type monocrystalline silicon wafers with a thickness of 180 μm to form a pyramid textured surface, remove impurity ions and clean the surface;
B、通过等离子体化学气相沉积制备正背面的双本征非晶硅层，正背面本征非晶硅厚度为10nm；B. Prepare the double intrinsic amorphous silicon layer on the front and back by plasma chemical vapor deposition, and the thickness of the intrinsic amorphous silicon on the front and back is 10nm;
C、选取P型非晶硅膜为受光面掺杂层，使用等离子体增强化学气相沉积制备n型非晶硅层，厚度为10 nm；C. Select the p-type amorphous silicon film as the doped layer on the light-receiving surface, and use plasma-enhanced chemical vapor deposition to prepare an n-type amorphous silicon layer with a thickness of 10 nm;
D、使用等离子体化学气相沉积制备p型非晶硅层，禁带宽度为1.7 eV，厚度10 nm；D, using plasma chemical vapor deposition to prepare a p-type amorphous silicon layer with a band gap of 1.7 eV and a thickness of 10 nm;
E、使用磁控溅射方法沉积TCO导电膜，厚度80nm；E, use magnetron sputtering method to deposit TCO conductive film, thickness 80nm;
F、通过丝网印刷形成正背面银金属电极，主栅宽度为1mm，主栅数目为4，正背面银副栅线宽度为60μm，线数为100；F. Form the front and back silver metal electrodes by screen printing, the width of the main grid is 1mm, the number of main grids is 4, the width of the front and back silver auxiliary grids is 60 μm, and the number of lines is 100;
G、烧结使金属与硅之间形成良好的欧姆接触。G. Sintering makes good ohmic contact between metal and silicon.
H、进行测试电池的电性能。H, to test the electrical performance of the battery.
实施例：Example:
A、对N型厚度为180μm的单晶硅片进行制绒处理，形成金字塔绒面，去除杂质离子及进行表面清洁；A. Perform texturing treatment on N-type monocrystalline silicon wafers with a thickness of 180 μm to form a pyramid textured surface, remove impurity ions and clean the surface;
B、通过等离子体化学气相沉积制备正背面的双本征非晶硅层，正背面本征非晶硅厚度为10nm；B. Prepare the double intrinsic amorphous silicon layer on the front and back by plasma chemical vapor deposition, and the thickness of the intrinsic amorphous silicon on the front and back is 10nm;
C、选取p型非晶硅膜为受光面掺杂层。使用等离子体增强化学气相沉积制备n型非晶硅层，厚度为10nm；C. Select the p-type amorphous silicon film as the doped layer on the light-receiving surface. Using plasma-enhanced chemical vapor deposition to prepare an n-type amorphous silicon layer with a thickness of 10 nm;
D、使用等离子体化学气相沉积制备p型非晶硅层，
E、使用磁控溅射方法沉积TCO导电膜，厚度80nm；E, use magnetron sputtering method to deposit TCO conductive film, thickness 80nm;
F、通过丝网印刷形成正背面银金属电极，主栅宽度为1mm，主栅数目为4，正背面银副栅线宽度为60μm，线数为100；F. Form the front and back silver metal electrodes by screen printing, the width of the main grid is 1mm, the number of main grids is 4, the width of the front and back silver auxiliary grids is 60 μm, and the number of lines is 100;
G、烧结使金属与硅之间形成良好的欧姆接触。G. Sintering makes good ohmic contact between metal and silicon.
H、进行测试电池的电性能。H, to test the electrical performance of the battery.
按照上述方法制备出HJT电池的电性能见下表，可以看出效率提高在0.15%（abs），主要表现在电流和填充性能上的提升，电流的提升主要得益于受光面第一掺杂层较大禁带宽度带来的高透过率，以及与本征非晶硅层的带隙匹配；填充的提升主要得益于受光面第二掺杂层的低禁带宽度带来的高电导率。因此采用通过调整工艺参数实现受光面双掺杂非晶硅层，使其膜层同时具有优异的光学性能和电学性能的方案是可行的，具体对比试验数据如下：The electrical performance of the HJT battery prepared according to the above method is shown in the table below. It can be seen that the efficiency is increased by 0.15% (abs), which is mainly reflected in the improvement of current and filling performance. The improvement of current is mainly due to the first doping of the light-receiving surface. The high transmittance brought by the large bandgap of the layer, and the bandgap matching with the intrinsic amorphous silicon layer; the improvement of filling is mainly due to the high transmittance brought by the low bandgap of the second doped layer on the light receiving surface. conductivity. Therefore, it is feasible to realize the double-doped amorphous silicon layer on the light-receiving surface by adjusting the process parameters, so that the film layer has excellent optical and electrical properties at the same time. The specific comparative test data are as follows:
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108538966A (en) * | 2018-04-18 | 2018-09-14 | 晋能光伏技术有限责任公司 | A kind of deficient manufacturing procedure rework preocess method after efficient heterojunction battery CVD |
| CN109411551A (en) * | 2018-12-13 | 2019-03-01 | 江苏爱康能源研究院有限公司 | Efficient silicon/crystalline silicon heterojunction solar battery electrode structure of multiple deposition and preparation method thereof |
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| CN109950132A (en) * | 2019-03-01 | 2019-06-28 | 晋能光伏技术有限责任公司 | A method for double-sided deposition of solar cell amorphous silicon layer in tubular PECVD equipment |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012043124A1 (en) * | 2010-10-01 | 2012-04-05 | 株式会社カネカ | Method for manufacturing photoelectric conversion device |
| CN204315606U (en) * | 2015-01-21 | 2015-05-06 | 中电投西安太阳能电力有限公司 | Double heterojunction double-sided solar battery |
| US20160284915A1 (en) * | 2013-11-12 | 2016-09-29 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Photovoltaic cell with silicon heterojunction |
| CN106024917A (en) * | 2016-05-31 | 2016-10-12 | 英利能源（中国）有限公司 | A kind of solar cell sheet and solar cell assembly |
| WO2016182128A1 (en) * | 2015-05-12 | 2016-11-17 | 주식회사 테스 | Method for manufacturing solar cell module |
| CN205920977U (en) * | 2016-06-29 | 2017-02-01 | 新奥光伏能源有限公司 | Silicon heterojunction solar cell and photovoltaic module with novel projecting pole |
| CN106449850A (en) * | 2015-08-05 | 2017-02-22 | 钧石(中国)能源有限公司 | High efficiency silicon-based heterojunction double-sided battery and its preparation method |
| CN106684161A (en) * | 2017-02-04 | 2017-05-17 | 江苏神科新能源有限公司 | A silicon-based heterojunction solar cell and its preparation method |
| CN107170850A (en) * | 2017-05-25 | 2017-09-15 | 君泰创新（北京）科技有限公司 | The preparation method and heterojunction solar battery of a kind of heterojunction solar battery |
| CN207637825U (en) * | 2017-12-11 | 2018-07-20 | 晋能光伏技术有限责任公司 | A kind of efficient crystal silicon non crystal heterogeneous agglomeration battery structure |
-
2017
- 2017-12-11 CN CN201711303308.3A patent/CN107819052A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012043124A1 (en) * | 2010-10-01 | 2012-04-05 | 株式会社カネカ | Method for manufacturing photoelectric conversion device |
| US20160284915A1 (en) * | 2013-11-12 | 2016-09-29 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Photovoltaic cell with silicon heterojunction |
| CN204315606U (en) * | 2015-01-21 | 2015-05-06 | 中电投西安太阳能电力有限公司 | Double heterojunction double-sided solar battery |
| WO2016182128A1 (en) * | 2015-05-12 | 2016-11-17 | 주식회사 테스 | Method for manufacturing solar cell module |
| CN106449850A (en) * | 2015-08-05 | 2017-02-22 | 钧石(中国)能源有限公司 | High efficiency silicon-based heterojunction double-sided battery and its preparation method |
| CN106024917A (en) * | 2016-05-31 | 2016-10-12 | 英利能源（中国）有限公司 | A kind of solar cell sheet and solar cell assembly |
| CN205920977U (en) * | 2016-06-29 | 2017-02-01 | 新奥光伏能源有限公司 | Silicon heterojunction solar cell and photovoltaic module with novel projecting pole |
| CN106684161A (en) * | 2017-02-04 | 2017-05-17 | 江苏神科新能源有限公司 | A silicon-based heterojunction solar cell and its preparation method |
| CN107170850A (en) * | 2017-05-25 | 2017-09-15 | 君泰创新（北京）科技有限公司 | The preparation method and heterojunction solar battery of a kind of heterojunction solar battery |
| CN207637825U (en) * | 2017-12-11 | 2018-07-20 | 晋能光伏技术有限责任公司 | A kind of efficient crystal silicon non crystal heterogeneous agglomeration battery structure |
Non-Patent Citations (2)
| Title |
|---|
| 吴其胜等: "新能源材料（第二版）", 30 June 2017, 华东理工大学出版社, pages: 178 - 179 * |
| 周潘兵等: "光伏技术与应用概论", 31 August 2011, 中央广播电视大学出版社, pages: 86 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108538966A (en) * | 2018-04-18 | 2018-09-14 | 晋能光伏技术有限责任公司 | A kind of deficient manufacturing procedure rework preocess method after efficient heterojunction battery CVD |
| CN108538966B (en) * | 2018-04-18 | 2023-11-03 | 晋能光伏技术有限责任公司 | A process method for rework of high-efficiency heterojunction cells with defective processes after CVD |
| CN109638101A (en) * | 2018-12-04 | 2019-04-16 | 江苏爱康能源研究院有限公司 | The emitter structure and preparation method thereof of the double-deck amorphous silicon doped layer solar cell |
| CN109461780B (en) * | 2018-12-13 | 2023-12-15 | 江苏爱康能源研究院有限公司 | High-efficiency crystalline silicon heterojunction solar cell electrode structure with high matching degree and preparation method thereof |
| CN109461780A (en) * | 2018-12-13 | 2019-03-12 | 江苏爱康能源研究院有限公司 | Efficient silicon/crystalline silicon heterojunction solar battery electrode structure of high matching degree and preparation method thereof |
| CN109449227A (en) * | 2018-12-13 | 2019-03-08 | 江苏爱康能源研究院有限公司 | Silicon/crystalline silicon heterojunction solar battery electrode structure of lamination intrinsic layer and preparation method thereof |
| CN109411551A (en) * | 2018-12-13 | 2019-03-01 | 江苏爱康能源研究院有限公司 | Efficient silicon/crystalline silicon heterojunction solar battery electrode structure of multiple deposition and preparation method thereof |
| CN109449227B (en) * | 2018-12-13 | 2023-12-15 | 江苏爱康能源研究院有限公司 | Crystalline silicon heterojunction solar cell electrode structure with stacked intrinsic layers and preparation method thereof |
| CN109411551B (en) * | 2018-12-13 | 2023-12-15 | 江苏爱康能源研究院有限公司 | Multi-step deposition of high-efficiency crystalline silicon heterojunction solar cell electrode structure and preparation method thereof |
| CN109950132A (en) * | 2019-03-01 | 2019-06-28 | 晋能光伏技术有限责任公司 | A method for double-sided deposition of solar cell amorphous silicon layer in tubular PECVD equipment |
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| CN114678434B (en) * | 2021-12-28 | 2024-05-10 | 浙江爱旭太阳能科技有限公司 | Heterojunction battery capable of improving photoelectric conversion efficiency |
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