CN107818959B

CN107818959B - Semiconductor packaging structure

Info

Publication number: CN107818959B
Application number: CN201711180440.XA
Authority: CN
Inventors: 黄仕铭; 林俊宏; 陈奕廷; 詹士伟; 张永兴; 李天伦
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2013-12-04
Filing date: 2013-12-04
Publication date: 2021-09-03
Anticipated expiration: 2033-12-04
Also published as: CN104701270A; CN104701270B; CN107818959A

Abstract

The present invention relates to a semiconductor packaging structure. The semiconductor package structure includes a first substrate, a second substrate, a die, several interconnecting elements and a cladding material. The first substrate has an upper surface. The second substrate has a lower surface, wherein the upper surface of the first substrate is the lower surface facing the second substrate. The die is electrically connected to the upper surface of the first substrate. A plurality of inner connecting elements are electrically connected to the first substrate and the second substrate. The inner connecting elements include an upper portion and a lower portion, wherein the upper portion is joined to the lower portion to form a joint portion, the lower portion has a shoulder portion, the shoulder portion surrounds the joint portion, and the lower portion further has a top surface and a lower portion. The peripheral surface, the top surface is flat, and the shoulder is located at the junction of the top surface and the peripheral surface. The cladding material is located between the upper surface of the first substrate and the lower surface of the second substrate, and covers the die and the internal connection element. Therefore, during reflow, the second substrate does not warp, and the problem of peeling off of the first and second substrates is solved.

Description

Semiconductor packaging structure

The application is filed in 2013, 12 and 4, has an application number of 201310645713.9 and is a divisional application of Chinese patent application named as a semiconductor packaging structure and a semiconductor process

Technical Field

The invention relates to a semiconductor packaging structure. More particularly, the present invention relates to a stacked semiconductor package structure.

Background

The conventional method for manufacturing a stacked semiconductor package structure includes first bonding a die and a plurality of Solder balls (Solder balls) to an upper surface of a lower substrate. Then, a Molding Process is used to form a Molding compound on the upper surface of the lower substrate to encapsulate the die and the solder balls. Then, after the sealing material is solidified, a plurality of openings are formed on the upper surface of the sealing material by using high-temperature laser to expose the upper parts of the solder balls. Then, an upper substrate is placed on the sealing material, so that the solder on the lower surface of the upper substrate contacts the solder balls. Then, a heating oven is used for first heating, so that the solder and the solder balls are melted to form the interconnection element. Then, after forming a plurality of solder balls on the lower surface of the lower substrate, a reflow process is performed. And finally, carrying out a cutting step.

In the conventional manufacturing method, during the process of moving to the heating oven, the lower surface of the upper substrate is only in contact with the molding compound without bonding force, and the solder balls are also only in contact with each other without bonding force, so that the upper substrate and the molding compound are shifted (Shift). In addition, after the first heating, only the solder of the upper substrate and the solder ball of the lower substrate are bonded with each other, but the lower surface of the upper substrate is only contacted with the sealing adhesive material without bonding force. Therefore, after reflow, the upper substrate is easily warped (warp), and even the upper substrate and the lower substrate are peeled off (Peeling off), which affects the yield of the product.

In order to improve the above problem, a new solution is proposed. The solution is to use the solder balls to joint the upper and lower substrates, and then to perform a molding process to form a molding compound between the upper and lower substrates. However, in the molding process, the molding compound is injected between the upper and lower substrates from the side, so the solder balls affect the flow of the molding compound, and the distribution of the filling particles in the molding compound is not uniform.

Disclosure of Invention

One aspect of the present disclosure relates to a semiconductor package structure. In one embodiment, the semiconductor package structure includes a first substrate, a second substrate, a die, a plurality of interconnection elements, and a cladding material. The first substrate has an upper surface. The second substrate has a lower surface, wherein the upper surface of the first substrate faces the lower surface of the second substrate. The die is electrically connected to the upper surface of the first substrate. The inner connecting elements are electrically connected with the first substrate and the second substrate and comprise an upper part and a lower part, wherein the upper part is jointed with the lower part to form the joint part, the lower part is provided with a shoulder part which surrounds the joint part, the lower part is further provided with a top surface and a peripheral surface, the top surface is a plane, and the shoulder part is positioned at the joint of the top surface and the peripheral surface. The cladding material is located between the upper surface of the first substrate and the lower surface of the second substrate and wraps the crystal grains and the internal connecting element.

Another aspect of the present disclosure relates to a semiconductor process. In one embodiment, the semiconductor process comprises the steps of: (a) forming a plurality of first conductive parts on conductive pads on a first substrate of a first substrate, wherein the first substrate further has an upper surface, and the conductive pads on the first substrate are exposed on the upper surface of the first substrate; (b) leveling (Leveling) the first conductive portions so that each of the first conductive portions has a top surface, and the top surfaces are coplanar; (c) electrically connecting a die to an upper surface of a first substrate, wherein the first substrate further has a plurality of first substrate upper conductive pads exposed at the upper surface of the first substrate; (d) applying a coating material on the upper surface of the first substrate to coat the crystal grain and the first conductive parts, wherein the coating material is a B-stage (B-stage) adhesive material; (e) forming a plurality of openings in the cladding material to expose the top surfaces of the first conductive parts; (f) pressing a second substrate on the coating material to make a lower surface of the second substrate adhered to the coating material, wherein the second substrate further has a plurality of second substrate lower conductive pads and a plurality of second conductive portions, the second substrate lower conductive pads are exposed on the lower surface of the second substrate, the second conductive portions are located on the second substrate lower conductive pads, and the second conductive portions contact the top surfaces of the first conductive portions; and (g) performing a heating step to melt the second conductive parts and the first conductive parts to form a plurality of internal connection elements, and curing the coating material to form a C stage.

In this embodiment, since the lower surface of the second substrate is adhered to the covering material, the second substrate and the covering material will not shift during the movement of the whole package structure. In addition, during reflow, the second substrate will not warp, and the problem of peeling the first and second substrates is solved, so as to improve the yield of the product.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the invention.

Fig. 2 shows an enlarged schematic view of the region a of fig. 1.

FIG. 2A is an enlarged schematic view of another embodiment of the interconnection elements.

Fig. 3 to 11 are schematic views illustrating a semiconductor process according to an embodiment of the present invention.

Fig. 12 is a schematic cross-sectional view of another embodiment of a semiconductor package structure of the present invention.

Fig. 13 is an enlarged view of the region B of fig. 12.

Fig. 14 is a schematic cross-sectional view of another embodiment of a semiconductor package structure of the present invention.

Detailed Description

Referring to fig. 1, a schematic cross-sectional view of a semiconductor package structure according to an embodiment of the invention is shown. The semiconductor package 1 includes a first substrate 10, a second substrate 12, a die 14, a plurality of interconnection elements 16, a molding compound 18, and a plurality of solder balls 20.

The first substrate 10 has an upper surface 101, a lower surface 102, a plurality of first substrate upper conductive pads 103 and a plurality of first substrate lower conductive pads 104. In the embodiment, the first substrate 10 is a package substrate, the lower conductive pads 104 of the first substrate are exposed at the lower surface 102 of the first substrate 10, and the upper conductive pads 103 of the first substrate are exposed at the upper surface 101 of the first substrate 10. The first substrate lower conductive pads 104 are electrically connected to the first substrate upper conductive pads 103.

The second substrate 12 has an upper surface 121, a lower surface 122, a plurality of second substrate upper conductive pads 123 and a plurality of second substrate lower conductive pads 124. The upper surface 101 of the first substrate 10 faces the lower surface 122 of the second substrate 12. In the embodiment, the second substrate 12 is a package substrate or an Interposer (Interposer), the upper conductive pads 123 of the second substrate are exposed at the upper surface 121 of the second substrate 12, and the lower conductive pads 124 of the second substrate are exposed at the lower surface 122 of the second substrate 12. The second substrate upper conductive pads 123 are electrically connected to the second substrate lower conductive pads 124.

The die 14 is electrically connected to the upper surface 101 of the first substrate 10. In the present embodiment, the die 14 is attached to the upper surface 101 of the first substrate 10 by flip-chip bonding, that is, the die 14 is electrically connected to the upper surface 101 of the first substrate 10 by its active surface, and its back surface faces upward. The interconnection elements 16 are connected to the first substrate upper conductive pads 103 and the second substrate lower conductive pads 124. In the present embodiment, each of the interconnection elements 16 is formed by a first conductive portion (e.g., Solder Ball) and a second conductive portion (e.g., Pre-Solder) fused together to form an upper portion 161 and a lower portion 162, respectively, wherein the lower portion 162 has a shoulder 1621. The interconnection elements 16 are mainly used for electrically connecting the first substrate upper conductive pads 103 and the second substrate lower conductive pads 124.

The first substrate top pad 103 and the first substrate bottom pad 104, or the second substrate top pad 123 and the second substrate bottom pad 124, of the present invention can be electrically connected by using a conductive Trace (Trace) (not shown), and the second substrate bottom pad 124 can be coplanar with or protruding from the conductive Trace as required.

The encapsulating material 18 is located between the upper surface 101 of the first substrate 10 and the lower surface 122 of the second substrate 12, and encapsulates the die 14 and the interconnection elements 16. The coating material 18 is adhered to the upper surface 101 of the first substrate 10 and the lower surface 122 of the second substrate 12, respectively, and the adhesion between the coating material 18 and the upper surface 101 of the first substrate 10 is substantially the same as the adhesion between the coating material 18 and the lower surface 122 of the second substrate 12. In the present embodiment, the coating material 18 is a Non-Conductive Film (NCF), a Non-Conductive Paste (NCP), or an ABF (Ajinomoto Build-up Film). When the coating material 18 is in a B-stage adhesive state, the upper surface 101 of the first substrate 10 and the lower surface 122 of the second substrate 12 are bonded. Since the lower surface 122 of the second substrate 12 is adhered to the covering material 18, the second substrate 12 and the covering material 18 will not be shifted during the movement of the whole package structure. In addition, after heating, the coating material 18 is cured to be in a C-stage (C-stage) state, and the adhesion between the coating material and the upper surface 101 of the first substrate 10 is substantially the same as the adhesion between the coating material and the lower surface 122 of the second substrate 12, and the bonding effect of the interconnection elements 16 is added, so that the second substrate 12 is not warped (warp) during reflow, and the product yield can be improved.

In the present embodiment, the cladding material 18 has a plurality of receiving grooves 181 for receiving the inner connecting elements 16, the shape of the side walls of the receiving grooves 181 completely conforms to the shape of the inner connecting elements 16, and the outer surfaces of the inner connecting elements 16 completely contact the side walls of the receiving grooves 181, i.e. the shape of the receiving grooves 181 is defined by the inner connecting elements 16. In other words, there is no gap between the inner connecting elements 16 and the side walls of the receiving grooves 181. Thus, the inner connecting elements 16 are tightly bonded to the cladding material 18.

In addition, the cladding material 18 further has a plurality of filler particles (Fillers)182, and the filler particles 182 have different sizes and are uniformly distributed in the cladding material 18 and are not located in the interconnection elements 16. At the same time, the density of the filler particles 182 is also uniform in the cladding material 18. It is noted that the uniformly distributed filler particles 182 may facilitate the uniformity of laser drilled holes in the cladding material 18 during the fabrication process, thereby improving the uniformity of the interconnection elements 16 and the Reliability (Reliability) of the semiconductor package 1.

Furthermore, the filler particles 182 do not need to flow through the mold Channel (Molding Channel), thereby reducing the overall thickness of the cladding material 18, particularly the thickness of the cladding material 18 between the second substrate 12 and the die 14. In one embodiment, the thickness of the cladding material 18 between the second substrate 12 and the die 14 may be no greater than the largest size of the filler particles 182; in another embodiment, the thickness of cladding material 18 between second substrate 12 and die 14 is less than 20 micrometers (μm).

For example, region A in the figure₁And region A₂Respectively representing the left cladding material 18 and the right cladding material 18, wherein region A₁The left-most side of the covering material 18 extends to the right by a predetermined distance which is 10% of the maximum width of the covering material 18, and the area A₂Extending the rightmost side of the coverstock 18 the predetermined distance to the left. Located in the area A₁And region A₂The filler particles 182 have the same particle size distribution and density. In practical experiments, the regions A are respectively captured₁And region A₂Any small area is enlarged, 100 filling particles are respectively taken for comparison, and the area A can be found₁100 filler particles and region A₂The particle size distribution and density of the 100 filler particles in (1) are substantially the same.

The lower solder balls 20 are disposed on the first substrate lower conductive pads 104 for electrically connecting to an external device.

Referring to fig. 2, an enlarged schematic view of the area a of fig. 1 is shown. In the present embodiment, the interconnection element 16 includes an upper portion 161 and a lower portion 162. The upper portion 161 is electrically connected to the second substrate lower conductive pads 124, and the lower portion 162 is electrically connected to the first substrate upper conductive pads 103, wherein the volume of the lower portion 162 is greater than the volume of the upper portion 161. The upper portion 161 engages the lower portion 162 to form an engagement portion 163. The lower portion 162 has a shoulder 1621, a top surface 1622, and a peripheral surface 1623. The shoulder 1621 is located at the intersection of the top surface 1622 and the peripheral surface 1623, and the shoulder 1621 surrounds the junction 163. In this embodiment, the top surface 1622 is a flat surface, and the peripheral surface 1623 is an arc surface, wherein the top surface 1622 is parallel to the conductive pad 103 on the first substrate. The junction 163 is coplanar with the top surface 1622, and the top surface 1622 surrounds the junction 163.

The lower portion 162 has a first width W in the region contacting the conductive pad 103 on the first substrate₁And the upper portion 161 has a second width W in the contact region with the second substrate lower conductive pad 124₂. The lower portion itself has a maximum width W_mThe top surface 1622 has a third width W₃The joint portion 163 has a fourth width W₄Wherein the maximum width W_mIs greater than the first width W₁The second width W₂And the third width W₃And the third width W₃Is greater than the fourth width W₄。

The first width W₁Is approximately equal to the fourth width W₄. In the present embodiment, each of the interconnection elements 16 is formed by a first conductive portion (e.g., Solder Ball) and a second conductive portion (e.g., Pre-Solder) fused together to form the upper portion 161 and the lower portion 162, respectively, so that the maximum width W of the interconnection elements 16 is larger than that of the interconnection elements 16_mCan be effectively reduced so that the Pitch of the interconnection elements 16 can be effectively reduced for Fine Pitch (Fine Pitch) circuits.

The distance between the back surface of the die 14 and the upper surface 101 of the first substrate 10 is a first height h₁The distance between the shoulder 1621 (or the top surface 1622) and the upper surface 101 of the first substrate 10 is a second height h₂The distance between the shoulder 1621 (or the top surface 1622) and the lower surface 122 of the second substrate 12 is a third height h₃Wherein h is₁＞h₂And h is₂+h₃＞h₁。

Referring to FIG. 2A, an enlarged view of another embodiment of the interconnection elements is shown. In the present embodiment, each of the interconnection elements 16 is formed by melting a first conductive portion (e.g., Solder Ball) and a second conductive portion (e.g., Pre-Solder) after being planarized to form the upper portion 161 and the lower portion 162, respectively. Since the first conductive portion 15 is pre-planarized to form a flat top surface 151 (fig. 4), the area of contact is increased, so that even if there is an offset S between the second conductive portion and the first conductive portion, the second conductive portion can contact the top surface 151, thereby ensuring the connection between the upper portion 161 and the lower portion 162 and improving the yield.

Referring to fig. 3-11, a schematic diagram of a semiconductor process according to an embodiment of the invention is shown. Referring to fig. 3, the first substrate 10 is provided. The first substrate 10 has an upper surface 101, a lower surface 102, a plurality of first substrate upper conductive pads 103 and a plurality of first substrate lower conductive pads 104. In the embodiment, the first substrate 10 is a package substrate, the lower conductive pads 104 of the first substrate are exposed at the lower surface 102 of the first substrate 10, and the upper conductive pads 103 of the first substrate are exposed at the upper surface 101 of the first substrate 10. The first substrate lower conductive pads 104 are electrically connected to the first substrate upper conductive pads 103.

Next, a plurality of first conductive portions 15 are formed on the first substrate conductive pads 103. In the present embodiment, the first conductive portions 15 are a plurality of solder balls, which are spherical and have a radius R.

Referring to fig. 4, the first conductive portions 15 are leveled (Leveling) so that each of the first conductive portions 15 has a top surface 151, and the top surfaces 151 are coplanar. In the present embodiment, the first conductive portions 15 are pressed by a mold after being heated to about 170 ℃. The planarized first conductive portion 15 has a second height h₂Wherein R < h₂< 2R and the top surface has a maximum width W, wherein W<2.2R. The maximum width W is substantially equal to the third width W in the final package structure₃(FIG. 2).

Second height h of the first conductive parts 15 after leveling₂Almost the same, the tolerance can be reduced, and the second substrate in the subsequent process can be reduced12 difficulty of engagement. Furthermore, the similarity of the appearance of the flattened first conductive parts 15 is relatively high, which can be used as an anchor point for other processes, thereby providing more process design choices. In addition, the flattened first conductive parts 15 can also reduce the thickness of the whole packaging structure.

Referring to fig. 5, the die 14 is electrically connected to the upper surface 101 of the first substrate 10. In the present embodiment, the die 14 is attached to the upper surface 101 of the first substrate 10 by flip-chip bonding. That is, the die 14 is electrically connected to the upper surface 101 of the first substrate 10 by its active surface, and its back surface is upward. The distance between the back surface of the die 14 and the upper surface 101 of the first substrate 10 is a first height h₁The top surface 151 is spaced apart from the upper surface 101 of the first substrate 10 by a second height h₂Wherein h is₁＞h₂。

Referring to fig. 6, the cladding material 18 is provided. In the embodiment, the coating material 18 is a Non-Conductive Film (NCF), a Non-Conductive Paste (NCP) or an ABF (Ajinomoto Build-up Film), and has a plurality of filler particles (Fillers) 182. The filler particles 182 have different particle sizes and are uniformly distributed in the coating material 18. At this time, the coating material 18 is in a B-stage (B-stage) state.

Referring to fig. 7, the covering material 18 is applied on the upper surface 101 of the first substrate 10 to cover the die 14 and the first conductive portions 15. The cladding material 18 is still in the B-staged state at this point. In the embodiment, the covering material 18 is formed on the upper surface 101 of the first substrate 10 from top to bottom or from bottom to top by pressing or printing, and the like, so that the first conductive portions 15 do not affect the flow of the filling particles 182 in the covering material 18, and the filling particles 182 do not need to pass through the flow process of a mold Channel (Molding Channel), so that the filling particles 182 are still uniformly distributed in the covering material 18.

Referring to fig. 8, a plurality of openings 183 are formed on the cladding material 18 to expose the top surfaces 151 of the first conductive portions 15. In this embodiment, these openings 183 are formed using a low temperature laser. At this time, the clad material 18 is still in the B-stage state.

Referring to fig. 9, the second substrate 12 is provided. The second substrate 12 has an upper surface 121, a lower surface 122, a plurality of second substrate upper conductive pads 123, a plurality of second substrate lower conductive pads 124, and a plurality of second conductive portions 125. The lower surface 122 of the second substrate 12 faces the upper surface 101 of the first substrate 10. In the embodiment, the second substrate 12 is a package substrate or an Interposer (Interposer), the upper conductive pads 123 of the second substrate are exposed at the upper surface 121 of the second substrate 12, and the lower conductive pads 124 of the second substrate are exposed at the lower surface 122 of the second substrate 12. The second substrate upper conductive pads 123 are electrically connected to the second substrate lower conductive pads 124. The second conductive portions 125 are located on the second substrate lower conductive pads 124. In this embodiment, the second conductive parts 125 are a plurality of pre-solders, and the outer surface thereof is an arc surface. The volume of each second conductive portion 125 is less than the volume of each first conductive portion 15.

Then, a lower pressure is applied to press the second substrate 12 on the cladding material 18. Since the coating material 18 is still in the B-stage state, the lower surface 122 of the second substrate 12 can adhere to the coating material 18, and the adhesion between the coating material 18 and the upper surface 101 of the first substrate 10 is substantially the same as the adhesion between the coating material 18 and the lower surface 122 of the second substrate 12. According to one embodiment, the downforce is applied while heating to about 90 ℃, at which time the coverstock 18 is in a flowable state, filling any voids. In addition, since the encapsulant 18 does not require a flow space, the thickness of the overall package structure can be greatly reduced by controlling the amount of the encapsulant 18 and the down pressure.

Referring to fig. 10, a first heating is performed in a heating oven, so that the first conductive portion 15 and the second conductive portion 125 are melted and bonded to form the upper portion 161 and the lower portion 162 of the interconnection element 16, respectively. The operating temperature at this point was about 245 ℃. It is noted that the lower surface 122 of the second substrate 12 is adhered to the encapsulating material 18 during the moving process to the heating oven, so that the second substrate 12 and the encapsulating material 18 are not displaced. In the present embodiment, the first conductive portion 15 has a flat top surface 151, and the volume of the second conductive portion 125 is smaller than the volume of the first conductive portion 15. Thus, after interfusion, the lower portion 162 has a shoulder 1621. At this point, the cladding material 18 may fill the void above the shoulder 1621. That is, the shape of the receiving grooves 181 in the cladding material 18 is defined by the interconnection elements 16.

At this time, the distance between the shoulder 1621 and the lower surface 122 of the second substrate 12 is a third height h₃Wherein h is₂+h₃＞h₁。

After heating for a period of time, the cladding material 18 cures to a C-stage. The solidified covering material 18 has the receiving grooves 181 therein to receive the inner connecting elements 16, the side walls of the receiving grooves 181 completely conform to the shape of the inner connecting elements 16, and the outer surfaces of the inner connecting elements 16 completely contact the side walls of the receiving grooves 181. In other words, no gap exists between the inner connecting elements 16 and the sidewalls of the receiving grooves 181, and the inner connecting elements 16 are tightly bonded to the covering material 18.

Referring to fig. 11, a plurality of lower solder balls 20 are formed on the first substrate lower conductive pads 104. Then, reflow is performed. It is noted that the second substrate 12 is tightly adhered to the molding compound 18 and the first substrate 10, so that the second substrate 12 will not warp after reflow, thereby increasing the yield of the product. Then, dicing is performed to form a plurality of semiconductor packages as shown in fig. 1. During the cutting process, the second substrate 12 is also tightly adhered to the molding compound 18 and the first substrate 10, so that the problem of peeling of the second substrate 12 caused by the stress generated during the cutting process does not occur.

Referring to fig. 12, a schematic cross-sectional view of another embodiment of a semiconductor package structure of the present invention is shown. Referring to fig. 13, an enlarged schematic view of the region B of fig. 12 is shown. The semiconductor package 1a of the present embodiment is substantially the same as the semiconductor package 1 shown in fig. 1 and 2, and its differences are as follows. In the semiconductor package structure 1a of the present embodiment, the upper surface 101 of the first substrate 10 partially covers a first upper dielectric layer 105, and the lower surface 102 of the first substrate 10 partially covers a first lower dielectric layer 106. The first substrate upper conductive pads 103 are exposed from the first upper dielectric layer 105, and the first substrate lower conductive pads 104 are exposed from the first lower dielectric layer 106. In addition, the upper surface 121 of the second substrate 12 partially covers a second upper dielectric layer 126, and the lower surface 122 of the second substrate 12 partially covers a second lower dielectric layer 127. The second substrate upper conductive pads 123 are exposed from the second upper dielectric layer 126, and the second substrate lower conductive pads 124 are exposed from the second lower dielectric layer 127. In the present embodiment, the adhesion between the first upper dielectric layer 105 and the cladding material 18 is substantially the same as the adhesion between the second lower dielectric layer 127 and the cladding material 18.

Referring to fig. 14, a schematic cross-sectional view of another embodiment of a semiconductor package structure of the present invention is shown. The semiconductor package 1b of the present embodiment is substantially the same as the semiconductor package 1 shown in fig. 1 and 2, and its differences are as follows. In the semiconductor package structure 1b of the present embodiment, the thickness of the cladding material 18 between the lower surface 122 of the second substrate 12 and the upper surface 141 of the die 14 is defined as T, and the thickness T is smaller than or equal to the maximum particle size of the filler particles 182. Therefore, the thickness T may also be equal to 0, such that the lower surface 122 of the second substrate 12 contacts the upper surface 141 of the die 14.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Thus, those skilled in the art will appreciate that various modifications and changes can be made to the above embodiments without departing from the spirit of the invention. The scope of the invention is to be determined by the following claims.

Claims

1. a semiconductor packaging structure, is characterized in that, comprises:

a first substrate having an upper surface;

a second substrate having a lower surface, wherein the upper surface of the first substrate faces the lower surface of the second substrate;

a die electrically connected to the upper surface of the first substrate;

A plurality of interconnecting elements electrically connecting the first substrate and the second substrate, the interconnecting elements include an upper portion and a lower portion, wherein the upper portion joins the lower portion to form a joint portion, and the lower portion has a shoulder portion , the shoulder portion surrounds the joint portion, the lower portion further has a top surface and a peripheral surface, the top surface is a plane, and the shoulder portion is located at the junction of the top surface and the peripheral surface; and

a cladding material, located between the upper surface of the first substrate and the lower surface of the second substrate, and covering the die and the internal connection element;

Wherein, the upper surface of the first substrate is partially covered with a first dielectric layer, and the lower surface of the second substrate is partially covered with a second dielectric layer, wherein the coating material adheres to the first dielectric layer when it is in the state of the B-stage adhesive material. a dielectric layer and the second dielectric layer.

2. The semiconductor package structure of claim 1, wherein the first substrate further has a plurality of conductive pads on the first substrate, the second substrate further has a plurality of conductive pads under the second substrate; The lower part is electrically connected to the lower conductive pad of the second substrate, and the lower part is electrically connected to the upper conductive pad of the first substrate.

3 . The semiconductor package structure of claim 1 , wherein the first substrate further has a lower surface and a plurality of conductive pads under the first substrate, and the conductive pads under the first substrate are exposed under the first substrate. 4 . surface, and the conductive pads on the first substrate are exposed on the upper surface of the first substrate; the second substrate further has an upper surface and a plurality of conductive pads on the second substrate, and the conductive pads on the second substrate are exposed on the The upper surface of the second substrate, and the conductive pads under the second substrate are exposed on the lower surface of the second substrate.

4 . The semiconductor package structure of claim 1 , wherein the volume of the lower portion is larger than that of the upper portion. 5 .

5 . The semiconductor package structure of claim 1 , wherein the peripheral surface is an arc surface, and the top surface is parallel to the conductive pads on the first substrate. 6 .

6 . The semiconductor package structure as claimed in claim 1 , wherein a distance between a back surface of the die and the upper surface of the first substrate is a first height h1 , and the shoulder and the upper surface of the first substrate are at a distance h1 . The distance is the second height h2, the distance between the shoulder and the lower surface of the second substrate is the third height h3, where h1>h2, and h2+h3>h1.

7 . The semiconductor package structure of claim 1 , wherein the area of the lower portion in contact with the conductive pad on the first substrate has a first width, and the area of the upper portion in contact with the conductive pad under the second substrate has a first width. 8 . a second width, the lower portion itself has a maximum width, the lower portion further has a top surface, the top surface has a third width, the joint portion has a fourth width, wherein the maximum width is greater than the first width, the The second width and the third width, and the third width is greater than the fourth width.

8 . The semiconductor package structure of claim 1 , wherein the cladding material has a plurality of accommodating grooves for accommodating the inner connecting elements, and the shape of the sidewalls of the accommodating grooves is completely the same as that of the inner connecting elements. 9 . match, and the outer surface of the inner connecting element contacts the side wall of the receiving groove.

9 . The semiconductor package structure of claim 1 , wherein the cladding material has a plurality of accommodating grooves for accommodating the interconnecting elements, and the shape of the accommodating grooves is defined by the interconnecting elements. 10 . .

10 . The semiconductor package structure of claim 1 , wherein the coating material is a non-conductive film, a non-conductive adhesive or ABF. 11 .

11 . The semiconductor package structure as claimed in claim 1 , wherein the cladding material comprises an area A1 and an area A2 , wherein the area A1 is the leftmost edge of the cladding material extending to the right for a predetermined distance. 12 . distance, the preset distance is 10% of the maximum width of the cladding material, and the area A2 is the preset distance extending from the rightmost edge of the cladding material to the left, where the filling in the area A1 and the area A2 The particle size distribution and density of the particles are the same.

12. A semiconductor packaging structure, comprising:

a first substrate having an upper surface;

a second substrate having a lower surface and a plurality of conductive pads under the second substrate, wherein the upper surface of the first substrate faces the lower surface of the second substrate;

a die electrically connected to the upper surface of the first substrate;

A plurality of internal connection elements are electrically connected to the first substrate and the second substrate, the internal connection elements include an upper part and a lower part, wherein the upper part joins the lower part to form a joint part, and the upper part and the second part The contact area of the conductive pad under the substrate has a second width, the lower portion has a top surface, the top surface is flat, the top surface has a third width, and the joint portion has a fourth width, wherein the second width is greater than the fourth width, and the third width is greater than the second width; and

13 . The semiconductor package structure of claim 12 , wherein the first substrate has a plurality of conductive pads on the first substrate, and a region of the lower portion in contact with the conductive pads on the first substrate has a first width, 14 . The lower portion itself has a maximum width, wherein the maximum width is greater than the first width, the second width and the third width, and the third width is greater than the fourth width.

14. The semiconductor package structure of claim 12, wherein the upper surface of the first substrate has a plurality of conductive pads on the first substrate, and the conductive pads on the first substrate are exposed on the first substrate surface, the first substrate further has a lower surface and a plurality of conductive pads under the first substrate, the conductive pads under the first substrate are exposed on the lower surface of the first substrate, and the lower surface of the second substrate has the second substrate a lower conductive pad, and the lower conductive pad of the second substrate is exposed on the lower surface of the second substrate; the second substrate further has an upper surface and a plurality of conductive pads on the second substrate, and the conductive pads on the second substrate are exposed on the upper surface of the second substrate; the upper portion is electrically connected to the lower conductive pad of the second substrate, and the lower portion is electrically connected to the upper conductive pad of the first substrate.

15. The semiconductor package structure of claim 12, wherein the upper portion of each of the interconnecting elements is a pre-solder; the lower portion of each of the interconnecting elements is a solder ball.

16. The semiconductor package structure of claim 12, wherein the upper volume is smaller than the lower ball volume.

17 . The semiconductor package structure of claim 12 , wherein the cladding material has a plurality of accommodating grooves for accommodating the inner connecting elements, and the shape of the sidewalls of the accommodating grooves is completely the same as that of the inner connecting elements. 18 . match, and the outer surface of the inner connecting element contacts the side wall of the receiving groove.

18 . The semiconductor package structure of claim 12 , wherein the cladding material has a plurality of accommodating grooves for accommodating the interconnecting elements, and the shape of the accommodating grooves is defined by the interconnecting elements 18 . .