CN107818806A - Semiconductor storage - Google Patents

Abstract

A semiconductor memory device according to one embodiment includes a memory cell including a resistive memory element, and a write driver. The write driver supplies a first voltage to the memory cell during a first write operation of changing the resistive memory element from a first resistance value to a second resistance value smaller than the first resistance value. The write driver supplies a second voltage different from the first voltage to the memory cell in a second write operation for changing the resistive memory element from the second resistance value to the first resistance value.

Description

semiconductor storage device

Associate application

This application enjoys the priority of the basic application based on US Provisional Patent Application No. 62/394,161 (filing date: September 13, 2016). This application incorporates the entire content of the basic application by referring to this basic application.

technical field

Embodiments of the present invention relate to semiconductor memory devices.

Background technique

As a memory device included in a memory system, a semiconductor memory device having a resistive memory element is known.

As a semiconductor storage device having a resistive memory element, there are known MRAM (Magnetoresistive Random Access Memory, magnetoresistive random access memory), ReRAM (Resistive Random Access Memory, resistive random access memory), PCRAM (Phase-Change Random Access Memory, relative random access memory), etc.

Contents of the invention

Embodiments of the present invention provide a highly reliable semiconductor memory device.

A semiconductor memory device according to an embodiment includes a memory cell including a resistive memory element, and a write driver. The write driver supplies a first voltage to the memory cell during a first write operation for changing the resistive memory element from a first resistance value to a second resistance value smaller than the first resistance value. The write driver supplies a second voltage different from the first voltage to the memory cell in a second write operation for changing the resistive memory element from the second resistance value to the first resistance value.

Description of drawings

FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to a first embodiment.

FIG. 2 is a schematic diagram illustrating the configuration of a memory cell of the semiconductor memory device according to the first embodiment.

3 is a circuit diagram showing connections of a write driver, a current sink (current sink, current sink), and a memory cell array of the semiconductor memory device according to the first embodiment.

4 is a graph for explaining the temperature characteristics of the resistance value of the current path at the time of writing data "1" in the semiconductor memory device according to the first embodiment.

5 is a graph for explaining the temperature characteristics of the resistance value of the current path at the time of writing data "0" in the semiconductor memory device according to the first embodiment.

FIG. 6 is a graph for explaining the temperature characteristics of the voltage when data "1" is written in the semiconductor memory device according to the first embodiment.

7 is a graph for explaining the temperature characteristic of the voltage at the time of writing data "0" in the semiconductor memory device according to the first embodiment.

8 is a circuit diagram showing a configuration of a voltage generation circuit of a control unit of the semiconductor memory device according to the first embodiment.

9 is a graph showing the relationship between voltages generated in the voltage generating circuit of the semiconductor memory device according to the first embodiment.

10 is a circuit diagram showing a configuration of a signal generation circuit of a control unit of the semiconductor memory device according to the first embodiment.

11 is a flowchart showing a write operation of the semiconductor memory device according to the first embodiment.

12 is a timing chart showing a write operation when data "0" is written in the semiconductor memory device according to the first embodiment.

FIG. 13 is a schematic diagram for explaining a write operation when data "0" is written in the semiconductor memory device according to the first embodiment.

FIG. 14 is a timing chart showing a write operation when data "1" is written in the semiconductor memory device according to the first embodiment.

FIG. 15 is a schematic diagram for explaining a write operation when data "1" is written in the semiconductor memory device according to the first embodiment.

16 is a timing chart showing changes in current flowing in the magnetoresistance effect element during a write operation of the semiconductor memory device according to the first embodiment.

17 is a circuit diagram showing connections of a write driver, a current sink, and a memory cell array of the semiconductor memory device according to the second embodiment.

18 is a circuit diagram showing a configuration of a signal generation circuit of a control unit of the semiconductor memory device according to the second embodiment.

19 is a circuit diagram showing connections of a write driver, a current sink, and a memory cell array of the semiconductor memory device according to the third embodiment.

20 is a block diagram showing the configurations of semiconductor memory devices according to a first modification example and a second modification example.

Detailed ways

Hereinafter, embodiments will be described with reference to the drawings. In addition, in the following description, the same code|symbol is attached|subjected to the component which has substantially the same function and a structure, and it repeats description only when necessary. In addition, the embodiments shown below illustrate devices and methods for realizing the technical ideas of the embodiments, and the technical ideas of the embodiments do not limit the materials, shapes, structures, arrangements, etc. of the constituent parts to the following . Various changes can be added to the technical idea of embodiment within the range of a claim.

In addition, in the following description, a magnetic memory device (MRAM: Magnetoresistive Random Access Memory) using a magnetoresistive effect element as a resistive memory element will be described as an example of a semiconductor memory device having a resistive memory element.

1. First Embodiment

The semiconductor memory device according to the first embodiment will be described.

1.1 About composition

First, the configuration of the semiconductor memory device according to the first embodiment will be described.

1.1.1. About the structure of the semiconductor memory device

The semiconductor memory device according to the first embodiment is, for example, a magnetic memory device using a magnetoresistance effect (MTJ: Magnetic Tunnel Junction, Magnetic Tunnel Junction) element as a resistive memory element and utilizing a perpendicular magnetization method.

FIG. 1 is a block diagram showing the configuration of a semiconductor memory device 1 according to the first embodiment. As shown in FIG. 1, a semiconductor memory device 1 has a memory cell array 11, a current sink 12, a sense amplifier and write driver (SA/WD) 13, a row decoder 14, a page buffer 15, an input/output circuit 16, and the control unit 17 .

The memory cell array 11 has a plurality of memory cells 20 associated with rows and columns. Furthermore, the memory cells 20 located in the same row are connected to the same word line WL, and both ends of the memory cells 20 located in the same column are connected to the same bit line BL and the same source line (source line) /BL.

The current sink 12 is connected to the bit line BL and the source line /BL. The current sink 12 sets the bit line BL or the source line /BL to the ground potential during operations such as writing and reading data.

SA/WD13 is connected to bit line BL and source line /BL. SA/WD 13 supplies current to memory cell 20 to be operated via bit line BL and source line /BL, and writes data into memory cell 20 . In addition, SA/WD 13 supplies current to memory cell 20 to be operated via bit line BL and source line /BL, and reads data from memory cell 20 . More specifically, SA/WD 13 includes a first write driver 30 and a second write driver 40 . The first write driver 30 and the second write driver 40 in the SA/WD 13 write data into the memory cell 20 . Also, the sense amplifier of SA/WD 13 reads data from memory cell 20 . The details of data writing using the first write driver 30 and the second write driver 40 will be described later.

Row decoder 14 is connected to memory cell array 11 via word line WL. The row decoder 14 decodes a row address designating a row direction of the memory cell array 11 . Then, word lines WL are selected based on the decoding results, and voltages required for operations such as writing and reading data are applied to the selected word lines WL.

The page buffer 15 temporarily holds data to be written in the memory cell array 11 and data that has been read from the memory cell array 11 in data units called pages.

The input/output circuit 16 transmits various signals received from outside the semiconductor memory device 1 to the control unit 17 and the page buffer 15, and transmits various information from the control unit 17 and the page buffer 15 to the outside of the semiconductor memory device 1. send.

The control unit 17 is connected to the current sink 12 , the SA/WD 13 , the row decoder 14 , the page buffer 15 , and the input/output circuit 16 . The control unit 17 controls the current sink 12 , the SA/WD 13 , the row decoder 14 , and the page buffer 15 according to various signals received by the input/output circuit 16 from outside the semiconductor memory device 1 . Specifically, for example, the control unit 17 includes a voltage generation circuit 50 and a signal generation circuit 60 . Voltage generation circuit 50 and signal generation circuit 60 generate a write voltage and a control signal based on a write signal received from the outside, respectively, and supply the generated write voltage and control signal to SA/WD 13 . Details of the voltage generation circuit 50 and the signal generation circuit 60 will be described later.

1.1.2. About the composition of the storage unit

Hereinafter, the configuration of the memory cell of the semiconductor memory device according to the first embodiment will be described with reference to FIG. 2 . FIG. 2 is a schematic diagram illustrating the configuration of the memory cell 20 of the semiconductor memory device 1 according to the first embodiment.

As shown in FIG. 2 , the memory cell 20 includes, for example, a selection transistor 21 and a magnetoresistance effect element 22 . The selection transistor 21 is provided as a switch for controlling the supply and stop of current when writing and reading data to and from the magnetoresistance effect element 22 . The magnetoresistance effect element 22 includes a plurality of stacked films, and the resistance value can be switched between a low-resistance state and a high-resistance state by flowing a current in a direction perpendicular to the film surface. The magnetoresistance effect element 22 functions as a resistive memory element, and data can be written in accordance with a change in the resistance state, and the written data can be read while being held in a non-volatile state.

In the selection transistor 21 , the gate is connected to the word line WL, one of the source and the drain is connected to the source line /BL, and the other of the source and the drain is connected to one end of the magnetoresistance effect element 22 . The word line WL is, for example, commonly connected to gates of selection transistors (not shown) of other memory cells arranged in the row direction of the memory cell array 11 . The word lines WL are arranged, for example, in the column direction of the memory cell array 11 . The source line /BL extends in the row direction of the memory cell array 11 , and is, for example, commonly connected to the other end of the selection transistor (not shown) of other memory cells arranged in the column direction of the memory cell array 11 . The source line /BL is electrically connected to the first write driver 30 .

The other end of the magnetoresistance effect element 22 is connected to the bit line BL. The bit line BL extends in the row direction of the memory cell array 11 , and is commonly connected to the other end of the magnetoresistive element 22 (not shown) of other memory cells 20 arranged in the column direction of the memory cell array 11 . The bit line BL is electrically connected to the second write driver 40 . The bit line BL and the source line /BL are arranged in the column direction of the memory cell array 11, for example.

1.1.3. Regarding the composition of the magnetoresistance effect element

Hereinafter, the configuration of the magnetoresistance effect element of the semiconductor memory device according to the first embodiment will be described continuously using FIG. 2 .

The magnetoresistance effect element 22 has a storage layer 23 , a tunnel barrier layer 24 and a reference layer 25 . The magnetoresistance effect element 22 is formed by laminating a memory layer 23 , a tunnel barrier layer 24 , and a reference layer 25 in this order. The magnetoresistance effect element 22 is a perpendicular magnetization type MTJ element in which the magnetization orientations of the storage layer 23 and the reference layer 25 are oriented in directions perpendicular to the film surface, respectively.

The storage layer 23 is a ferromagnetic layer having an easy magnetization axis direction perpendicular to the film surface, and includes, for example, cobalt iron boron (CoFeB) or iron boride (FeB). The storage layer 23 has a magnetization direction facing either the selection transistor 21 side or the reference layer 25 side. The magnetization direction of the storage layer 23 is set to be more easily reversed than that of the reference layer 25 .

Tunnel barrier layer 24 is a non-magnetic insulating film made of, for example, magnesium oxide (MgO).

The reference layer 25 is a ferromagnetic layer having an easy magnetization axis direction perpendicular to the film surface, and includes, for example, cobalt platinum (CoPt), cobalt nickel (CoNi), or cobalt palladium (CoPd). The magnetization direction of the reference layer 25 is fixed. In addition, "the magnetization direction is fixed" means that the magnetization direction is not changed by a current of a magnitude capable of reversing the magnetization direction of the storage layer 23 . The storage layer 23, the tunnel barrier layer 24, and the reference layer 25 constitute a magnetic tunnel junction.

In addition, in the first embodiment, spin transfer writing (spin injection writing) is employed in which a write current is directly passed through such a magnetoresistance effect element 22 and the magnetization direction of the storage layer 23 is controlled by the write current. )Way. The magnetoresistance effect element 22 can take either a low-resistance state or a high-resistance state depending on whether the relative relationship between the magnetization directions of the memory layer 23 and the reference layer 25 is parallel or antiparallel.

When a write current in the direction of arrow A1 in FIG. 2 , that is, from storage layer 23 to reference layer 25 flows through magnetoresistance effect element 22 , the relative relationship between the magnetization directions of storage layer 23 and reference layer 25 becomes parallel. In this parallel state, the resistance value of the magnetoresistance effect element 22 becomes low, and the magnetoresistance effect element 22 is set in a low resistance state. This low-resistance state is called "P (Parallel, parallel) state", and is defined as a state of data "0", for example.

When a write current in the direction of arrow A2 in FIG. 2 , that is, from the reference layer 25 to the storage layer 23 flows through the magnetoresistance effect element 22 , the relative relationship between the magnetization directions of the storage layer 23 and the reference layer 25 becomes antiparallel. In this antiparallel state, the resistance value of the magnetoresistance effect element 22 becomes high, and the magnetoresistance effect element 22 is set in a high resistance state. This high-resistance state is called an "AP (Anti-Parallel, anti-parallel) state", and is defined as, for example, a state of data "1".

In addition, in the following description, although the above-mentioned method of defining data will be described, the method of defining data "1" and data "0" is not limited to the above-mentioned example. For example, the P state may be defined as data "1", and the AP state may be defined as data "0".

1.1.4 Regarding the composition of the write drive

Hereinafter, the configuration of the write driver of the semiconductor memory device according to the first embodiment will be described. 3 is a circuit diagram showing connections of a write driver, a current sink, and a memory cell array of the semiconductor memory device according to the first embodiment. FIG. 3 shows a configuration for supplying independent voltages to the magnetoresistance effect element 22 when data "0" is written and when data "1" is written.

As shown in FIG. 3 , the first write driver 30 is electrically connected to one end of the memory cell array 11 via a source line /BL. In addition, the second write driver 40 is electrically connected to the other end of the memory cell array 11 via a bit line BL.

The first write driver 30 is a driver that supplies a voltage for driving a write current when writing data “0” into the memory cells 20 in the memory cell array 11 . The first write driver 30 includes a p-channel MOS transistor 31 . Current sink 12 includes n-channel MOS transistors 32 and 33 . The p-channel MOS transistors and the n-channel MOS transistors have the same size and the same voltage-current characteristics, unless there is a particular distinction between them. In the following description, a p-channel MOS transistor and an n-channel MOS transistor are simply referred to as transistors unless they are particularly distinguished.

In the transistor 31, the signal ENP0 is input to the gate, and the voltage VddWA is supplied to the back gate. In addition, the voltage VddWP is supplied to one end of the transistor 31, and the other end is connected to the source line /BL. The voltage VddWP is a voltage for driving a write current when data "0" is written. In addition, the voltage VddWA is a voltage for driving a write current when data "1" is written. Voltage VddWP is generated independently of voltage VddWA, and is, for example, smaller than voltage VddWA. In addition, the voltage VddWP may have a value equal to or greater than the voltage VddWA.

In the transistor 32, the signal ENN1 is input to the gate, one end is connected to the source line /BL, and the other end is grounded.

In the transistor 33, the signal PR is input to the gate, one end is connected to the source line /BL, and the other end is grounded.

The second write driver 40 is a driver that supplies a voltage for driving a write current when writing data “1” into the memory cells 20 in the memory cell array 11 . The second write driver 40 includes a p-channel MOS transistor 41 . Current sink 12 includes n-channel MOS transistors 42 and 43 .

In the transistor 41, the signal ENP1 is input to the gate, and the voltage VddWA is supplied to the back gate. In addition, the voltage VddWA is supplied to one end of the transistor 41, and the other end is connected to the bit line BL.

In the transistor 42, the signal ENN0 is input to the gate, one end is connected to the bit line BL, and the other end is grounded.

In the transistor 43, the signal PR is input to the gate, one end is connected to the bit line BL, and the other end is grounded.

The voltages VddWA and VddWP, and the signals ENP0 , ENP1 , ENN0 , ENN1 , and PR are generated by, for example, the control unit 17 and supplied to the first write driver 30 or the second write driver 40 . In the magnetoresistance effect element 22 in the memory cell array 11, when the voltage VddWP is supplied to the first write driver 30, the write data “0” flows from the first write driver 30 to the second write driver 40. " current. In addition, when the voltage VddWA is supplied to the second write driver 40 , a current for writing data “1” flows from the second write driver 40 toward the first write driver 30 .

With the configuration as described above, the current flowing in the magnetoresistance effect element 22 can be independently controlled when data “0” is written and when data “1” is written.

Hereinafter, the temperature characteristics of the resistance value between the write drivers according to the first embodiment will be described with reference to FIGS. 4 and 5 .

4 and 5 are graphs illustrating the temperature characteristics of the resistance value between the write drivers of the semiconductor memory device according to the first embodiment. FIG. 4 shows the temperature characteristics of the resistance value of the current path when data "1" is written in a certain temperature range. FIG. 5 shows the temperature characteristics of the resistance value of the current path when data "0" is written in a certain temperature range. The following description applies to at least the temperature ranges shown in FIGS. 4 and 5 .

First, a case where data "1" is written will be described using FIG. 4 . As shown in FIG. 4 , when data “1” is written, the current path between the first write driver 30 and the second write driver 40 is classified into, for example, the magnetoresistance of the memory cell 20 to be written. Each of the effect element portion, the channel region portion, and the wiring portion has a different resistance value. Specifically, the combined resistance value R_wpath_p of the current path includes the resistance value R_MTJp of the magnetoresistance effect element portion, the resistance value R_Ch of the channel region portion, and the resistance value R_wire of the wiring portion. The resistance values R_MTJp, R_Ch, and R_wire each have different temperature characteristics.

The resistance value R_MTJp is the resistance value of the magnetoresistance effect element 22 in a state where the magnetization directions of the storage layer 23 and the reference layer 25 are parallel to each other. The resistance value R_MTJp has, for example, a substantially constant value regardless of changes in temperature. In addition, the resistance value R_MTJp is, for example, about ten thousand ohms, and is larger than the other resistance values R_Ch and C_wire in the entire temperature range.

The resistance value R_Ch is the sum of the resistance values of channel regions in transistors existing in all current paths such as the selection transistor 21 . The resistance value R_Ch has a positive correlation with temperature change. The resistance value R_Ch is, for example, about several thousand ohms, and is larger than the resistance value R_wire in the entire temperature range. In addition, the resistance value R_Ch, for example, has a greater change in resistance value with respect to the temperature of the memory cell 20 than the other resistance values R_MTJp and R_wire.

The resistance value R_wire is the sum of the resistances of wiring existing in the current path, such as the bit line BL and the source line /BL. The resistance value R_wire has a positive correlation with temperature change. The resistance value R_wire is, for example, about several hundred ohms.

The combined resistance value R_wpath_p can be regarded as the value of a resistor formed by connecting the resistance values R_MTJp, R_Ch, and R_wire in series, for example. The resultant resistance value R_wpath_p has a weak positive correlation with respect to the temperature change. Alternatively, the combined resistance value R_wpath_p can be regarded as having a constant value regardless of changes in temperature.

Next, a case where data "1" is written will be described using FIG. 5 .

As shown in FIG. 5, when data "0" is written, the current path between the first write driver 30 and the second write driver 40 is also classified into magnetoresistance effect elements as in the case of FIG. , the channel region portion, and the wiring portion each have a different resistance value. Specifically, the combined resistance value R_wpath_ap of the current path includes the resistance value R_MTJap of the magnetoresistance effect element portion, the resistance value R_Ch, and the resistance value R_wire. The resistance values R_MTJap, R_Ch, and R_wire each have different temperature characteristics.

The resistance value R_MTJap is the resistance value of the magnetoresistance effect element 22 in a state where the magnetization directions of the storage layer 23 and the reference layer 25 are antiparallel to each other. The resistor value R_MTJap is larger than the other resistor values R_Ch and C_wire over the entire temperature range. In addition, although the resistance value R_MTJap has a negative correlation with the temperature of the memory cell 20, it is larger than the resistance value R_MTJp at any temperature.

Regarding the resistance values R_Ch and R_wire, substantially the same temperature characteristics as those shown in FIG. 4 are shown.

The combined resistance value R_wpath_ap can be regarded as the value of a resistance formed by connecting the resistance values R_MTJap, R_Ch, and R_wire in series, for example. The resultant resistance value R_wpath_ap has a strong negative correlation with respect to the temperature change. That is, the absolute value of the change amount with respect to temperature of the combined resistance value R_wpath_ap is larger than the absolute value of the change amount with respect to temperature of the combined resistance value R_wpath_p.

Hereinafter, the temperature characteristics of the voltage supplied to the write driver according to the first embodiment will be described with reference to FIGS. 6 and 7 .

6 is a graph for explaining temperature characteristics of a voltage supplied to a second write driver of the semiconductor memory device according to the first embodiment. FIG. 6 shows the temperature characteristics of the voltage VddWA required when a certain constant current flows with respect to the combined resistance value R_wpath_p.

As shown in FIG. 6 , the voltage VddWA has a weak positive correlation with temperature, like the combined resistance value R_wpath_p. Alternatively, it can be considered that the voltage VddWA is independent of the temperature, similarly to the combined resistance value R_wpath_p.

Voltage VddWA is related to temperature according to the following equation, for example.

VddWA(T)＝VddWA(T0)+Tc1(T－T0) (Tc1≥0)

Here, the temperature T represents an arbitrary temperature, and the temperature T0 is, for example, the temperature of an environment in which the semiconductor memory device 1 normally operates. For example, the temperature T0 is set to 27° C. in an example shown in FIG. 6 , but it is not limited to 27° C., and may be set to an arbitrary value. Voltages VddWA(T) and VddWA(T0) are values of voltage VddWA corresponding to temperatures T and T0, respectively. The gradient Tc1 is a non-negative constant indicating the amount of change in the voltage VddWA with respect to the temperature T. As shown in FIG.

7 is a graph for explaining temperature characteristics of a voltage supplied to a first write driver of the semiconductor memory device according to the first embodiment. FIG. 7 shows temperature characteristics of voltage VddWP required when a certain constant current flows with respect to combined resistance value R_wpath_ap.

As shown in FIG. 7 , the voltage VddWP has a strong negative correlation with the temperature, like the combined resistance value R_wpath_ap. The voltage VddWP is related to the temperature according to the following equation, for example.

VddWP(T)＝VddWP(T0)+Tc0(T－T0) (Tc0＜0)

Here, voltages VddWP(T) and VddWP(T0) are values of voltage VddWA corresponding to temperatures T and T0, respectively. The gradient Tc0 is a negative constant indicating the amount of change in the voltage VddWP with respect to the temperature T. As shown in FIG.

Furthermore, as described above, the inclination Tc1 is set to a non-negative value (Tc1≥0), and the inclination Tc0 is set to a negative value (Tc0<0). Therefore, the inclinations Tc1 and Tc0 have a relationship of Tc1≥0>Tc0. In addition, as described above, the gradient Tc1 with respect to the temperature T has a weak positive correlation, and the gradient Tc0 has a strong negative correlation. Therefore, the absolute value |Tc0| is set to a value larger (|Tc0|>|Tc1|) than the absolute value |Tc1| of the inclination Tc1.

1.1.5 About the composition of the control department

Hereinafter, the configuration of the control unit of the semiconductor memory device according to the first embodiment will be described.

First, the configuration of the voltage generating circuit of the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 8 and 9 . 8 is a block diagram showing the configuration of a voltage generation circuit in the control unit of the semiconductor memory device according to the first embodiment. 9 is a graph showing the relationship between voltages generated in the voltage generating circuit of the semiconductor memory device according to the first embodiment.

As shown in FIG. 8 , the voltage generating circuit 50 includes a reference voltage generating circuit 51 , an AP writing voltage generating circuit 52 , and a P writing voltage generating circuit 53 .

The reference voltage generating circuit 51 generates voltages VREF_PTC and VREF_NTC, and supplies them to each of the AP writing voltage generating circuit 52 and the P writing voltage generating circuit 53 . The voltage VREF_PTC is a voltage having a positive temperature characteristic. The voltage VREF_NTC is a voltage having a negative temperature characteristic. The reference voltage generation circuit 51 includes, for example, a positive temperature characteristic voltage generation circuit 54 and a negative temperature characteristic voltage generation circuit 55 .

Positive temperature characteristic voltage generating circuit 54 generates voltage VREF_PTC, and supplies it to AP writing voltage generating circuit 52 and P writing voltage generating circuit 53 . The negative temperature characteristic voltage generating circuit 55 generates a voltage VREF_NTC, and supplies it to the AP writing voltage generating circuit 52 and the P writing voltage generating circuit 53 . The positive temperature characteristic voltage generation circuit 54 and the negative temperature characteristic voltage generation circuit 55 have a function of generating voltages VREF_PTC and VREF_NTC by changing their own temperature changes. In addition, by considering the temperature change of the positive temperature characteristic voltage generating circuit 54 and the negative temperature characteristic voltage generating circuit 55 as the temperature change of the memory cell 20, the voltages VREF_PTC and VREF_NTC can be regarded as being generated according to the temperature change of the memory cell 20. of. For the positive temperature characteristic voltage generation circuit 54 and the negative temperature characteristic voltage generation circuit 55 , for example, a BGR (Band-gap reference) circuit may be applied, but the invention is not limited thereto.

AP write voltage generation circuit 52 generates voltage VddWA based on voltages VREF_PTC and VREF_NTC when receiving voltages VREF_PTC and VREF_NTC from positive temperature characteristic voltage generation circuit 54 and negative temperature characteristic voltage generation circuit 55 , respectively. The AP writing voltage generating circuit 52 supplies the generated voltage VddWA to the first writing driver 30 .

P writing voltage generation circuit 53 generates voltage VddWP based on voltages VREF_PTC and VREF_NTC when receiving voltages VREF_PTC and VREF_NTC from positive temperature characteristic voltage generation circuit 54 and negative temperature characteristic voltage generation circuit 55 , respectively. The P writing voltage generating circuit 53 supplies the generated voltage VddWP to the first writing driver 30 and the second writing driver 40 .

The AP writing voltage generating circuit 52 and the P writing voltage generating circuit 53 can generate mutually independent voltages VddWA and VddWP by, for example, adding voltages VREF_PTC and VREF_NTC in different ratios.

In the example shown in FIG. 9 , the voltages VREF_PTC, VREF_NTC, VddWA, and VddWP are generated according to, for example, the relationship shown in the following formula.

VddWA=(M1×VREF_PTC+N1×VREF_NTC)/(M1+N1)

VddWP＝(M2×VREF_PTC+N2×VREF_NTC)/(M2+N2)

Here, the numbers M1, N1, M2, and N2 are arbitrary real numbers.

As mentioned above, the voltage VREF_PTC has a positive temperature characteristic (such as the slope TcoP), and the voltage VREF_NTC has a negative temperature characteristic (such as the slope TcoN). In this case, the voltage VddWA has a gradient Tc1=(M1×TcoP+N1×TcoN)/(M1+N1) as a temperature characteristic, and the voltage VddWP has a gradient Tc0=(M2×TcoP+N2×TcoN)/(M2 +N2) as a temperature characteristic. Thus, by giving the numbers M1 and N1 in an appropriate ratio, the inclination Tc1 can be adjusted to 0 or more (Tc1≧0). In addition, by giving the numbers M2 and N2 in an appropriate ratio, the inclination Tc0 can be adjusted to be negative (Tc0<0).

Furthermore, the numbers M1 and N1 can be set independently of the numbers M2 and N2. In addition, the numbers M1, N1, M2 and N2 can be predetermined, and can also be changed within a certain range. By configuring as described above, the voltage generating circuit 50 can generate voltages VddWP and VddWA that have mutually independent values and have mutually different temperature characteristics.

Hereinafter, the configuration of the signal generating circuit of the semiconductor memory device according to the first embodiment will be described with reference to FIG. 10 . 10 is a circuit diagram showing the configuration of a signal generation circuit in the control unit of the semiconductor memory device according to the first embodiment.

As shown in FIG. 10 , the signal generation circuit 60 includes inverters (inverters) 61 , 62 , 63 and 64 . Inverters 61 to 64 are all driven, for example, with voltage VddWA as a driving voltage. That is, the inverters 61 - 64 output high-level signals of the magnitude of the voltage VddWA.

A signal WRT0 is input to the inverter 61 . Signal WRT0 is a signal instructing to write data “0” into memory cells 20 in memory cell array 11 . The signal WRT0 is sent from the outside, for example, and input to the control unit 17 via the input/output circuit 16 . Inverter 61 generates signal ENP0 in which signal WRT0 is inverted (inverted) when signal WRT0 is input. The generated signal ENP0 is input to the inverter 62 and output to the first write driver 30 .

Inverter 62 generates signal ENN0 inverting signal ENP0 when signal ENP0 is input. The generated signal ENN0 is output to the first write driver 30 .

The signal WRT1 is input to the inverter 63 . Signal WRT1 is a signal instructing to write data “0” into memory cells 20 in memory cell array 11 . The signal WRT1 is sent from the outside, for example, and input to the control unit 17 via the input/output circuit 16 . Inverter 63 generates signal ENP1 inverting signal WRT1 when signal WRT1 is input. The generated signal ENP1 is input to the inverter 64 and output to the second write driver 40 .

Inverter 64 generates signal ENN1 inverting signal ENP1 when signal ENP1 is input. The generated signal ENN1 is output to the second write driver 40 .

1.2 About work

Hereinafter, the operation of the semiconductor memory device according to the first embodiment will be described.

1.2.1 Summary of writing work

First, the outline of the writing operation of the semiconductor memory device according to the first embodiment will be described. 11 is a flowchart showing an outline of a write operation of the semiconductor memory device according to the first embodiment. First, before step ST10 , the control unit 17 starts supplying the write voltage to the first write driver 30 and the second write driver 40 as the power is turned on. In addition, the control unit 17 changes the write voltage supplied to the first write driver 30 and the second write driver 40 according to the temperature at this point in time. Specifically, the positive temperature characteristic voltage generating circuit 54 generates a voltage VREF_PTC that is independent of temperature change or has a positive temperature characteristic, and supplies the voltage VREF_PTC to the AP writing voltage generating circuit 52 and the P writing voltage generating circuit 53 . The negative temperature characteristic voltage generating circuit 55 generates a voltage VREF_NTC having a negative temperature characteristic, and supplies it to the AP writing voltage generating circuit 52 and the P writing voltage generating circuit 53 . AP writing voltage generating circuit 52 and P writing voltage generating circuit 53 generate voltages VddWA and VddWP based on voltages VREF_PTC and VREF_NTC, respectively. AP writing voltage generation circuit 52 supplies voltage VddWA to first writing driver 30 and second writing driver 40 . The P write voltage generating circuit 53 supplies the voltage VddWP to the first write driver 30 .

Next, as shown in FIG. 11 , in step ST10 , control unit 17 receives signal WRT0 or WRT1 indicating to write data (either data “0” or data “1”) from the outside via input/output circuit 16 . The control unit 17 selects whether to write data "1" or write data "0" based on the received signal WRT0 or WRT1.

Specifically, for example, in step ST10, when the control part 17 receives signal WRT1, it determines with writing data "1" (ST10; YES), and it progresses to step ST20. Moreover, when the control part 17 receives signal WRT0, it determines with writing data "0" (ST10; NO), and progresses to step ST30.

In step ST20, the control unit 17 executes a writing operation of data "1". In addition, in step ST30, the control unit 17 executes a writing operation of data "0".

At this point, the writing work is finished.

1.2.2 About data "0" writing work

Hereinafter, an operation of writing data "0" in the semiconductor memory device according to the first embodiment will be described. 12 is a timing chart showing a write operation of data "0" in the semiconductor memory device according to the first embodiment. FIG. 12 shows each operation shown in FIG. 11, especially step ST30.

As shown in FIG. 12 , the control unit 17 does not receive a signal instructing writing of data until time T10 is reached. Therefore, the signal WRT0 and the signal WRT1 are input to the control unit 17 at "L (Low)" level until time T10 is reached. Along with this, the inverter 61 outputs a signal ENP0 of “H (High)” level as an inverted signal of the signal WRT0 . Inverter 62 outputs signal ENN0 at "L" level as an inverted signal of signal ENP0. In addition, inverter 63 outputs signal ENP1 at "H" level as an inverted signal of signal WRT1. Inverter 64 outputs signal ENN1 at "L" level as an inverted signal of signal ENP1. On the other hand, "H" level is input to the signal PR. Therefore, until time T10 is reached, the transistors 31 , 32 , 41 , and 42 are in the off state, and the transistors 33 and 43 are in the on state. Thus, the memory cell array 11 is grounded.

At time T10, control unit 17 receives signal WRT0 of "H" level as a signal instructing writing of data "0". Along with this, inverter 61 outputs signal ENP0 at “L” level as an inverted signal of signal WRT0 . Inverter 62 outputs signal ENN0 at "H" level as an inverted signal of signal ENP0. In addition, since the signal WRT1 maintains "L" level, the signal ENP1 and the signal ENN1 do not change. In addition, "L" level is input to the signal PR. Accordingly, at time T10, the transistors 31 and 42 are in the on state, and the transistors 32, 33, 41, and 43 are in the off state.

At time T20, the signal WRT0 and the signal WRT1 are input at "L" level similarly to time T10. Along with this, the inverters 61 and 63 output signals ENP0 and ENP1 of "H" level, respectively. Inverters 62 and 64 output "L" level signals ENN0 and ENN1, respectively. "H" level is input to the signal PR. Therefore, at time T20, the transistors 31, 32, 41, and 42 are in an off state, and the transistors 33 and 43 are in an on state. Thus, the memory cell array 11 is grounded.

FIG. 13 is a schematic diagram for explaining an operation of writing data "0" in the semiconductor memory device according to the first embodiment. In FIG. 13 , the current path of the write current when data "0" is written is indicated by arrows.

As described above, from the time T10 to the time T20, the transistors 31 and 42 are in the on state, and the transistors 32, 33, 41, and 43 are in the off state. Therefore, a current path is formed with the first write driver 30 supplied with the voltage VddWP as one end and the second write driver 40 side grounded as the other end. Therefore, a write current of data "0" flows from the source line /BL toward the bit line BL in the magnetoresistance effect element 22 to be written in the memory cell array 11 . Data “0” is written into the magnetoresistance effect element 22 .

1.2.3 About data "1" writing work

Hereinafter, the write operation of data "1" in the semiconductor memory device of the first embodiment will be described. 14 is a timing chart showing a write operation of data "1" in the semiconductor memory device according to the first embodiment. FIG. 14 shows each operation shown in FIG. 11, especially step ST20.

As shown in FIG. 14 , the control unit 17 does not receive a signal instructing writing of data until time T30 is reached. Therefore, the signal WRT0 and the signal WRT1 are input to the control unit 17 at "L" level until time T30 is reached. Along with this, the inverter 61 outputs a signal ENP0 of “H” level as an inverted signal of the signal WRT0 . Inverter 62 outputs signal ENN0 at "L" level as an inverted signal of signal ENP0. In addition, inverter 63 outputs signal ENP1 at "H" level as an inverted signal of signal WRT1. Inverter 64 outputs signal ENN1 at "L" level as an inverted signal of signal ENP1. On the other hand, "H" level is input to the signal PR. Therefore, until time T30 is reached, the transistors 31 , 32 , 41 , and 42 are in the off state, and the transistors 33 and 43 are in the on state. Thus, the memory cell array 11 is grounded.

At time T30, control unit 17 receives signal WRT1 at "H" level as a signal instructing writing of data "1". Along with this, inverter 63 outputs signal ENP1 at “L” level as an inverted signal of signal WRT1 . Inverter 64 outputs signal ENN1 at "H" level as an inverted signal of signal ENP1. In addition, since the signal WRT0 maintains "L" level, the signal ENP0 and the signal ENN0 do not change. In addition, "L" level is input to the signal PR. Accordingly, at time T30, the transistors 41 and 32 are in the on state, and the transistors 31, 33, 42, and 43 are in the off state.

At time T40, the signal WRT0 and the signal WRT1 are input at "L" level in the same manner as up to time T30. Along with this, the inverters 61 and 63 output signals ENP0 and ENP1 of "H" level, respectively. Inverters 62 and 64 output "L" level signals ENN0 and ENN1, respectively. "H" level is input to the signal PR. Therefore, at time T40, the transistors 31, 32, 41, and 42 are in the off state, and the transistors 33 and 43 are in the on state. Thus, the memory cell array 11 is grounded.

FIG. 15 is a schematic diagram for explaining an operation of writing data "1" in the semiconductor memory device according to the first embodiment. In FIG. 15 , the current path of the write current when data "1" is written is indicated by arrows.

As described above, from the time T30 to the time T40, the transistors 41 and 32 are in the on state, and the transistors 31, 32, 41 and 42 are in the off state. Accordingly, a current path is formed with the second write driver 40 supplied with the voltage VddWA as one end and the first write driver 30 grounded as the other end. Therefore, a write current of data “1” flows from the bit line BL toward the source line /BL in the magnetoresistance effect element 22 to be written in the memory cell array 11 . Data “1” is written into the magnetoresistance effect element 22 .

1.2.4 About write current

Hereinafter, the write current flowing in the magnetoresistance effect element during the write operation of the semiconductor memory device according to the first embodiment will be described. 16 is a timing chart showing changes in a write current flowing in the magnetoresistance effect element of the semiconductor memory device according to the first embodiment. In FIG. 16 , a change in current when data "0" is written and a change in current when data "1" is written are shown together. In addition, times T10 and T20 and times T30 and T40 in FIG. 16 correspond to times T10 and T20 in FIG. 12 and times T30 and T40 in FIG. 14 , respectively.

As shown in FIG. 16, first, writing of data "0" is performed between time T10 and time T20. Furthermore, the magnetoresistance effect element 22 is set to be in the AP state until time T10 is reached.

At time T10 , the control unit 17 supplies the voltage VddWP between the first write driver 30 and the second write driver 40 . Then the current Iap2p flows in the magnetoresistance effect element 22 in the AP state.

At time T15, the magnetoresistance effect element 22 is reversed from the AP state to the P state by the current Iap2p, and data "0" is written therein. Along with this, the resistance value of the magnetoresistance effect element 22 changes from the resistance value R_MTJap to the resistance value R_MTJp, and the flowing current changes from the current Iap2p to the current Ip2p.

In addition, the voltage VddWP is set so that the current Iap2p (and Ip2p) is not too large with respect to the current Ic0 required for the magnetoresistance effect element 22 to invert from the AP state to the P state.

At time T20 , the control unit 17 grounds the first write driver 30 and the second write driver 40 . Then, no current flows through the magnetoresistance effect element 22 .

So far, the writing work of data "0" ends.

Next, writing of data "1" is performed between time T30 and time T40. Furthermore, the magnetoresistance effect element 22 is set in the P state until reaching time T30.

At time T30 , the control unit 17 applies the voltage VddWA between the first write driver 30 and the second write driver 40 . Then the current Ip2ap flows in the magnetoresistance effect element 22 in the P state.

Here, regarding the currents Ip2ap and Ip2p flowing in the magnetoresistance effect elements 22 having the same resistance value R_MTJp, the current Ip2p is smaller than the current Ip2ap. This is because the voltage VddWP applied when the current Ip2p flows is smaller than the voltage VddWA applied when the current Ip2ap flows.

At time T35, the magnetoresistance effect element 22 is reversed from the P state to the AP state by the current Ip2ap, and data "1" is written. Along with this, the resistance value of the magnetoresistance effect element 22 changes from the resistance value R_MTJp to the resistance value R_MTJap, and the flowing current changes from the current Ip2ap to the current Iap2ap.

Here, regarding the currents Iap2p and Iap2ap flowing in the magnetoresistance effect elements 22 having the same resistance value R_MTJap, the current Iap2p is smaller than the current Iap2ap. This is because the voltage VddWP applied when the current Iap2p flows is smaller than the voltage VddWA applied when the current Iap2ap flows.

In addition, the voltage VddWA is set so that the current Ip2ap (and Iap2ap) is not too large with respect to the current Ic1 required for the magnetoresistance effect element 22 to invert from the P state to the AP state.

At time T40, the control unit 17 grounds the first write driver 30 and the second write driver 40 . Then, no current flows through the magnetoresistance effect element 22 .

So far, the writing operation of data "1" ends.

1.3 Effects of this embodiment

There is known a method of reversing the magnetization direction of the memory layer by flowing a current of a predetermined magnitude through the magnetoresistance effect element. In order to reliably reverse the magnetization direction, the write current actually flowing through the magnetoresistance effect element is set to a value larger than the current required to reverse the magnetization direction.

On the other hand, it is known that if a write current of a magnitude larger than the current capable of reversing the magnetization direction is made to flow through the magnetoresistance effect element, the magneto-resistance effect element will return to the direction antiparallel to the desired direction after inversion. The magnetization direction of the state. Such a phenomenon is also called, for example, a back hopping effect, and may cause erroneous writing. In addition, a write current larger than necessary is also undesirable from the viewpoint of reducing power consumption. Therefore, it is necessary to set the write voltage so as to reliably reverse the magnetization direction and prevent excessive current from flowing.

However, in general, the magnitude of the current required to reverse the direction of magnetization differs between the case of writing data "1" (current Ic1) and the case of writing data "0" (current Ic0). In addition, generally, the same write voltage is used when writing data "1" and when writing data "0". Therefore, the write voltage that causes a current of an appropriate magnitude to flow during one data write causes an excessively large current to flow such that bounce occurs during the other data write. More specifically, the writing voltage that flows a current (>current Ic0) of such magnitude as to reverse the magnetization direction of the memory layer 23 of the magnetoresistance effect element 22 in the high resistance state is applied to the magnetoresistance effect in the low resistance state. During writing in which the magnetization direction of the memory layer 23 of the element 22 is reversed, an excessive current flows. In this way, there is still room for discussion about making a current of an appropriate magnitude flow through the magnetoresistance effect element in any case of data writing.

According to the first embodiment, the voltage generating circuit 50 generates the voltage VddWP supplied to the first write driver 30 and the voltage VddWA supplied to the second write driver 40 independently of each other. Thus, the voltage VddWP is supplied to the first write driver 30 in the write operation of data “0”, and the voltage VddWA is supplied to the second write driver 40 in the write operation of data “1”. Therefore, the voltage generation circuit 50 can independently control the current flowing in the magnetoresistance effect element 22 in the writing operation of data "0", and the current flowing in the magnetoresistance effect element 22 in the writing operation of data "1". flowing current. Therefore, erroneous writing due to bounce can be suppressed, and the reliability of the semiconductor memory device 1 at the time of data writing can be improved. More specific reasons are as follows.

In either of the writing operations of data "0" and data "1", the current flowing after the reversal of the magnetization direction causes a bounce effect. Also, the current that flows when data “0” is written increases after the magnetization direction is reversed, and the current that flows when data “1” is written decreases after the magnetization direction is reversed. Therefore, in the writing operation of data "1", the difference between the current flowing after the reversal of the magnetization direction and the current Ic1 required for the reversal of the magnetization direction is small, while in the writing operation of data "0", the magnetization The difference between the current flowing after the reversal of the direction and the current Ic0 required for the reversal of the magnetization direction is large. Therefore, in the writing operation of data "0", bounce is more likely to occur than in the case of writing data "1". Therefore, in order to suppress the bounce effect, it is necessary to suppress the current flowing when data "0" is written to be lower than the current flowing when data "1" is written. However, in general, the same write voltage is used when writing data "1" and when writing data "0". In this case, the current flowing in the magnetoresistance effect element 22 in the AP state has the same magnitude in the writing operation of data "0" and the writing operation of data "1". According to the first aspect of the first embodiment, the voltage VddWP is set to be smaller than the voltage VddWA. As a result, the current flowing through the magnetoresistance effect element 22 in the AP state in the write operation of data "0" becomes smaller than the same current used in the write operation of data "0" and the write operation of data "1". The voltage situation is small. As a result, regarding the current Iap2p and the current Iap2ap, the current Iap2p can be made smaller than the current Iap2ap, and the current Ip2p can also be made smaller. Therefore, erroneous writing due to bounce can be more effectively suppressed, and the reliability of the semiconductor memory device 1 at the time of data writing can be improved.

In addition, according to the second aspect of the first embodiment, the control unit 17 changes the voltage VddWP and the voltage VddWA according to the temperature. Accordingly, when the resistance value of the current path when writing data “0” or data “1” has a temperature characteristic, the value of an appropriate write current to be supplied to the magnetoresistance effect element 22 can be kept at The most appropriate value regardless of temperature changes. Therefore, the reliability of the semiconductor memory device 1 at the time of data writing can be improved.

Specifically, the composite resistance value R_wpath_ap has a strong negative correlation with respect to temperature variations. This is because the temperature characteristic of the resistance value R_MTJap, which is a dominant component of the composite resistance value R_wpath_ap, has a strong negative correlation. Therefore, according to the second aspect of the first embodiment, the temperature characteristic of the voltage VddWP is set to have a strong negative correlation with the temperature change. Accordingly, the temperature characteristic of the voltage VddWP is made to correspond to the temperature characteristic of the combined resistance value R_wpath_ap, and the value of the write current for data “0” can be kept at an optimum value regardless of changes in temperature.

In addition, the combined resistance value R_wpath_p has a positive correlation with respect to the temperature change, or it can be regarded as irrelevant. This is because the temperature characteristic of the resistance value R_MTJp, which is a dominant component of the composite resistance value R_wpath_p, has a weak positive correlation or can be regarded as non-correlation. Therefore, according to the second aspect of the first embodiment, the temperature characteristic of the voltage VddWA is set to have a weak positive correlation with a temperature change, or to have no correlation. Accordingly, the temperature characteristic of the voltage VddWA is made to correspond to the temperature characteristic of the combined resistance value R_wpath_p, and the value of the write current for data “1” can be kept at an optimum value regardless of changes in temperature.

In addition, the absolute value of the change amount of the combined resistance value R_wpath_ap with respect to the temperature is larger than the absolute value of the change amount of the combined resistance value R_wpath_ap with respect to the temperature. Therefore, according to the second aspect of the first embodiment, the absolute value of the change amount of voltage VddWP with respect to temperature is set to be larger than the absolute value of the change amount of voltage VddWA with respect to temperature. Thereby, the relationship of the temperature characteristics of the voltages VddWP and VddWA can be made to correspond to the relationship of the temperature characteristics of the composite resistance values R_wpath_ap and R_wpath_p.

2. Second Embodiment

Hereinafter, the semiconductor memory device according to the second embodiment will be described. The semiconductor storage device according to the second embodiment differs from the semiconductor storage device according to the first embodiment in that the number and types of voltages supplied to the first write driver and the second write driver are different. Specifically, the first write driver and the second write driver of the semiconductor storage device 1 according to the first embodiment are driven by two types of voltages VddWA and VddWP, while the semiconductor storage device of the second embodiment is driven by three types of voltages VddWA and VddWP. and Vdd drive. Hereinafter, the same reference numerals are assigned to the same components as those of the first embodiment, and their descriptions are omitted, and only the parts different from those of the first embodiment will be described.

2.1 About composition

The configuration of the semiconductor memory device according to the second embodiment will be described.

2.1.1. Regarding the composition of the write driver

The configuration of the write driver of the semiconductor memory device according to the second embodiment will be described. 17 is a circuit diagram showing connections of a write driver, a current sink, and a memory cell array of the semiconductor memory device according to the second embodiment.

As shown in FIG. 17 , first write driver 30A and current sink 12 are electrically connected to one end of memory cell array 11 via bit line BL. In addition, the second write driver 40A and the current sink 12 are electrically connected to the other end of the memory cell array 11 via the source line /BL. The first write drivers 30A and 40A have the same configuration as the first write drivers 30 and 40 , respectively.

In the transistor 31, the signal ENP0 is input to the gate, and the voltage Vdd is supplied to the back gate. In addition, the voltage VddWP is supplied to one end of the transistor 31, and the other end is connected to the bit line BL.

In the transistor 41, the signal ENP1 is input to the gate, and the voltage VddWA is supplied to the back gate. In addition, the voltage VddWA is supplied to one end of the transistor 41, and the other end is connected to the source line /BL.

The voltage Vdd is, for example, a power supply voltage input to the semiconductor memory device 1 from the outside, and is, for example, about 1.8V. The voltage Vdd is higher than the voltages VddWA and VddWP, and in this case, the voltages VddWA and VddWP are, for example, approximately 1.5V and 1.2V, respectively. In addition, the voltage values of the above-mentioned voltages Vdd, VddWA, and VddWP are examples, and arbitrary values may be employed within a range satisfying the magnitude relation of Vdd>VddWA>VddWP.

Voltages Vdd, VddWA, and VddWP, and signals ENP0 , ENP1 , ENN0 , ENN1 , and PR are generated, for example, by control unit 18A, and output to first write driver 30A or second write driver 40A. With the configuration as described above, the voltages VddWP and Vdd are supplied to the write driver 30A, and the voltages VddWA and Vdd are supplied to the write driver 40A.

2.1.2 About the composition of the control department

Hereinafter, the configuration of the control unit of the semiconductor memory device according to the second embodiment will be described. 18 is a circuit diagram showing the configuration of a signal generation circuit of a semiconductor memory device according to a second embodiment. As shown in FIG. 18 , the signal generation circuit 60A includes inverters 61 - 64 similarly to the signal generation circuit 60 . All of the inverters 61 to 64 are driven using the voltage Vdd as a driving voltage. That is, the inverters 61 - 64 output signals at the "H" level of the magnitude of the voltage VddWA.

2.2 Effects of this embodiment

The voltage Vdd is input from the outside and commonly used as a power supply voltage in the semiconductor memory device. Therefore, the voltage Vdd may be an excessively high value than the voltage to be supplied to the write driver at the time of data writing. According to the second embodiment, voltages VddWP and VddWA are set to values smaller than voltage Vdd. Thus, the voltages VddWP and VddWA can be generated independently of the voltage Vdd. Therefore, regardless of the value of the voltage Vdd, the control unit 17 can supply the voltages VddWP and VddWA of appropriate magnitudes to the first write driver 30A and the second write driver 40A. Therefore, the reliability of the semiconductor memory device 1 at the time of data writing can be further improved.

In addition, according to the second embodiment, the same effects as those of the first embodiment and the first and second aspects of the first embodiment can be obtained.

3. The third embodiment

Hereinafter, a semiconductor memory device according to a third embodiment will be described. The semiconductor storage device of the third embodiment differs from the semiconductor storage devices of the first and second embodiments in that the gate sizes of the transistors 31 and 41 are different from each other. Hereinafter, the same reference numerals are assigned to the same components as those of the first embodiment, and their descriptions are omitted, and only the parts different from those of the first embodiment will be described.

3.1 About composition

The configuration of the semiconductor memory device according to the third embodiment will be described.

3.1.1. Regarding the composition of the write driver

Hereinafter, the configuration of the write driver of the semiconductor memory device according to the third embodiment will be described. 19 is a circuit diagram showing connections of a write driver, a current sink, and a memory cell array of the semiconductor memory device according to the third embodiment.

As shown in FIG. 19 , the first write driver 30B and the current sink 12 are electrically connected to one end of the memory cell array 11 via the bit line BL. In addition, the second write driver 40B and the current sink 12 are electrically connected to the other end of the memory cell array 11 via the source line /BL. The first write driver 30B includes a p-channel MOS transistor 31B instead of the transistor 31 . The second write driver 40B includes a p-channel MOS transistor 41B instead of the transistor 41 .

In the transistor 31B, the signal ENP0 is input to the gate, and the voltage VddWA is supplied to the back gate. In addition, the voltage VddWP is supplied to one end of the transistor 31B, and the other end is connected to the bit line BL.

In the transistor 41B, the signal ENP1 is input to the gate, and the voltage VddWA is supplied to the back gate. In addition, the voltage VddWA is supplied to one end of the transistor 41B, and the other end is connected to the source line /BL.

The transistors 31B and 41B have different gate sizes, respectively. Specifically, the ratio W31/L31 of the gate length L31 to the gate width W31 of the transistor 31B is smaller than the ratio W41/L41 of the gate length L41 to the gate width W41 of the transistor 41B. Thus, even when the same voltage is applied to the respective gates, back gates, and sources of the transistors 31B and 41B, the value of the current flowing in the drain of the transistor 31B is larger than the value of the current flowing in the drain of the transistor 41B. Small.

3.2 Effects of this embodiment

The magnitude of the current (leakage current) flowing between the source and drain of the transistor depends on the size of the transistor. Specifically, for example, the leakage current may be directly proportional to the gate width of the transistor and inversely proportional to the gate length.

According to the third embodiment, the transistor 31B is set to have a smaller gate size than the transistor 41B. Accordingly, when the same voltage is supplied to respective one ends of the transistor 31B and the transistor 41B, the value of the current flowing through the transistor 31B can be made smaller than the value of the current flowing through the transistor 41B. Therefore, the current flowing through the first write driver 30 can be suppressed to be smaller than the current flowing through the first write driver of the semiconductor memory device according to the first embodiment. Therefore, the reliability of the semiconductor memory device 1 at the time of data writing can be further improved.

In addition, according to the third embodiment, the same effects as those of the first embodiment and the first and second aspects of the first embodiment can be obtained.

4. Modifications, etc.

Embodiments are not limited to the forms described in each of the above-mentioned embodiments, and various modifications are possible. For example, the semiconductor storage device 1 may measure the temperature of the memory cell 20 and feed back information indicating the measured temperature to the generation of the voltages VddWA and VddWP. Hereinafter, the same reference numerals are assigned to the same components as those of the first embodiment, and their descriptions are omitted, and only the parts different from those of the first embodiment will be described.

20 is a block diagram showing the configurations of semiconductor memory devices according to a first modification example and a second modification example. As shown in FIG. 20 , the memory cell array 11 may further include, for example, a monitor circuit 18 .

The monitoring circuit 18 of the first modification may include, for example, a temperature sensor (not shown) to measure the temperature of the storage unit 20 . The monitoring circuit 18 transmits cell information including information indicating the measured temperature of the memory cell 20 to the voltage generation circuit 50 of the control unit 17 .

When receiving the cell information, the voltage generating circuit 50 of the first modification generates voltages VddWA and VddWP based on information indicating the temperature of the memory cell 20 included in the cell information.

According to the first modified example described above, the semiconductor memory device 1 can directly measure the temperature of the memory cell 20 . Therefore, voltages VddWA and VddWP can be generated with more appropriate values than when voltages VddWA and VddWP are generated by approximating the temperature of reference voltage generating circuit 51 to the temperature of memory cell 20 .

In addition, the monitoring circuit 18 of the second modified example may include, for example, a replica storage unit (replica memory cell) (not shown). The monitoring circuit 18 can detect changes in temperature characteristics caused by deterioration over time by monitoring the temperature characteristics of the replica storage unit. The monitoring circuit 18 transmits cell information including information indicating the detected change in temperature characteristics to the voltage generating circuit 50 of the control unit 17 . Such a monitor circuit 18 is not limited to the memory cell array 11 , and may be provided anywhere in the semiconductor memory device 1 . For example, the monitoring circuit 18 may be provided in the control unit 17 .

When receiving the cell information, the voltage generating circuit 50 of the second modification generates voltages VddWA and VddWP based on information indicating changes in temperature characteristics included in the cell information.

According to the second modified example described above, the semiconductor memory device 1 can detect the temporal change in the temperature characteristic of the memory cell 20 . Therefore, voltages VddWA and VddWP can be generated with more appropriate temperature characteristics than when voltages VddWA and VddWP are generated according to predetermined temperature characteristics.

In addition, with regard to the semiconductor memory device 1 described in each of the above-mentioned embodiments, an example in which the voltages VddWA and VddWP are generated in consideration of the temperature characteristic has been described, but the temperature characteristic may not be taken into consideration. In this case, the semiconductor memory device 1 according to the third embodiment can make the voltages VddWA and VddWP supplied to the first write driver 30 and the second write driver 40 equal in value.

In addition, the magnetoresistance effect element 22 described in each of the above-mentioned embodiments has been described as a vertically magnetized MTJ, but is not limited thereto, and may be a horizontally magnetized MTJ element having horizontal magnetic anisotropy.

In addition, the magnetoresistance effect element 22 described in each of the above-mentioned embodiments is a bottomless (bottom free) type in which the memory layer 23 is provided on the semiconductor substrate side and the reference layer 25 is stacked above the memory layer 23. The case has been described, but a topless type in which the reference layer 25 is provided on the semiconductor substrate side and the memory layer 23 is stacked on the reference layer 25 may also be used.

In each of the above-described embodiments, an MRAM using a magnetoresistance effect element has been described as an example of a semiconductor memory device, but the present invention is not limited thereto. For example, it can also be applied to a resistance variable memory like MRAM, for example, a semiconductor memory device having an element that stores data by resistance change, such as ReRAM and PCRAM.

In addition, regardless of whether it is a volatile memory or a nonvolatile memory, the present invention can be applied to any semiconductor storage device having an element capable of changing resistance due to supply of current or application of voltage. To store data, or to read the stored data by converting the resistance difference accompanying the resistance change into a current difference or a voltage difference.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and their equivalents.

Claims (20)

1. a kind of semiconductor storage, the semiconductor storage has：Memory cell including resistance storage element, with And write driver；

Said write driver,

Write making the resistance storage element from the 1st resistance value as the 1st of 2nd resistance value smaller than the 1st resistance value Enter in work, the 1st voltage is supplied to the memory cell；

Make the resistance storage element from the 2nd resistance value turns into the 2nd write-in work of the 1st resistance value, to The memory cell supplies 2nd voltage different from the 1st voltage.

2. semiconductor storage as claimed in claim 1,

2nd voltage described in 1st voltage ratio is small.

3. semiconductor storage as claimed in claim 2,

The 2nd power of voltage ratio voltage is small.

4. semiconductor storage as claimed in claim 1,

The electric current that is flowed in the resistance storage element for the 2nd resistance value in the described 1st write-in work, than The electric current flowed in the 2nd write-in work in the resistance storage element for the 2nd resistance value is small.

5. semiconductor storage as claimed in claim 1,

The electric current that is flowed in the resistance storage element for the 1st resistance value in the described 1st write-in work, than The electric current flowed in the 2nd write-in work in the resistance storage element for the 1st resistance value is small.

6. semiconductor storage as claimed in claim 1,

Said write driver includes：

1st transistor, its 1st end electrically connect with the 1st end of the memory cell, and the 2nd end electrically connects with the 1st voltage, Turn into conducting state in the 1st write-in work and supply the 1st voltage to the 1st end of the memory cell, the described 2nd Turn into cut-off state in write-in work；And

2nd transistor, its 1st end electrically connect with the 2nd end of the memory cell, and the 2nd end electrically connects with the 2nd voltage, Turn into conducting state in the 2nd write-in work and supply the 2nd voltage to the 2nd end of the memory cell, the described 1st Turn into cut-off state in write-in work.

7. semiconductor storage as claimed in claim 6,

The grid size of 1st transistor is smaller than the grid size of the 2nd transistor.

8. a kind of semiconductor storage, the semiconductor storage has：Memory cell including resistance storage element, write Enter driver and voltage generation circuit；

Said write driver makes the resistance storage element turn into the smaller than the 1st resistance value the 2nd from the 1st resistance value In 1st write-in work of resistance value, the 1st voltage is supplied to the memory cell；

1st voltage is supplied said write driver by the voltage generation circuit, the 1st voltage is become according to temperature Change.

9. semiconductor storage as claimed in claim 8,

1st voltage has negative correlation with the temperature.

10. semiconductor storage as claimed in claim 9,

Said write driver makes the resistance storage element turn into the 2nd of the 1st resistance value from the 2nd resistance value Write in work, 2nd voltage different from the 1st voltage is supplied to the memory cell；

2nd voltage is supplied to said write driver by the voltage generation circuit, and the 2nd voltage and the temperature are not It is related.

11. semiconductor storage as claimed in claim 8,

Said write driver makes the resistance storage element turn into the 2nd of the 1st resistance value from the 2nd resistance value Write in work, 2nd voltage different from the 1st voltage is supplied to the memory cell；

2nd voltage is supplied to said write driver by the voltage generation circuit, makes the 2nd voltage according to the temperature Spend and change.

12. semiconductor storage as claimed in claim 11,

2nd voltage has positive correlation with the temperature.

13. semiconductor storage as claimed in claim 12,

1st voltage has negative correlation with the temperature.

14. semiconductor storage as claimed in claim 13,

Change of 1st voltage relative to the absolute value of the variable quantity of the temperature than the 2nd voltage relative to the temperature The absolute value of change amount is big.

15. semiconductor storage as claimed in claim 11,

2nd voltage is bigger relative to the variable quantity of the temperature than the 1st voltage relative to the variable quantity of the temperature.

16. semiconductor storage as claimed in claim 11,

2nd voltage described in 1st voltage ratio is small.

17. semiconductor storage as claimed in claim 16,

The 2nd power of voltage ratio voltage is small.

18. semiconductor storage as claimed in claim 11,

Said write driver includes：

1st transistor, its 1st end electrically connect with the 1st end of the memory cell, and the 2nd end electrically connects with the 1st voltage, Turn into conducting state in the 1st write-in work and supply the 1st voltage to the 1st end of the memory cell, the described 2nd Turn into cut-off state in write-in work；And

2nd transistor, its 1st end electrically connect with the 2nd end of the memory cell, and the 2nd end electrically connects with the 2nd voltage, Turn into conducting state in the 2nd write-in work and supply the 2nd voltage to the 2nd end of the memory cell, the described 1st Turn into cut-off state in write-in work.

19. semiconductor storage as claimed in claim 18,

The grid size of 1st transistor is smaller than the grid size of the 2nd transistor.

20. semiconductor storage as claimed in claim 19,

1st voltage is equal or smaller than the 2nd voltage with the 2nd voltage.