CN107808031A - A kind of restructurable computing system implementation method based on FPGA - Google Patents

Abstract

The invention discloses a kind of restructurable computing system implementation method based on FPGA, comprise the following steps：The first step, definition is with realizing the hardware subsystem based on IP kernel；Second step, definition is with realizing the operating system subsystem based on component；3rd step, define the software subsystem based on component；4th step, update computing system.Traditional computing system is decomposed into hardware subsystem, operating system subsystem and software subsystem by the present invention, and realize the restructural of hardware subsystem based on FPGA, the restructural of software view is realized by the modularization of operating system subsystem and software subsystem, so as to improve the efficiency of system design and flexibility.

Description

A Realization Method of Reconfigurable Computing System Based on FPGA

technical field

The invention relates to the technical field of computing systems, in particular to an FPGA-based reconfigurable computing system implementation method.

Background technique

Since the beginning of the 21st century, the advancement of semiconductor technology and the demand for high-performance computing have promoted the rapid development of computer systems, and the architecture of processors has undergone tremendous changes. As the core component of the computer, the performance improvement of the processor is largely due to the progress of the semiconductor process and the development of the system structure. The progress of the semiconductor process and the development of the system structure have always been in a relationship of mutual promotion, the former is the basis of the latter, and the latter promotes the former. Every change in the development of the architecture is accompanied by a breakthrough in the number of integrated transistors on the chip, which can be said to be a "qualitative change" caused by a "quantitative change" in the number of transistors. At the same time, a complete computing system, in addition to the processor and its instruction set, also includes components such as an operating system and a software system. Traditional computing systems are constructed on the basis of manufactured processors. Although software parts such as operating systems and software systems can be updated dynamically, the hardware part centered on the processor cannot be updated and upgraded. The emergence of reconfigurable hardware makes it possible to reconfigure processors and related hardware.

In the development process of processor technology, reconfigurable computing is an important direction. The concept of reconfigurable computing (Reconfigurable Computing) was first proposed by Estrin et al. in 1963, but the current concept is quite different from that at that time. The commonly used reconfigurable computing refers to: the system has some form of programmability Hardware, the functionality of which can be regularly customized through a series of physical control points, so that different applications can be executed using the same hardware. Reconfigurable computing is expected to fill the gap in performance and flexibility between hardware computing (ASIC-based computing) and software computing (general-purpose processor-based computing), thereby achieving higher performance than software computing while maintaining higher performance than hardware Computing flexibility.

Reconfigurable computing devices are usually composed of arrays of computing elements (Computational elements) and wiring resources (Routing resources), both of which are programmable. A computing unit is also called a logic block, its function is determined by a certain number of configuration bits, and the interconnection between logic blocks is determined by the connection resources. The logic block implements simple logic functions, and realizes complex custom functions through the connection of configurable wires. According to the size of logic block granularity, reconfigurable devices can be divided into fine-grained structure and coarse-grained structure, and some more refined classifications also divide the granularity into fine-grained, medium-grained, coarse-grained, and ultra-coarse-grained. The most common reconfigurable hardware is FPGA (Field Programmable Gate Arrays). Some literature directly equates FPGA-based computing with reconfigurable computing. FPGA is a fine-grained reconfigurable device.

Generally, reconfigurable computing systems use the combination of reconfigurable hardware and general-purpose microprocessors. General-purpose processors perform operations that reconfigurable hardware cannot efficiently complete, such as data-dependent control, storage access, etc., while computationally intensive programs Hotspots are mapped to reconfigurable hardware. According to the coupling method of general-purpose microprocessors and reconfigurable hardware, reconfigurable hardware in computing systems can be roughly divided into four categories: reconfigurable functional units, reconfigurable coprocessors, reconfigurable auxiliary processing units, and reconfigurable Refactored independent processing unit.

In commercial reconfigurable hardware, FPGA is the most mature and common, and it usually exists as an independent chip or even a board. Therefore, in existing commercial reconfigurable computing systems, FPGA is used the most, and most of them are based on the above-mentioned Two coupling structures exist, such as IntelQuickAssist FSB-FPGA acceleration system and XtremeData FPGA acceleration platform as auxiliary processing units, and SRC-7 reconfigurable supercomputer as independent processing units.

For the above-mentioned first two coupling structures, there are many studies on the structure based on single-core processors. However, due to the limitations of semiconductor technology in the past, there is room for continuous improvement in the performance of general-purpose processors and the inconvenience of reconfigurable computing application development, etc. Institutional processors have not been widely available.

A form of computing can be characterized in two ways: flexibility and performance. Considering these two aspects, with performance as the abscissa and flexibility as the ordinate, the characteristics of common computing forms are as follows: general-purpose computing based on general-purpose processors has the highest flexibility, but the concurrency that can be developed and utilized is limited. The performance is relatively the lowest; while the application-customized computing is customized and optimized for specific applications, and the performance is relatively high. However, it is precisely because it is only customized for specific applications that it has the worst flexibility. The two extremes differ a hundredfold in efficiency in terms of performance and energy consumption. Between these two extremes, there are various forms of computing. Among these forms of computing, reconfigurable computing is expected to bridge the gap between application-specific computing and general-purpose computing in terms of flexibility and performance.

Reconfigurable computing uses reconfigurable hardware to customize for different applications, and can make full use of multi-level parallelism from instruction level to task level, so as to achieve performance close to ASIC; and through runtime reconfiguration (Run-time reconfiguration) , RTR) reconfigures the circuit function of the reconfigurable hardware, thus maintaining the flexibility close to the software. Therefore, reconfigurable computing is more cost-effective relative to both extremes, and compared with general-purpose computing, it has achieved significant performance improvements and lower power consumption in different applications, such as intrusion detection, analysis, bioinformatics, etc.

The modules that can be programmed on the FPGA are defined as intellectual property cores or IP cores (IP Core, IntellectualProperty Core). IP core refers to a reusable module provided by a party in the form of logic units and chip designs. The IP core has usually passed the design verification, and the designer designs based on the IP core, which can shorten the cycle required for the design. IP core is divided into soft core, hard core and solid core. The soft core is usually a process-independent design code with a register-transfer-level hardware description language description, which can be followed by design; the hard core is a series of process files after the former passes through logic synthesis, layout, and wiring, and has a specific process form, physical The implementation method; the solid core is usually between the above two. It has passed the process of functional verification and timing analysis, and the designer can obtain it in the form of a logic gate-level netlist.

The so-called on-chip refers to the processor chip; the so-called on-chip device refers to the device integrated on the processor chip; peripheral is the abbreviation of external device. The so-called board refers to a computer system motherboard (motherboard); the so-called on-board device refers to a device integrated or installed on a computer system motherboard.

One of the main goals of processor architecture design is to maintain the programmability and flexibility of the processor while pursuing high-performance and high-efficiency design for application domains. Reconfigurable computing is unparalleled in other forms of computing in this regard. natural advantages. Therefore, the present invention adopts FPGA as the hardware platform realized by the computing system, and transforms the operating system and software system, thereby realizing dynamic update from hardware to software and realizing the reconfigurability of the computing system.

Contents of the invention

The purpose of the present invention is to provide a method for realizing a FPGA-based reconfigurable computing system.

The technical solution adopted by the present invention to solve its technical problems is as follows: a method for implementing a reconfigurable computing system based on FPGA, comprising the following steps:

The first step is to define and implement the hardware subsystem based on the IP core:

1) Definition and implementation of processor IP core:

Define the processor IP core as CIP for the reconfigurable computing system;

2) Define and realize the IP core of the on-board equipment:

The sum of the on-board devices is defined as a set P, set P={P1, P2, P3...,Pm}, which means that there are m on-board devices in the reconfigurable computing system; for any on-board device Pi, it corresponds to an IP Core BIPi, the IP cores corresponding to all m on-board devices form a set BIP, set BIP={BIP1, BIP2, BIP3...,BIPm};

3) Set the computing system configuration file: according to the CIP and the set BIP, set the computing system configuration file;

(1) Whether the hardware subsystem of the computing system needs to be loaded for the first time is indicated by a 2-bit loading bit;

(2) Update status of CIP;

(3) The update status of the IP core of the equipment on the board in the collection BIP;

4) set up the loading file that can run on the FPGA: according to the update status of the device IP core on each board in the CIP and the set BIP and the computing system configuration file, set up the loading file that can run on the FPGA;

The second step is to define and implement the component-based operating system subsystem:

The operating system subsystem is defined as different components, and the set of operating system subsystem components is set OSC, set OSC={OSC1, OSC2, OSC3...OSCm}, which means that there are m components in the operating system subsystem; for any A component OSCi, including component attributes, which are used to define whether the component can be updated and the relationship with other components;

The third step is to define the component-based software subsystem:

Define and realize the software subsystem running in the computing system as different components, the set of software subsystem components is set SSC, set SSC={SSC1, SSC2, SSC3...SSCn}, which means that there are n in the operating system subsystem components; for any component SSCi, including component attributes, the component attributes are used to define whether the component can be updated, and the relationship with other components;

The fourth step is to update the computing system;

The update of the computing system includes the update of three subsystems, which are respectively the hardware subsystem, the operating system subsystem and the software subsystem; if the hardware subsystem based on the IP core changes, the loading file that will be able to run on the FPGA Burning to the FPGA; if the component-based operating system subsystem changes, update the operating system subsystem components on the FPGA; if the component-based software subsystem changes, update the software subsystem components on the FPGA.

Further, the CIP includes a processor core, an on-chip memory, an on-chip bus, an on-chip device, and an external interface.

Further, the information defined in the computing system configuration file includes:

(4) The way CIP is connected to external equipment;

(5) The connection mode between the IP cores of the on-board equipment in the collective BIP;

(6) Integrate the connection mode of the IP core of the on-board equipment in the BIP and the equipment other than the FPGA;

Further, the 2-bit loading bits include 00, 01, 10, and 11, wherein 00 indicates that the system has never created a loading file that can run on the FPGA, and has never been implemented on the FPGA platform. At this time, all IP The update status bits of the core are all 1; 01 is used as a reserved bit; 10 indicates that the hardware subsystem has been loaded, and there is no change in the IP core this time; 11 indicates that the hardware subsystem has been loaded, and there is a change in the IP core this time .

Further, the update status of the CIP is represented by the update status bit U (CIP) of the CIP, if the CIP is not updated, the update status bit U (CIP) of the CIP is set to 0, if the CIP is updated, the update of the CIP The status bit U(CIP) is set to 1;

The update status of the IP core BIPi of any on-board device is represented by the update status bit U(BIPi) of the BIPi. If the BIPi is not updated, the update status bit U(BIPi) of the BIPi is set to 0. If the BIPi is updated, the BIPi The update status bit U(BIPi) of the device is set to 1.

Further, step 4 in the first step) establishes a loading file that can run on the FPGA, specifically:

Process the CIP, integrated BIP and computing system configuration files on the local computer, read the computing system configuration files, connect to each IP core of the computing system, accept the injected data for verification; if the verification fails, output a verification error message , return to the first step; if the verification is passed, check the loading bit in the computing system configuration file:

(1) If the loading bit is 00, it means that the hardware subsystem has not been loaded, then all IP cores, including CIP and IP cores of on-board devices, will be processed uniformly to generate a loading file that can run on the FPGA, and will be able to Burn the loading file running on the FPGA to the FPGA;

(2) If the loading bit is 01 or 10, do nothing;

(3) If the loading bit is 11, it means that the hardware subsystem has been loaded, but the IP core has been updated, then check the U(CIP) in the computing system configuration file and the update status bit of the IP core of each on-board device in the collective BIP, All IP cores whose update status is 1, including CIP and IP cores of on-board devices, are processed in a unified manner to generate a loading file that can run on the FPGA.

Further, in the fourth step, when there are two or more subsystems that need to be updated at the same time, the specific update order is: update the hardware subsystem first, then the operating system subsystem, and finally the software subsystem .

Further, for any component OSCi, the component attribute CP(OSCi)={UPDATE, CList}, wherein:

1) UPDATE=0, indicating that the component OSCi can be updated; UPDATE=1, indicating that the component OSC _CM i cannot be updated;

2) CList represents a list of components that have a communication relationship with OSCi.

Further, for any component SSCi, the component attribute CPS(SSCi)={UPDATE, CPList}, where:

1) UPDATE=0, indicating that the component SSCi can be updated; UPDATE=1, indicating that the component SSCi cannot be updated;

2) CPList represents a list of components that have a communication relationship with SSCi.

Further, for any of the components OSCi and SSCi, component implementations are also respectively included, and the component implementations are specific implementation codes of the components OSCi and SSCi.

Compared with the background technology, the present invention has the beneficial effects that:

The present invention decomposes the traditional computing system into a hardware subsystem, an operating system subsystem and a software subsystem, and realizes the reconfigurability of the hardware subsystem on the basis of FPGA. Realize reconfigurability at the software level, thereby improving the efficiency and flexibility of system design.

(1) Efficiency. FPGA supports the reconfigurability of the computing system at the hardware level, and the componentized operating system and software subsystems realize the reconfigurability of the computing system at the software level, thereby realizing the high efficiency of the entire computing system construction.

(2) Flexibility. The reconfigurable computing system composed of reconfigurable hardware and reconfigurable software can be based on FPGA and supported by componentization to realize dynamic partial reconfiguration of the system, reducing the workload of system construction and improving the flexibility of the system sex.

Description of drawings

FIG. 1 is a flow chart of an FPGA-based reconfigurable computing system implementation method of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

As shown in Figure 1, an FPGA-based reconfigurable computing system implementation method, the specific implementation process is as follows:

The first step is to define and realize the hardware subsystem based on IP core

1) Definition and implementation of processor IP core

Define processor IP core as CIP for reconfigurable computing system, including processor core, on-chip memory, on-chip bus, on-chip device, and external interface. Depending on the actual situation, other modules may also be included, such as new memory modules, specific controllers, and debug interfaces.

In one embodiment, for a specific computing system CM, its processor IP core is CIP(CM).

2) Define and realize the IP core of the on-board equipment

Define on-board device IP cores for reconfigurable computing systems. The sum of on-board devices is defined as a set P, set P={P1, P2, P3...,Pm}, which means that there are m on-board devices in the reconfigurable computing system. For any on-board device Pi, there is one IP core BIPi corresponding, and the IP cores corresponding to all m on-board devices form a set BIP, set BIP={BIP1, BIP2, BIP3...,BIPm}. Wherein, BIP1 is the IP core corresponding to the device P1 on the board, BIP2 is the IP core corresponding to the device P2 on the board, and so on. The on-board bus is defined as on-board devices.

In an embodiment, for the specific computing system CM, there are three on-board devices P1, P2, and P3, and the corresponding IP cores are BIP1, BIP2, and BIP3 respectively, wherein BIP1 is an on-board bus.

3) Set the computing system configuration file

According to the CIP and the collective BIP, set up the computing system configuration file. The following information is defined in the computing system configuration file:

1. Whether the hardware subsystem of the computing system needs to be loaded for the first time is indicated by a 2-digit loading bit, where 00 means that the system has never created a loading file that can run on the FPGA, and has never been implemented on the FPGA platform. At this time The update status bits of all IP cores are 1; 01 is used as a reserved bit; 10 means that the hardware subsystem has been loaded, and there is no IP core change this time; 11 means that the hardware subsystem has been loaded, and there is an IP core this time change.

2. How to connect CIP to external equipment;

3. The connection mode between the IP cores of the on-board equipment in the integrated BIP;

4. Integrate the connection method between the IP core of the on-board equipment in the integrated BIP and the equipment other than the FPGA;

5. The update status of CIP is represented by the update status bit U(CIP) of CIP. If the CIP is not updated, the update status bit U(CIP) of CIP is set to 0. If the CIP is updated, the update status bit of CIP is set to 0. U(CIP) is set to 1;

6. Collect the update status of the IP core of the on-board equipment in the BIP. Any on-board equipment IP core BIPi has an update status bit U(BIPi). If the BIPi has not been updated, the update status bit U(BIPi) of the BIPi is set to is 0, if BIPi is updated, the update status bit U(BIPi) of BIPi is set to 1;

In one embodiment, for the specific computing system CM, its computing system configuration file is Config(CM), wherein the information is:

1. The loading bit is 00;

2. CIP (CM) is connected to the off-chip through a 32-bit bus;

3. BIP2 and BIP3 are connected through a 32-bit bus, and the 32-bit bus is defined and implemented by BIP1;

4. The IP core of the on-board equipment in the integrated BIP is connected to the equipment other than the FPGA through a serial connection;

5. The update status bit U(CIP(CM)) of CIP(CM) is 1;

6. The update status bit U (BIP1) of BIP1 is 1, the update status bit U (BIP2) of BIP2 is 1, and the update status bit U (BIP3) of BIP3 is 1;

4) Create a load file that can run on the FPGA

Process the CIP, integrated BIP and computing system configuration files on the local computer, read the computing system configuration files, connect to each IP core of the computing system, accept the injected data for verification; if the verification fails, output a verification error message , return to the first step; if the verification is passed, check the loading bit in the computing system configuration file:

(1) If the loading bit is 00, it means that the hardware subsystem has not been loaded, then all IP cores, including CIP and IP cores of on-board devices, will be processed uniformly to generate a loading file that can run on the FPGA, and will be able to Burn the loading file running on the FPGA to the FPGA;

(2) If the loading bit is 01 or 10, do nothing;

(3) If the loading bit is 11, it means that the hardware subsystem has been loaded, but the IP core has been updated, then check the U(CIP) in the computing system configuration file and the update status bit of the IP core of each on-board device in the collective BIP, All IP cores whose update status is 1, including CIP and IP cores of on-board devices, are processed in a unified manner to generate a loading file that can run on the FPGA.

In one embodiment, for the specific computing system CM, CIP (CM), BIP1, BIP2, BIP3 and Config (CM) are processed on the local computer, Config (CM) is read, and each IP of the computing system is connected The core accepts the injected data for verification; if the verification fails, output a verification error message and return to the first step; if the verification passes, check the loading bit in the computing system configuration file. Since the loading bit is 00, all IP cores, including CIP (CM) and IP cores BIP1, BIP2, and BIP3 of the on-board device, are processed in a unified manner to generate a loading file HWFile that can run on the FPGA, and can run on The loading file HWFile on the FPGA is programmed to the FPGA.

The second step is to define and implement the component-based operating system subsystem

The operating system subsystem is defined as different components, and the components communicate through interfaces. A single component can be updated, and new components can be added to the operating system subsystem. The set of operating system subsystem components is the set OSC, set OSC={OSC1, OSC2, OSC3...OSCm}, which means that there are m components in the operating system subsystem. Component OSCi includes component attributes and component implementation. Component attributes are used to define whether the component can be updated and the relationship with other components. Component implementation is the specific implementation code of component OSCi.

Existing operating systems, such as Windows 10, are component-based operating systems that can be updated and upgraded online.

In one embodiment, for this specific computing system CM, a component-based operating system subsystem OSC _CM is defined and implemented, and OSC _CM is composed of components OSC _CM 1, OSC _CM 2, OSC _CM 3, OSC _CM 4, OSC _CM 5 composition. Then the operating system subsystem has 5 components in total. For any one of the components OSC _CM i, component attribute CP(OSC _CM i) = {UPDATE, CList}, where:

1) UPDATE=0, indicating that the component OSC _CM i can be updated; UPDATE=1, indicating that the component OSC _CM i cannot be updated;

2) List represents a list of components that have a communication relationship with OSC _CM i;

Then there are:

Table 1 Component properties of the five components in the operating system subsystem OSC _CM of computing system CM

serial number components UPDATE CList illustrate 1 OSC _CM 1 0 OSC _CM 2, OSC _CM 3 can be updated 2 OSC _CM 2 0 OSC _CM 1, OSC _CM 3 can be updated 3 OSC _CM 3 0 OSC _CM 1, OSC _CM 2 can be updated 4 OSC _CM 4 0 OSC _CM 1, OSC _CM 2, OSC _CM 3 can be updated 5 OSC _CM 5 1 OSC _CM 1 cannot update

The third step is to define the component-based software subsystem

For the software that will run in the computing system, it is defined and implemented as different components, the components communicate through the interface, a single component can be updated, and new components can be added to the software. The set of software subsystem components is the set SSC, and the set SSC={SSC1, SSC2, SSC3...SSCn}, which means that there are n components in the operating system subsystem. Component SSCi includes component attributes and component implementation. Component attributes are used to define whether the component can be updated and the relationship with other components. Component implementation is the specific implementation code of component SSCi.

All existing major software can be updated and upgraded online through componentization or similar componentization.

In an embodiment, for this specific computing system CM, a component-based software subsystem SSC _CM is defined and implemented, and the SSC _CM is composed of components SSC _CM 1 , SSC _CM 2 , and SSC _CM 3 . Then the software subsystem consists of three components. For any component SSC _CM i, component attribute CPS(SSC _CM i)={UPDATE, CPList}, where:

1) UPDATE=0, indicating that the component SSC _CM i can be updated; UPDATE=1, indicating that the component SSC _CM i cannot be updated;

2) CPList represents a list of components that have a communication relationship with SSC _CM i;

Then there are:

Table 2 Component attributes of the 3 components in the software subsystem SSC _CM of the computing system CM

serial number components UPDATE CList illustrate 1 SSC _CM 1 0 SSC _CM 2, OSC _CM 3 can be updated 2 SSC _CM 2 0 SSC _CM 1, OSC _CM 3 can be updated 3 SSC _CM 3 0 SSC _CM 1, OSC _CM 2 can be updated

The fourth step, update the computing system

The update of the computing system includes the update of three subsystems, which are the hardware subsystem, the operating system subsystem and the software subsystem. If the hardware subsystem based on the IP core has changed, burn the loading file that can run on the FPGA to the FPGA; if the component-based operating system subsystem has changed, update the operating system subsystem components on the FPGA; if Component-based software subsystems have changed, updating the software subsystem components on the FPGA. When there are two or more subsystems to be updated, the specific update sequence is as follows: update the hardware subsystem first, then the operating system subsystem, and finally the software subsystem.

In one embodiment, for this specific computing system CM, there are loading files HWFile, component-based operating system subsystem OSC _CM , and component-based software subsystem SSC _CM that can run on the FPGA, then:

1) If one of HWFile, OSC _CM and SSC _CM changes, then:

a) If HWFile has changed, burn HWFile to FPGA;

b) If the OSC _CM has changed, update the OSC _CM on the FPGA;

c) If the SSC _CM has changed, update the SSC _CM on the FPGA;

2) If any two of HWFile, OSC _CM and SSC _CM have changed, then:

a) If HWFile and OSC _CM have changed, burn HWFile to FPGA, and then update OSC _CM on FPGA;

b) If HWFile and SSC _CM have changed, burn HWFile to FPGA, and then update SSC _CM on FPGA;

c) If the OSC _CM and SSC _CM have changed, update the OSC _CM on the FPGA, and then update the SSC _CM on the FPGA;

3) If HWFile, OSC _CM and SSC _CM have all changed, first burn HWFile to FPGA, then update OSC _CM on FPGA, and finally update SSC _CM on FPGA.

Here, there are two versions of OSC _CM , the OSC _CM before the operating system subsystem changes, the OSC _CM has been programmed into the FPGA, called the OSC CM on the FPGA, and the OSC _CM after the operating system subsystem changes _CM , called OSC _CM . The so-called update of the OSC _CM refers to replacing the OSC _CM before the change of the operating system subsystem, that is, the OSC _CM on the FPGA, with the OSC _CM after the change of the operating system subsystem, that is, the OSC _CM .

Here, there are two versions of SSC _CM , that is, the SSC _CM before the operating system subsystem changes, the SSC _CM has been programmed into the FPGA, called SSC CM on the FPGA, and the SSC _CM after the operating system subsystem changes _CM , called SSC _CM . The so-called update of the SSC _CM refers to replacing the SSC _CM before the change of the operating system subsystem, that is, the SSC _CM on the FPGA, with the SSC _CM after the change of the operating system subsystem, that is, the SSC _CM .

The descriptions of the above embodiments are only used to help understand the method and core idea of the present invention. It should be pointed out that for those skilled in the art, without departing from the principle of the present invention, some improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims (10)

1. A kind of 1. restructurable computing system implementation method based on FPGA, it is characterised in that：Comprise the following steps：

   The first step, definition is with realizing the hardware subsystem based on IP kernel：

   1) definition is with realizing processor IP nuclear：

   It is CIP for restructurable computing system definition processor IP kernel；

   2) definition is with realizing equipment IP kernel on plate：

   The summation of equipment is defined as a set P, set P={ P1, P2, P3 ..., Pm } on plate, represents in restructurable computing system Share equipment on m plate；For equipment Pi on any one plate, a corresponding IP kernel BIPi, on all m plates corresponding to equipment IP kernel forms a set BIP, set BIP={ BIP1, BIP2, BIP3 ..., BIPm }；

   3) computer system configurations file is set：According to CIP and set BIP, computer system configurations file is set；The computing system Information defined in configuration file includes：

   (1) whether computing system hardware subsystem needs to do to load first, is represented by the loading positions of 2；

   (2) CIP more new state；

   (3) in set BIP on plate equipment IP kernel more new state；

   4) load document that can run on FPGA is established：According to every in the loading positions of described 2 and the CIP, set BIP The more new state of equipment IP kernel on individual plate, establish the load document that can run on FPGA；

   Second step, definition is with realizing the operating system subsystem based on component：

   Operating system subsystem is defined as to different components, the collection of operating system subsystem component is combined into set OSC, set OSC={ OSC1, OSC2, OSC3 ... OSCm }, represents there be m component in the operating system subsystem；For any of which component Whether OSCi, including component property, the component property can update the relation between other assemblies for definitions component；

   3rd step, define the software subsystem based on component：

   The software subsystem run in computing system is defined and is embodied as different components, the set of software subsystem components For set SSC, set SSC={ SSC1, SSC2, SSC3 ... SSCn }, represent there be n component in the operating system subsystem；It is right In any component SSCi, including component property, the component property be used for definitions component whether can update, with other assemblies it Between relation；

   4th step, update computing system：

   The renewal of computing system, includes the renewal of three subsystems, be respectively the hardware subsystem, operating system subsystem and Software subsystem；Changed if based on the hardware subsystem of IP kernel, the load document programming that will be can run on FPGA Onto FPGA；Changed if based on the operating system subsystem of component, update the operating system subsystem group on FPGA Part；Changed if based on the software subsystem of component, update the software subsystem components on FPGA.
2. A kind of 2. restructurable computing system implementation method based on FPGA according to claim 1, it is characterised in that：It is described CIP includes equipment, external interface on processor core, on-chip memory, on-chip bus, piece.
3. A kind of 3. restructurable computing system implementation method based on FPGA according to claim 1, it is characterised in that：It is described Information defined in computer system configurations file also includes：

   (4) CIP is connected to the mode of external equipment；

   (5) connected mode in set BIP on plate between equipment IP kernel；

   (6) in set BIP on plate equipment IP kernel and FPGA external equipment connected mode.
4. A kind of 4. restructurable computing system implementation method based on FPGA according to claim 1, it is characterised in that：It is described The loading position of 2 includes 00,01,10 and 11, wherein 00 expression system was not from setting up the load document that can run on FPGA, Also never realized in FPGA platform；01 is used as reserved bit；10 expression hardware subsystems had loaded, and this does not have IP The change of core；11 expression hardware subsystems had loaded, and this has the change of IP kernel.
5. A kind of 5. restructurable computing system implementation method based on FPGA according to claim 4, it is characterised in that：It is described CIP more new state is represented by CIP renewal mode bit U (CIP), if CIP is not updated, CIP renewal mode bit U (CIP) 0 is set to, if CIP is updated, CIP renewal mode bit U (CIP) is set to 1；

   Equipment IP kernel BIPi more new state is represented by BIPi renewal mode bit U (BIPi) on any one plate, if BIPi Not being updated, then BIPi renewal mode bit U (BIPi) is set to 0, if BIPi is updated, BIPi renewal mode bit U (BIPi) it is set to 1.
6. A kind of 6. restructurable computing system implementation method based on FPGA according to claim 5, it is characterised in that：It is described Step 4) in the first step establishes the load document that can run on FPGA, is specially：

   CIP, set BIP and computer system configurations file are handled on the local computer, read computer system configurations text Part, each IP kernel of computing system is connected, receives injecting data and is verified；If verification is not by output verification mistake letter Breath, return to the first step；If verification passes through, the loading position in computer system configurations file is checked：

   (1) if loading position is 00, represent that hardware subsystem did not load, then by equipment on all IP kernels, including CIP and plate IP kernel, be uniformly processed, generate the load document that can run on FPGA, and the load document that will be can run on FPGA Programming is on FPGA；

   (2) it is without any processing if loading position is 01 or 10；

   (3) if loading position is 11, represent that hardware subsystem had loaded, but IP kernel has renewal, then checks computing system In configuration file in U (CIP), set BIP on each plate equipment IP kernel renewal mode bit, by all more new states be 1 IP The IP kernel of equipment, is uniformly processed on core, including CIP and plate, generates the load document that can run on FPGA.
7. A kind of 7. restructurable computing system implementation method based on FPGA according to claim 1, it is characterised in that：It is described In 4th step, when having two or more subsystems while needing renewal, then specific update sequence is：Preferential renewal is hard Part subsystem, next to that operating system subsystem, is finally software subsystem.
8. A kind of 8. restructurable computing system implementation method based on FPGA according to claim 1, it is characterised in that：For Any of which component OSCi, component property CP (OSCi)={ UPDATE, CList }, wherein：

   1) UPDATE=0, represent that component OSCi can update；UPDATE=1, represent component OSC_CMI can not update；

   2) CList represents the component list for having correspondence with OSCi.
9. A kind of 9. restructurable computing system implementation method based on FPGA according to claim 1, it is characterised in that：For Any of which component SSCi, component property CPS (SSCi)={ UPDATE, CPList }, wherein：

   1) UPDATE=0, represent that component SSCi can update；UPDATE=1, represent that component SSCi can not update；

   2) CPList represents the component list for having correspondence with SSCi.
10. 10. the restructurable computing system implementation method according to claim 1 based on FPGA, it is characterised in that：For institute Any component OSCi and component SSCi are stated, respectively further comprises component realization, it is component OSCi and component SSCi that the component, which is realized, Specific implementation code.