CN107731837A - Memory process method - Google Patents
Memory process method Download PDFInfo
- Publication number
- CN107731837A CN107731837A CN201710851456.2A CN201710851456A CN107731837A CN 107731837 A CN107731837 A CN 107731837A CN 201710851456 A CN201710851456 A CN 201710851456A CN 107731837 A CN107731837 A CN 107731837A
- Authority
- CN
- China
- Prior art keywords
- memory
- memory block
- polysilicon
- logic area
- silica
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 48
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 229920005591 polysilicon Polymers 0.000 claims abstract description 43
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 11
- 238000003860 storage Methods 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000001259 photo etching Methods 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 3
- 238000000576 coating method Methods 0.000 claims abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 230000000717 retained effect Effects 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000012876 topography Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Landscapes
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of memory process method, suitable for the manufacturing process of memory, the steps is included：Step 1: after silica is formed on the storage tube polysilicon gate and grid of memory, it is overall to deposit one layer of polysilicon, the memory block of overlaying memory and logic area；Step 2: overall again deposit one layer of silica；Step 3: remove the silica on memory block top；Step 4: further remove the polysilicon on memory block top；Step 5: remove logic area silica；Step 6: coating photoresist, carries out photoetching to memory block and logic area, opens the window between the polysilicon gate of memory block；Step 7: after window is opened, polysilicon is performed etching；Step 8: remove the photoresist of memory block and logic area.Compared to traditional handicraft, the present invention can save process costs less with one layer of reticle.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process area, particularly relates to a kind of in memory manufacturing process
Method.
Background technology
With continuing to optimize for memory process, the quantity of photolithography plate largely determines being produced into for product
This, has a strong impact on the competitiveness of product in the market.
The production procedure of traditional memory process includes, and oxide layer forms it on memory block polysilicon gate and grid
Afterwards, one layer of polysilicon is deposited, photoetching and etching then are carried out to the polysilicon of memory block, then remove photoresist, then to logic
Area carries out photoetching and etching, removes photoresist.
Such as：Some product under 95nm Self-align (autoregistration) SONOS platforms, carrying out memory cell grid
NPC2 photolithography plates are needed to use to carry out memory cell grid etching during etching.Deposited in substrate surfacePolysilicon after,
Polysilicon in storage region between adjacent S ONOS grids needs to remove by dry etching, falls hole for substrate and layer metal interconnection
Reserved location.By the technique of above-mentioned introduction, because memory block and logic area need step etching, this causes in traditional grid
On the basis of the etching of pole, it is necessary to NPC2 photolithography plates are additionally introduced when storage region etches, the production cost of product is significantly increased.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of memory process method, it is possible to reduce photolithography plate makes
With reduction production cost.
To solve the above problems, memory process method of the present invention, includes the steps：
Step 1: after silica is formed on the storage tube polysilicon gate and grid of memory, overall one layer of deposit
Polysilicon, the memory block of overlaying memory and logic area；
Step 2: overall again deposit one layer of silica；
Step 3: remove the silica on memory block top；
Step 4: further remove the polysilicon on memory block top；
Step 5, remove logic area silica；
Step 6, photoresist is coated, photoetching is carried out to memory block and logic area, opened between the polysilicon gate of memory block
Window；
Step 7, after window is opened, polysilicon is performed etching；
Step 8, remove the photoresist of memory block and logic area.
In the step 1, the thickness of the polysilicon of deposit isThe grid of memory is covered all,
Simultaneously because the surface topography of device, region of the polysilicon between polysilicon gate after deposit, and logic area appearance are recessed
Fall into, apparent height is less than the region of polysilicon gate.
In the step 2, silicon oxide deposition is in polysilicon surface, the thickness of depositThickness is enough
Surface is set to tend to be flat.
In the step 3, the thickness of memory block silicon face is after the silica on removal memory block top
In the step 4, the partial polysilicon for removing memory block top uses CMP or dry etching, memory block residue
Polysilicon thickness is retained in
In the step 5, remove the remaining silica of logic area and use CMP or dry etching, logic area polysilicon thickness
Degree is retained in
Memory process method of the present invention, optimize technique step, eliminates a set of reticle, uses a set of photoetching
Version performs etching simultaneously in storage region and logic area；Save process costs.
Brief description of the drawings
Fig. 1~8 are the inventive method block diagrams.
Fig. 9 is present invention process method flow diagram.
Description of reference numerals
1 is the silica on the grid of memory block, and 2 be memory block grid, and 3 be storage medium, and 4 be polysilicon, and 5 be silicon nitride
Side wall, 6 be silicon substrate, and 7 be memory block, and 8 be logic area, and 9 be silica, and 10 be photoresist.
Embodiment
Memory process method of the present invention, includes the steps：
Step 1, as shown in figure 1, silica and silicon nitride side on the storage tube polysilicon gate and grid of memory
It is overall to deposit one layer of polysilicon 4, the memory block 7 of overlaying memory and logic area 8 after wall is formed.The thickness of the polysilicon 6 of deposit
Spend and beThe grid of memory is covered all, simultaneously because the surface topography of device, the polycrystalline after deposit
Region of the silicon between polysilicon gate, and logic area 8 are recessed, and apparent height is less than the region of polysilicon gate.
Step 2, as shown in Fig. 2 integrally depositing one layer of silica 9 in whole device surface；Silica 9 is deposited on polycrystalline
The surface of silicon 4, the thickness of deposit areThickness is enough to make surface tend to be flat.
Step 3, remove the silica 9 on memory block top；The overall thickness of memory block silicon face surplus material after removal
It is retained inBetween.As shown in figure 3, logic area 8 there remains partial oxidation silicon 9.
Step 4, as shown in figure 4, further removing the polysilicon 9 on memory block top；Remove the part on the top of memory block 7
Polysilicon is retained in using CMP either dry etching, the thickness of memory block remaining polysilicon 4
Step 5, as shown in figure 5, removing logic area silica 9；Technique is more using CMP either dry etching, logic area
The thickness of crystal silicon 4 is retained in
Step 6, as shown in fig. 6, coating photoresist 10, carries out photoetching to memory block 7 and logic area 8, it is more to open memory block
Window between polysilicon gate.
Step 7, after window is opened, polysilicon 4 is performed etching；Logic area grid is formed.As shown in Figure 7.
Step 8, as shown in figure 8, removing the photoresist 10 of memory block 7 and logic area 8.
Present invention process improves for traditional handicraft, and original technological process is to storage region and the quarter of logic region
Erosion needs to complete in two steps：Memory block grid etch is carried out using NPC2 photolithography plates, in dry etching storage region between SONOS pipes
Grid, it is that substrate and metal interconnection fall hole reserved location；Logic area grid is formed using dry etching.And the present invention closes two steps
And be a step, and remove NPC2 photolithography plates.Using process optimizations such as cmp, dry etching, wet etchings, while shape
Into memory block and logic area figure.Save process costs.
The preferred embodiments of the present invention are these are only, are not intended to limit the present invention.Come for those skilled in the art
Various modifications and variations can be had by saying.Within the spirit and principles of the invention, any modification for being made, equivalent substitution, change
Enter, should be included in the scope of the protection.
Claims (6)
- A kind of 1. memory process method, suitable for the manufacturing process of memory, it is characterised in that：Include the steps：Step 1: after silica is formed on the storage tube polysilicon gate and grid of memory, it is overall to deposit one layer of polycrystalline Silicon, the memory block of overlaying memory and logic area；Step 2: overall again deposit one layer of silica；Step 3: remove the silica on memory block top；Step 4: further remove the polysilicon on memory block top；Step 5: remove logic area silica；Step 6: coating photoresist, carries out photoetching to memory block and logic area, opens the window between the polysilicon gate of memory block Mouthful；Step 7: after window is opened, polysilicon is performed etching；Step 8: remove the photoresist of memory block and logic area.
- 2. memory process method as claimed in claim 1, it is characterised in that：In the step 1, the polysilicon of deposit Thickness isThe grid of memory is covered all, simultaneously because the surface topography of device, more after deposit Region of the crystal silicon between polysilicon gate, and logic area are recessed, and apparent height is less than the region of polysilicon gate.
- 3. memory process method as claimed in claim 1, it is characterised in that：In the step 2, silicon oxide deposition is more Crystal silicon surface, the thickness of deposit areThickness is enough to make surface tend to be flat.
- 4. memory process method as claimed in claim 1, it is characterised in that：In the step 3, memory block top is removed Silica after the thickness of memory block silicon face be
- 5. memory process method as claimed in claim 1, it is characterised in that：In the step 4, memory block top is removed Partial polysilicon use CMP or dry etching, memory block remaining polysilicon thickness is retained in
- 6. memory process method as claimed in claim 1, it is characterised in that：In the step 5, it is remaining to remove logic area Silica use CMP or dry etching, logic area polysilicon thickness is retained in
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710851456.2A CN107731837A (en) | 2017-09-19 | 2017-09-19 | Memory process method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710851456.2A CN107731837A (en) | 2017-09-19 | 2017-09-19 | Memory process method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107731837A true CN107731837A (en) | 2018-02-23 |
Family
ID=61207704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710851456.2A Pending CN107731837A (en) | 2017-09-19 | 2017-09-19 | Memory process method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107731837A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050042828A1 (en) * | 2003-08-21 | 2005-02-24 | Jung-Ho Moon | Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device |
| CN102693946A (en) * | 2012-06-11 | 2012-09-26 | 上海宏力半导体制造有限公司 | Methods for manufacturing semiconductor and memory |
| CN104752359A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Memory device and forming method thereof |
-
2017
- 2017-09-19 CN CN201710851456.2A patent/CN107731837A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050042828A1 (en) * | 2003-08-21 | 2005-02-24 | Jung-Ho Moon | Semiconductor device with split gate electrode structure and method for manufacturing the semiconductor device |
| CN102693946A (en) * | 2012-06-11 | 2012-09-26 | 上海宏力半导体制造有限公司 | Methods for manufacturing semiconductor and memory |
| CN104752359A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Memory device and forming method thereof |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20180223 |
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