CN107633803B - Signal masking unit, signal masking method and display panel - Google Patents

Abstract

The disclosure provides a signal shielding unit, a signal shielding method and a display panel. The reset unit is used for receiving a reset voltage and receiving a first control signal according to the driving signal. The first switch unit is used for receiving the pulse signal and receiving a second control signal according to the driving signal. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit does not work, the first switch unit is conducted and outputs the pulse signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs the working voltage to the first switch unit, and the first switch unit is turned off. The display device and the display method can reduce the power consumption of the display device while not reducing the efficiency of the display device.

Description

Signal masking unit, signal masking method and display panel

technical field

The present application relates to a signal masking unit, a signal masking method and a display panel, and particularly relates to a signal masking unit with low power consumption, a signal masking method and a display panel.

Background technique

With the rapid development of display devices, people use large and small display devices, such as mobile phones, computers, etc., on any occasion and at any time. While using the display device, different power consumption is caused each time the screen of the display device changes, and the power consumption also directly affects people's more concerns about using the display device.

Therefore, as people pay more and more attention to the issue of power saving and energy saving, how to reduce the power consumption of the display device without reducing the performance of the display device is one of the problems to be improved in the art.

SUMMARY OF THE INVENTION

An embodiment of the present application provides a signal masking unit. The signal mask unit includes a reset unit and a first switch unit. The reset unit is used for receiving the reset voltage and receiving the first control signal according to the driving signal. The first switch unit is electrically connected to the reset unit for receiving the pulse signal and receiving the second control signal according to the driving signal. The second control signal and the first control signal are inverted. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the reset unit does not work, and the second control signal turns on the first switch unit so that the first switch unit outputs a pulse signal. When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs a working voltage to the first switch unit, and the working voltage and the second control signal turn off the first switch unit.

Another embodiment of the present application is to provide a signal masking method for driving circuits. The signal masking method includes the following steps: making the driving circuit receive the first control signal and the second control signal according to the driving signal; making the driving circuit receive the pulse signal; when the first control signal is at the first voltage level and the second control signal is at the When the second voltage level is used, the drive circuit is made to output the pulse signal; and when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the drive circuit is made to stop outputting the pulse signal.

Another embodiment of the present application is to provide a display panel. The display panel includes a plurality of scan lines, a multi-level signal generator and a multi-level signal mask unit. Each signal generator generates a driving signal, and transmits the driving signal to the next-stage signal generator. The plurality of signal mask units are respectively coupled between one of the plurality of scan lines and the multi-level signal generator. The signal masking unit of each stage receives the first control signal and the second control signal according to the driving signal sent by the coupled signal generator of the current stage, wherein the second control signal is inverse to the first control signal, and when When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the stage signal mask unit sends the pulse signal to one of the plurality of scan lines.

Therefore, according to the technical implementation of this application, the embodiments of this application provide a signal masking unit, a signal masking method and a display panel, and particularly relate to a signal masking unit and a signal masking method with low power consumption and a display panel, thereby effectively reducing the power consumption of the display device without reducing the performance of the display device.

Description of drawings

In order to make the above-mentioned and other objects, features, advantages and embodiments of the present invention more clearly understood, the descriptions of the accompanying drawings are as follows:

FIG. 1 is a schematic diagram of a display panel according to some embodiments of the present application;

FIG. 2 is a schematic diagram of a signal masking unit according to some embodiments of the present application;

FIG. 3 is a detailed schematic diagram of a signal masking unit according to some embodiments of the present application; and

4 is a schematic diagram of an operation waveform according to some embodiments of the present application;

FIG. 5 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 6 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 7 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 8 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 9 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 10 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 11 is a schematic diagram of an operation waveform according to some embodiments of the present application;

FIG. 12 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 13 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 14 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 15 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 16 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application;

FIG. 17 is a schematic diagram of the operation of a signal masking unit according to the embodiment shown in FIG. 3 of the present application; and

FIG. 18 is a flowchart of a signal masking method according to some embodiments of the present application.

Description of reference numbers:

100: Display panel

110A～110N: Signal generator

120A～120N: Signal mask unit

120: Signal mask unit

130: Active Zone

GA to GN: scan line

En: drive signal

Vrst: reset voltage

VDD: working voltage

Vin_1, Vin_2:

RST1: Reset unit

T1, T2, T3, T4, T5, T6:

CLK: pulse signal

G[n]: Scan line voltage

BT, Q: Node

OUT: output terminal

400, 500: Operation waveform

P1, P2, P3, P4, P5, P6: Period

P7, P8, P9, P10, P11, P12: Period

600: Signal mask method

S610, S620, S630, S640, S650: Steps

Detailed ways

The following disclosure provides many different embodiments or illustrations for implementing different features of the invention. The elements and configurations in the specific examples are used in the following discussion to simplify the present disclosure. Any examples discussed are for illustrative purposes only and do not in any way limit the scope and meaning of the invention or its examples. Furthermore, the present disclosure may repeat references to numerical symbols and/or letters in different instances, such repetitions are for simplicity and clarification, and do not themselves specify the relationship between the different embodiments and/or configurations discussed below.

Terms used throughout the specification and claims generally have their ordinary meanings used in the art, in this disclosure, and in a particular context, unless otherwise noted. Certain terms used to describe the present disclosure are discussed below or elsewhere in this specification to provide those skilled in the art with additional guidance in the description of the present disclosure.

As used herein, "coupled" or "connected" may refer to two or more elements in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and "coupled" or "connected" "Connected" may also refer to the mutual operation or action of two or more elements.

Herein, the terms first, second, and third, etc., will be understood to describe various elements, components, regions, layers and/or blocks. However, these elements, components, regions, layers and/or blocks should not be limited by these terms. These terms are only used to identify a single element, component, region, layer and/or block. Thus, a first element, component, region, layer and/or block hereinafter could also be termed a second element, component, region, layer and/or block without departing from the scope of the present invention. As used herein, the term "and/or" includes any combination of one or more of the associated listed items. References to "and/or" in this document refer to any, all, or any combination of at least one of the listed elements.

See Figure 1. FIG. 1 is a schematic diagram of a display panel 100 according to some embodiments of the present application. As shown in FIG. 1 , the display panel 100 includes multi-level signal generators 110A - 110N, a plurality of signal mask units 120A - 120N, a plurality of scan lines GA - GN, and an active area 130 . The signal mask units 120A- 120N are respectively coupled between one of the scan lines GA-GN and one of the multi-level signal generators 110A- 110N. The active area 130 is coupled to the plurality of scan lines GA˜GN. In some embodiments, each of the multi-level signal generators 110A- 110N respectively generates the driving signal En, and transmits the driving signal En to the next-level signal generator among the multi-level signal generators 110A- 110N. For example, as shown in FIG. 1 , the signal generator 110A transmits the driving signal En to the signal generator 110B, the signal generator 110B transmits the driving signal En to the signal generator 110C, and so on.

In some embodiments, for example, only when the scan line voltage G[n] output to the scan line GA is at a low voltage level, the scan line GA will update the active area 130 coupled to the scan line GA, but This case is not limited to this. The rest of the scan lines GB to GN and so on. The operation of each element will be described below in conjunction with FIG. 2 .

See Figure 2. FIG. 2 is a schematic diagram of a signal masking unit 120 according to some embodiments of the present application. In some embodiments, the signal masking unit 120 of FIG. 2 is used to implement the signal masking unit 120A, 120B, 120C . . . or 120N in the first figure. The signal masking unit 120 receives the first control signal and the second control signal according to the driving signal transmitted by the coupled signal generator. The second control signal is inverted from the first control signal. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal mask unit 120 transmits the pulse signal to one of the plurality of scan lines GA˜GN. For example, the signal mask unit 120A in FIG. 1 receives the first control signal Vin_1 and the second control signal Vin_2 according to the driving signal En transmitted by the signal generator 110A coupled to the signal mask unit 120A. When the first control signal is at the first voltage level and the second control signal is at the second voltage level, the signal mask unit 120A transmits the pulse signal CLK to the scan line GA. The rest of the signal mask units 120B to 120N are analogous.

As shown in FIG. 2 , the signal mask unit 120 includes a reset unit RST1 , a switch unit T1 , a switch unit T2 and a switch unit T3 . The switch unit T1 is electrically connected to the reset unit RST1. The switch unit T2 is electrically connected to the reset unit RST1. The switch unit T3 is electrically connected to the switch unit T1.

The reset unit RST1 receives the reset voltage Vrst and determines whether to receive the control signal Vin_1 according to the driving signal En. The switch unit T1 receives the pulse signal CLK and determines whether to receive the control signal Vin_2 according to the driving signal En. The control signal Vin_1 and the control signal Vin_2 are inverted. When the control signal Vin_1 is at the first voltage level and the control signal Vin_2 is at the second voltage level, the reset unit RST1 does not work, and the control signal Vin_2 turns on the switch unit T1 so that the switch unit T1 outputs the pulse signal CLK as shown in FIG. 1 One of the multiple scan lines G1-GN shown. When the control signal Vin_1 is at the second voltage level and the control signal Vin_2 is at the first voltage level, the reset unit RST1 outputs the working voltage VDD to the switch unit T1, and the working voltage VDD and the control signal Vin_2 turn off the switch unit T1.

In some implementations, the switch unit T2 receives the control signal Vin_1 and turns on the control signal Vin_1 to the reset unit RST1 according to the driving signal En. The switch unit T3 receives the control signal Vin_2 and turns on the control signal Vin_2 to the switch unit T1 according to the driving signal En.

See Figure 3. FIG. 3 is a detailed schematic diagram of a signal masking unit 120 according to some embodiments of the present application. As shown in FIG. 3 , in some embodiments, the switch unit T1 has a control terminal and an output terminal. The control terminal is used for receiving the control signal Vin_2, and the output terminal is used for outputting the pulse signal CLK. The reset unit RST1 is electrically connected to the control terminal and the output terminal, respectively, to selectively output the operating voltage VDD to the control terminal and the output terminal of the switch unit T1 according to the control signal Vin_1 .

As shown in FIG. 3 , in some embodiments, the reset unit RST1 includes a switch unit T4 , a switch unit T5 , a switch unit T6 and a capacitor C1 . The switch unit T4 is used for receiving the reset voltage Vrst. The switch unit T5 is used for receiving the reset voltage Vrst. The control terminal of the switch unit T5 is used for receiving the control signal Vin_1 and is electrically connected to the switch unit T4 to receive the reset voltage Vrst. The switch unit T6 receives the reset voltage Vrst, the switch unit T6 has a control terminal and an output terminal, the control terminal of the switch unit T6 is electrically connected to the control terminal of the switch unit T5, and the output terminal of the switch unit T6 is electrically connected to the output terminal of the switch unit T1. sexual connection. The capacitor C1 is electrically connected to the control terminal of the switch unit T5 for receiving the reset voltage Vrst.

In some embodiments, when the reset voltage Vrst and the control signal Vin_1 turn on the switch unit T4 , the switch unit T5 and the switch unit T6 , the operating voltage VDD is turned on to the control terminal and the output terminal of the switch unit T1 to enable the switch unit The control terminal and the output terminal of T1 have a first voltage level.

As shown in FIG. 3 , in some embodiments, the switch units T1 - T6 are P-type metal oxide semiconductor field effect transistors (PMOS). However, this case is not limited to the embodiment of FIG. 3 .

See Figure 4. FIG. 4 is a schematic diagram of an operation waveform 400 according to some embodiments of the present application. As shown in FIG. 4 , during periods P1 to P6 , the control signal Vin_1 is at a high voltage level, and the control signal Vin_2 is at a low voltage level. Details of FIG. 4 will be described below with reference to FIGS. 5 to 10 .

See Figure 5. FIG. 5 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present invention. Please refer to Figure 4 and Figure 5 together. During the period P1, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. When the reset voltage Vrst is at a low voltage level, the switch unit T4 is turned on, so that the node Q is at a low voltage level, and both the switch unit T5 and the switch unit T6 are turned on. Since the switch unit T5 and the switch unit T6 are both turned on, the operating voltage VDD is supplied to the node BT and the output terminal OUT through the switch unit T5 and the switch unit T6. At this time, the node BT is at a high voltage level, so the switch unit T1 is not turned on. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN, and the scan line voltage G[n] is at a high voltage level, so one of the plurality of scan lines G1 ˜GN The active region 130 coupled to one of the plurality of scan lines G1 ˜GN is not updated.

See Figure 6. FIG. 6 is a schematic diagram of the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present invention. Please refer to Figure 4 and Figure 6 together. During the period P2, the driving signal En is at a low voltage level, so the switch unit T2 and the switch unit T3 are both turned on. The control signal Vin_1 of the high voltage level is supplied to the node Q through the switch unit T2, so the node Q is at the high voltage level. The control signal Vin_2 of the low voltage level is supplied to the node BT through the switch unit T3, so the node BT is at the low voltage level. The reset voltage Vrst is a high voltage level, so the switch unit T4 is not turned on. Since the node Q is at a high voltage level and the node BT is at a low voltage level, the switch unit T5 and the switch unit T6 are not turned on, while the switch unit T1 is turned on, and the signal mask unit 120 outputs the pulse signal CLK to the plurality of scan lines One of G1 to GN. At this time, the pulse signal CLK is at a high voltage level, so one of the plurality of scan lines G1 ˜GN does not update the active region 130 coupled to one of the plurality of scan lines G1 ˜GN.

See Figure 7. FIG. 7 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present invention. Please refer to Figure 4 and Figure 7 together. During the period P3, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is a high voltage level, so the switch unit T4 is not turned on. The working voltage VDD is supplied to the node Q through the capacitor C1, so the node Q is at a high voltage level, so that the switch unit T5 and the switch unit T6 are not turned on. The node BT is at a low voltage level, and the switch unit T1 is turned on. The signal mask unit 120 outputs the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. At this time, the pulse signal CLK is at a low voltage level, so one of the plurality of scan lines G1 ˜GN updates the active region 130 coupled to one of the plurality of scan lines G1 ˜GN.

See Figure 8. FIG. 8 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present invention. Please refer to Figure 4 and Figure 8 together. During the period P4, the driving signal En is at a high voltage level, so both the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is a low voltage level, so the switch unit T4 is turned on. Since the switch unit T4 is turned on, the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switch unit T5, so the node BT is at a high voltage level, so that the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN, and the scan line voltage G[n] is a high voltage level, so one of the plurality of scan lines G1 ˜GN The active region 130 coupled to one of the plurality of scan lines G1 ˜GN is not updated.

See Figure 9. FIG. 9 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present invention. Please refer to Figure 4 and Figure 9 together. During the period P5, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, the node Q is maintained at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on, and the operating voltage VDD is provided to the node BT through the switch unit T5, Therefore node BT is at a high voltage level. The node BT is at a high voltage level, so the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN, and the scan line voltage G[n] is a high voltage level, so one of the plurality of scan lines G1 ˜GN The active region 130 coupled to one of the plurality of scan lines G1 ˜GN is not updated.

See Figure 10. FIG. 10 is a schematic diagram illustrating the operation of a signal mask unit 120 according to the embodiment shown in FIG. 3 of the present application. Please refer to Figure 4 and Figure 10 together. During the period P6, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, and the node Q is maintained at a low voltage level. The node Q is at a low voltage level, so the switch unit T5 and the switch unit T6 are turned on, and the operating voltage VDD is supplied to the node BT through the switch unit T5, so the node BT is at a high voltage level, so that the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. Therefore, even if the pulse signal CLK is at a low voltage level during the period P6, since the signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scanning lines G1 to GN, the scanning line voltage G[n] is high voltage level, so one of the plurality of scan lines G1 ˜GN does not update the active region 130 coupled to one of the plurality of scan lines G1 ˜GN.

See Figure 11. FIG. 11 is a schematic diagram of an operation waveform 500 according to some embodiments of the present application. As shown in FIG. 11 , during periods P7 to P12 , the control signal Vin_1 is at a low voltage level, and the control signal Vin_2 is at a high voltage level. Details of FIG. 11 will be described below in conjunction with FIGS. 12 to 17 .

See Figure 12. FIG. 12 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present application. Please refer to Figure 11 and Figure 12 together. During the period P7, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is at a low voltage level, so the switch unit T4 is turned on, and the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on, and the operating voltage VDD is supplied to the node BT through the switch unit T5, so the node BT is at a high voltage level, so the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN, and the scan line voltage G[n] is at a high voltage level, so one of the plurality of scan lines G1 ˜GN The active region 130 coupled to one of the plurality of scan lines G1 ˜GN is not updated.

See Figure 13. FIG. 13 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present application. Please refer to Figure 11 and Figure 13 together. During the period P8, the driving signal En is at a low voltage level, so the switch unit T2 and the switch unit T3 are both turned on. The reset voltage Vrst is a high voltage level, so the switch unit T4 is not turned on. The control signal Vin_1 of the low voltage level is supplied to the node Q through the switch unit T2, so the node Q is at the low voltage level. The control signal Vin_2 of the high voltage level is supplied to the node BT through the switch unit T3, so the node BT is at the high voltage level. Since the node Q is at a low voltage level and the node BT is at a high voltage level, the switch unit T5 and the switch unit T6 are turned on, but the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. At this time, the scan line voltage G[n] is at a high voltage level, so one of the plurality of scan lines G1 ˜GN does not update the active region 130 coupled to one of the plurality of scan lines G1 ˜GN .

See Figure 14. FIG. 14 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present application. Please refer to Figure 11 and Figure 14 together. During the period P9, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, and the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switch unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. Therefore, even if the pulse signal CLK is at a low voltage level in the period P12, since the signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scanning lines G1-GN, the scanning line voltage G[n] at this time is It is a high voltage level, so one of the plurality of scan lines G1 -GN does not update the active region 130 coupled to one of the plurality of scan lines G1 -GN.

See Figure 15. FIG. 15 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present application. Please refer to Figure 11 and Figure 15 together. During the period P10, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is a low voltage level, so the switch unit T4 is turned on. The reset voltage Vrst is supplied to the node Q through the switch unit T4, so the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switch unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. At this time, the scan line voltage G[n] is at a high voltage level, so one of the plurality of scan lines G1 ˜GN does not update the active region 130 coupled to one of the plurality of scan lines G1 ˜GN .

See Figure 16. FIG. 16 is a schematic diagram illustrating the operation of a signal mask unit 120 according to the embodiment shown in FIG. 3 of the present application. Please refer to Figure 11 and Figure 16 together. During the period P11, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, and the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switch unit T5, so the node BT is at a high voltage level, so that the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. At this time, the scan line voltage G[n] is at a high voltage level, so one of the plurality of scan lines G1 ˜GN does not update the active region 130 coupled to one of the plurality of scan lines G1 ˜GN .

See Figure 17. FIG. 17 is a schematic diagram illustrating the operation of a signal masking unit 120 according to the embodiment shown in FIG. 3 of the present application. Please refer to Figure 11 and Figure 17 together. During the period P12, the driving signal En is at a high voltage level, so the switch unit T2 and the switch unit T3 are not turned on. The reset voltage Vrst is at a high voltage level, so the switch unit T4 is not turned on, and the node Q is at a low voltage level, so that the switch unit T5 and the switch unit T6 are turned on. The operating voltage VDD is supplied to the node BT through the switch unit T5, so the node BT is at a high voltage level. The node BT is at a high voltage level, so the switch unit T1 is not turned on. The working voltage VDD is supplied to the output terminal OUT through the switch unit T6, so the output terminal OUT is at a high voltage level. The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. Therefore, even if the pulse signal CLK is at a low voltage level in the period P12, since the signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scanning lines G1-GN, the scanning line voltage G[n] at this time is It is a high voltage level, so one of the plurality of scan lines G1 -GN does not update the active region 130 coupled to one of the plurality of scan lines G1 -GN.

See Figure 18. FIG. 18 is a flowchart of a signal masking method 600 according to some embodiments of the present application. As shown in FIG. 18, the signal masking method 600 includes the following steps:

Step S610: enabling the driving circuit to receive the first control signal and the second control signal according to the driving signal;

Step S620: enabling the driving circuit to receive the pulse signal;

Step S630: when the first control signal is at the first voltage level and the second control signal is at the second voltage level, enabling the driving circuit to output a pulse signal;

Step S640: when the first control signal is at the second voltage level and the second control signal is at the first voltage level, make the driving circuit stop outputting the pulse signal; and

Step S650: Enable the drive circuit to selectively receive the reset voltage according to the reset voltage and the first control signal, wherein the reset voltage has a second voltage level, and the reset voltage causes the drive circuit to stop outputting the pulse signal.

To make the signal masking method 600 of the embodiment of the present invention easy to understand, please refer to FIGS. 3 to 18 together.

In step S610, the driving circuit is made to receive the first control signal and the second control signal according to the driving signal. In some embodiments, the driving circuit may be the signal mask unit 120 as shown in FIG. 3 . For example, in some embodiments, when the driving signal En is at a low voltage level, the switch unit T2 and the switch unit T3 are turned on, and the signal mask unit 120 receives the control signal Vin_1 and the control signal Vin_2 .

In step S620, the driving circuit is made to receive the pulse signal. In some embodiments, the pulse signal CLK is received by the switch unit T1 of the signal mask unit 120 .

In step S630, when the first control signal is at the first voltage level and the second control signal is at the second voltage level, the driving circuit is made to output a pulse signal. For example, as shown in FIG. 7 , at this time, the control signal Vin_1 is at a high voltage level, and the control signal Vin_2 is at a low voltage level. The node Q is at a high voltage level, so the switch unit T5 and the switch unit T6 are not turned on. The node BT is at a low voltage level, and the switch unit T1 is turned on. The signal mask unit 120 outputs the pulse signal CLK to one of the plurality of scan lines G1 ˜GN. At this time, the pulse signal CLK is at a low voltage level, so one of the plurality of scan lines G1 ˜GN updates the active region 130 coupled to one of the plurality of scan lines G1 ˜GN.

In step S640, when the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops outputting the pulse signal. For example, as shown in FIG. 12 to FIG. 17 , in FIG. 12 to FIG. 17 , the control signal Vin_1 is at a low voltage level, the control signal Vin_2 is at a high voltage level, and the switch unit T1 is not turned on, so The signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN.

In step S650, the driving circuit is made to selectively receive the reset voltage according to the reset voltage and the first control signal, wherein the reset voltage has a second voltage level, and the reset voltage causes the driving circuit to stop outputting the pulse signal. For example, referring to FIG. 8 , when the reset voltage Vrst is at a low voltage level, the switch unit T4 is turned on, and the node Q is at a low voltage level at this time, and the switch unit T5 and the switch unit T6 are turned on. At this time, the node BT is at a high voltage level, and the switch unit T1 is not turned on, so the signal mask unit 120 does not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN.

In some embodiments, the driving signal En is generated by the signal generator 110 as shown in FIG. 1 and input to the signal mask unit 120 . In some other embodiments, the driving signal En is generated by the signal masking unit 120 of the previous stage in the display panel 100 and input to the signal masking unit 120 of the current stage.

In some embodiments, the reset voltage Vrst and the pulse signal CLK shown in FIG. 4 and FIG. 11 change periodically.

As shown in FIGS. 4 to 17 , when the control signal Vin_1 is at a high voltage level and the control signal Vin_2 is at a low voltage level, the signal mask unit 120 outputs the pulse signal CLK to one of the plurality of scan lines G1 ˜GN . On the other hand, if the pulse signal CLK is at a low voltage level, the scanning line voltage G[n] is at a low voltage level, so one of the plurality of scanning lines G1 to GN is updated to be in phase with one of the plurality of scanning lines G1 to GN. The active region 130 is coupled. On the other hand, when the control signal Vin_1 is at a low voltage level and the control signal Vin_2 is at a high voltage level, the signal mask unit 120 will not output the pulse signal CLK to one of the plurality of scan lines G1 ˜GN, so One of the plurality of scan lines G1 ˜GN does not update the active region 130 coupled to one of the plurality of scan lines G1 ˜GN. In the above manner, the embodiment of the present application can control the control signal Vin_1 and the control signal Vin_2 so that the display panel 100 only needs to update the part of the active area 130 that needs to be updated, so as to reduce the power consumption of the display panel 100 .

It can be known from the above embodiments of the present case that the embodiments of the present case provide a signal masking unit, a signal masking method, and a display panel, and particularly relate to a signal masking unit with low power consumption, a signal masking method and a display panel. The display panel can effectively reduce the power consumption of the display device without reducing the performance of the display device.

In addition, the above illustrations include sequential exemplary steps, but the steps do not have to be performed in the order shown. It is within the scope of this disclosure to perform the steps in a different order. The multiple steps may be added, replaced, changed in order and/or omitted as appropriate within the spirit and scope of the embodiments of the present disclosure.

Although this case has been disclosed above in terms of implementation, it is not intended to limit this case. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of this case. Therefore, the protection scope of this case should be limited to The appended claims shall control.

Claims (8)

1. A signal masking unit, comprising: a reset unit for receiving a reset voltage and receiving a first control signal according to a driving signal; and a first switch unit, electrically connected to the reset unit, for receiving a pulse signal and receiving a second control signal according to the driving signal, wherein the second control signal is inverse to the first control signal; When the first control signal is at a first voltage level and the second control signal is at a second voltage level, the reset unit does not work, and the second control signal turns on the first switch unit to make the the first switch unit outputs the pulse signal; When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs a working voltage to the first switch unit, the working voltage and the second The control signal turns off the first switch unit. 2. The signal mask unit of claim 1, further comprising: A second switch unit is electrically connected to the reset unit for receiving the first control signal and conducting the first control signal to the reset unit according to the driving signal. 3. The signal mask unit of claim 1, further comprising: A third switch unit is electrically connected to the first switch unit for receiving the second control signal and conducting the second control signal to the first switch unit according to the driving signal. 4. The signal mask unit of claim 1, wherein the first switch unit has a control terminal and an output terminal, the control terminal is used for receiving the second control signal, and the output terminal is used for outputting the pulse signal , the reset unit is respectively electrically connected with the control terminal and the output terminal to selectively output the working voltage to the control terminal and the output terminal according to the first control signal. 5. The signal mask unit of claim 4, wherein the reset unit comprises: a fourth switch unit for receiving the reset voltage; a fifth switch unit for receiving the working voltage, the fifth switch unit has a control terminal, wherein the control terminal of the fifth switch unit is used for receiving the first control signal and electrically connected with the fourth switch unit connect; a sixth switch unit for receiving the operating voltage, the sixth switch unit has a control terminal and an output terminal, wherein the control terminal of the sixth switch unit is electrically connected to the control terminal of the fifth switch unit , the output terminal of the sixth switch unit is electrically connected to the output terminal of the first switch unit; and A capacitor is electrically connected to the control terminal of the fifth switch unit. 6 . The signal mask unit of claim 5 , wherein when the reset voltage and the first control signal turn on the fourth switch unit, the fifth switch unit and the sixth switch unit, the operating voltage Being turned on to the control terminal and the output terminal of the first switch unit causes the control terminal and the output terminal of the first switch unit to have the first voltage level. 7. A signal masking method for a driving circuit, comprising: enabling the driving circuit to receive a first control signal and a second control signal according to a driving signal; causing the drive circuit to receive a pulse signal; When the first control signal is at a first voltage level and the second control signal is at a second voltage level, enabling the driving circuit to output the pulse signal; and When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the driving circuit stops outputting the pulse signal, Also contains: The driving circuit is made to selectively receive a working voltage according to a reset voltage and the first control signal, wherein the working voltage has the second voltage level, and the working voltage causes the driving circuit to stop outputting the pulse signal. 8. A display panel comprising: multiple scan lines; a multi-stage signal generator, wherein the signal generator of each stage generates a driving signal respectively, and transmits the driving signal to the next-stage signal generator; A multi-level signal masking unit is respectively coupled between one of the plurality of scan lines and one level of the plurality of signal generators, and the plurality of signal masking units of each level are coupled according to the When the driving signal transmitted by the stage signal generator receives a first control signal and a second control signal, wherein the second control signal and the first control signal are inverted, and when the first control signal is in a first control signal When a voltage level and the second control signal is at a second voltage level, when the stage signal mask unit sends a pulse signal to one of the plurality of scan lines, Wherein the plurality of signal mask units at each stage include: a reset unit for receiving a reset voltage and receiving the first control signal according to the driving signal sent by the signal generator; and a first switch unit electrically connected to the reset unit and one of the plurality of scan lines, the first switch unit receives the second control signal according to the driving signal transmitted by the signal generator, when the When the first switch unit is turned on, it is used for sending the pulse signal to one of the plurality of scan lines; When the first control signal is at the second voltage level and the second control signal is at the first voltage level, the reset unit outputs a working voltage to the first switch unit, the working voltage and the second The control signal turns off the first switch unit.

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