CN107634009A - A kind of GaN MOS HEMT devices and preparation method thereof - Google Patents

Abstract

The invention discloses a GaN MOS-HEMT device and a preparation method thereof. The method comprises: depositing a silicon nitride dielectric layer on a GaN epitaxial wafer to protect the surface of the material; etching to form a gate window; forming a gate window on the surface of the silicon nitride dielectric layer and Deposit polysilicon layer in gate window; oxidize polysilicon layer to _SiO2 gate dielectric layer; etch to form ohmic contact hole; deposit ohmic metal and form source and drain electrodes; deposit gate electrode metal and form gate electrode; surface protection and opening Electrode (PAD) window. The preparation process and conditions of the present invention are compatible with the Si CMOS process, the process is simple, the operability is strong, the contradiction between device performance and process complexity is well coordinated, and the mass production of GaN MOS-HEMT devices is provided. Possibility; the gate dielectric layer of the present invention is made of _SiO2 thin film, which has good compactness and less trapped charges, which can not only reduce the gate leakage current of GaN devices, but also make GaN devices have better dynamic characteristics, which can significantly improve the performance of devices. performance and stability.

Description

A kind of GaN MOS-HEMT device and its preparation method

technical field

The invention relates to the technical field of semiconductors, in particular to a GaN MOS-HEMT device and a preparation method thereof.

Background technique

GaN and GaN system materials are representative of the third-generation wide bandgap semiconductor materials because of their large bandgap width (3.4eV), high electron saturation rate (2×10 ⁷ cm/s), and high breakdown electric field (1× 10 ¹⁰ -3×10 ¹⁰ V/cm), high thermal conductivity, excellent corrosion resistance and radiation resistance, etc., are considered to be the best materials for researching short-wave optoelectronic devices and high-voltage, high-frequency and high-power devices. GaN/AlGaN heterostructure is one of the most attractive device structures, because of the strong spontaneous polarization and piezoelectric polarization effects between GaN and AlGaN, resulting in high electron concentration and high electron migration between GaN/AlGaN High-rate two-dimensional electron gas (2-DEG), the electron concentration is as high as 10 ¹² -10 ¹³ cm ^-2 , and the electron mobility can be as high as 2000cm ² /V; this makes GaN/AlGaN high electron mobility transistor (HEMT) a nitride The most important device type in the field of gallium devices is equivalent to the status of MOSFETs in Si devices.

Because of the inherent lattice mismatch defect of the GaN/AlGaN heterostructure, the crystal epitaxy quality is poor, and the device has a serious gate leakage current. This feature makes the device based on the GaN/AlGaN heterostructure unable to exert its maximum potential. Advantage. To solve this problem, the currently commonly used solution is to design a HEMT with MIS (nitride) or MOS (oxide) structure, that is, to grow a dense dielectric layer on the surface of the AlGaN epitaxial material. On the one hand, it solves the problem very well. The problem of large gate leakage current; on the other hand, a good dielectric layer can significantly improve the current collapse effect that is common in HEMT devices. The design for MIS or MOS is mainly divided into two camps. The first category is to use oxide as the gate dielectric layer, for example, grow a dielectric material with dense breakdown characteristics and a large dielectric constant by ALD, such as Al ₂ O ₃ , Hf ₂ O ₃ , etc., this solution can obtain first-class device characteristics, but it is highly experimental and difficult to mass produce; the second type uses nitride as the gate dielectric layer, and most of them are based on platforms compatible with Si processes. This scheme generally uses LPCVD to grow nitride (for example) Si ₃ N ₄ which is similar to the material of the GaN device epitaxial wafer as the dielectric layer, but the static and dynamic characteristics of the device manufactured by this scheme are not as good as the results of the first category. . Based on the above contradictions, the industry and academia urgently need to find a preparation scheme for MIS or MOS HEMT that can combine their respective advantages.

Contents of the invention

The present application provides a GaN MOS-HEMT device and a preparation method thereof, which are used to solve the problem of large gate leakage current of GaN HEMT devices in the prior art.

In order to solve the above problems, the technical scheme of the present invention is as follows:

A method for preparing a GaN MOS-HEMT device, comprising:

Prepare GaN epitaxial wafer;

Forming a _SiO2 gate dielectric layer on the upper surface of the GaN epitaxial wafer;

Etching the SiO ₂ gate dielectric layer to the outer surface of the GaN epitaxial wafer or inside the GaN epitaxial wafer to form an ohmic contact hole;

depositing ohmic metal in the ohmic contact hole;

Ohmic metal patterning and high temperature annealing to form source and drain electrodes;

Make a gate electrode on the area where the gate is preset to be formed on the SiO ₂ gate dielectric layer.

A GaN MOS-HEMT device comprising:

GaN epitaxial wafer;

isolation distribution to realize electrically insulated gate electrode, source electrode and drain electrode, the source electrode and drain electrode are respectively formed on the upper surface of the GaN epitaxial wafer;

A _SiO2 gate dielectric layer is formed on the upper surface of the GaN epitaxial wafer, between the gate electrode, the source electrode and the drain electrode.

It also includes a silicon nitride dielectric layer formed between the upper surface of the GaN epitaxial wafer and the _SiO2 gate dielectric layer, a gate window is formed on the silicon nitride dielectric layer corresponding to the gate electrode, and the _SiO2 gate dielectric layer is made of silicon nitride The dielectric layer extends to the inside of the gate window through the gate window to be in contact with the GaN epitaxial wafer;

The gate electrode is located on the upper surface of the _SiO2 gate dielectric layer.

The beneficial effects of the present invention are:

The present invention proposes a GaN MOS-HEMT device and its preparation method. The focus of the preparation method is to use dense _SiO2 formed by thermal oxidation as the gate dielectric layer of the GaN HEMT device to solve the large gate leakage current and current collapse effect Serious problem; this method first deposits a polysilicon layer on the gate, and then oxidizes the polysilicon layer into a dense _SiO2 film through high-temperature oxidation, which is used as a gate dielectric layer; the GaN MOS-HEMT device prepared by the oxidation process of polysilicon, The SiO ₂ thin film has good film quality and uniform film formation, which improves the static and dynamic characteristics of GaN HEMT devices; at the same time, the preparation method of the present invention is compatible with the existing Si CMOS process platform, and is very suitable for mass production of GaN MOS-HEMT.

Description of drawings

FIG. 1 is a schematic flow chart corresponding to a GaN MOS-HEMT device manufacturing method provided by an embodiment of the present invention;

2 to 9 are schematic diagrams of the device structure during the preparation process of a GaN MOS-HEMT device provided by an embodiment of the present invention.

In the figure, 101-silicon substrate, 102-GaN buffer layer, 103-two-dimensional electron gas thin layer, 104-AlGaN barrier layer, 105-GaN cap layer, 106-silicon nitride dielectric layer, 107- _SiO2 gate Dielectric layer, 108-protective layer, 109-polysilicon layer.

detailed description

In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

At present, most of the institutions and enterprises related to GaN device research use the existing 4-8inch Si CMOS process platform as the process basis for GaN HEMT device research and development, so as to develop Si CMOS compatible GaN HEMT process. This can not only save the time of platform construction and adjustment, but also greatly save R&D costs. But the static and dynamic characteristics of GaNHEMT devices fabricated on this platform are poor. During the research, it was found that due to the characteristics of the LPCVD deposition method itself, there are a large amount of mobile charges in the gate dielectric layer, which leads to the deterioration of the static and dynamic characteristics of GaN HEMT devices. If the movable charges in the gate dielectric layer are reduced, the static and dynamic characteristics of GaN HEMT devices can be improved to a certain extent. Therefore, the inventor thought of using thermally oxidized SiO ₂ as the gate dielectric layer. Due to its own characteristics, SiO ₂ formed by thermal oxidation has less movable charges. Therefore, using SiO ₂ as the gate dielectric layer can not only reduce the gate leakage current of GaN devices, but also make GaN devices have better dynamic characteristics.

In the process of perfecting the embodiment, the inventor found that if the _SiO2 layer is directly grown on the GaN epitaxial wafer, only PECVD and LPCVD can be used at present, and the formed _SiO2 layer will have more pores and be more brittle. It is not conducive to the formation of a good gate dielectric layer. Therefore, the inventor first grows a polysilicon layer at the position of the gate dielectric layer, and then oxidizes the polysilicon layer at high temperature to form an SiO ₂ layer.

In addition, if the polysilicon layer is directly grown on the GaN epitaxial wafer, the subsequent high temperature will cause damage to the surface of the GaN epitaxial wafer, so in the improved embodiment, a silicon nitride dielectric layer is first formed on the cap layer of the GaN epitaxial wafer, Then a gate window is opened on the silicon nitride dielectric layer, and finally a polysilicon layer is grown on the silicon nitride dielectric layer and in the gate window.

Example 1:

Referring to Fig. 1, a preparation method of a GaN MOS-HEMT device,

Step 201. First prepare the GaN epitaxial wafer: the structure of the GaN epitaxial wafer 201 is shown in FIG. 2 , and a GaN buffer layer 102 (GaN buffer layer), an AlGaN barrier layer 104 ( AlGaN barrier layer), GaN cap layer 105 (GaN cap layer), GaN cap layer 105 (GaN cap layer) as the upper surface of the GaN epitaxial wafer; GaN buffer layer 102 (GaN buffer layer) and AlGaN barrier layer 104 (AlGaN barrier layer ) to form a two-dimensional electron gas thin layer 103 (2-DEG). The GaN cap layer 105 (GaN cap layer) is used to passivate the material surface, which can significantly suppress the current collapse effect and reduce surface leakage. GaN epitaxial wafers can be used to manufacture GaN devices, or can be formed on ordinary silicon wafers through appropriate processes.

Clean the GaN epitaxial wafer. After cleaning, the following steps are specifically included:

Step 202. Deposit a silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) with a thickness of 30 nm on the GaN cap layer 105 (GaN cap layer) by LPCVD (low pressure chemical vapor deposition), see FIG. 2 . In another embodiment, the thickness of the deposited silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) can also be adjusted as required.

Step 203. Etching the gate window on the silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) by using RIE process (reactive ion etching method), and etching the gate window to the upper surface of the GaN epitaxial wafer , see Figure 3. In another embodiment, the etching depth of the gate window can also reach the inside of the GaN epitaxial wafer, for example, the etching depth reaches the inside of the AlGaN barrier layer 104 (AlGaN barrier layer) or removes all the AlGaN barrier layer 104 (AlGaN barrier layer). barrier layer) reaches the upper surface of the GaN buffer layer 102 (GaN buffer layer).

Step 204. Deposit a polysilicon layer 109 (Poly Si) on the Si ₃ N ₄ dielectric layer 106 etched with a gate window by using LPCVD (low pressure chemical vapor deposition), and the polysilicon layer 109 (Poly Si) is obtained by It is formed by thermal decomposition of SiH ₄ at ambient temperature, see Figure 4.

Step 205. Oxidize the polysilicon layer 109 (Poly Si) in an atmosphere of O ₂ :H ₂ =1:1 at 750° C. for 1 hour until it is completely oxidized into the SiO ₂ gate dielectric layer 107 , see FIG. 5 . The SiO ₂ thin film formed at high temperature has good compactness, small internal charge trap density, and few film pores, and is very suitable as a gate dielectric layer; the SiO ₂ gate dielectric layer 107 can greatly improve the gate control capability of the device and reduce the leakage of the gate Channel, enhance the stability and repeatability of the gate; in addition, because of the small trap charge, the dynamic resistance of the device will be greatly reduced, and the current collapse effect will be suppressed.

In addition, those skilled in the art should understand that in other embodiments, the oxidation process conditions of the polysilicon layer 109 (Poly Si) can also be adjusted as required, such as adjusting the oxygen content, oxidation temperature or oxidation time, for example, at 700°C- Oxidation at 800°C for 45-75 minutes, in short, as long as the polysilicon is completely oxidized to SiO ₂ .

Step 206. Use RIE process (reactive ion etching method) to etch to form an ohmic contact hole, and the etching stops on the GaN cap layer 105 (GaN cap layer), see FIG. 6; in another embodiment, the ohmic contact hole The etching can also stop inside the AlGaN barrier layer 104 (AlGaN barrier layer) or completely remove the AlGaN barrier layer 104 (AlGaN barrier layer);

Step 207. HF cleans the ohmic contact hole, and uses magnetron sputtering to deposit ohmic contact metal in the ohmic contact hole to form source and drain electrodes (S level, D level). The structure of the ohmic contact metal is Ti/Al/Ti/TiN , and the thicknesses are 200A/1200A/200A/200A, respectively, see Figure 7.

Step 208. Deposit gate metal on the _SiO2 gate dielectric layer 107 by magnetron sputtering, the structure of the gate metal is TiN/Ti/Al, and the thickness is 300A/200A/3000A respectively, and then photoetching the gate metal to form the gate electrode (G level), the gate electrode (G level) is located on the upper surface of the SiO ₂ gate dielectric layer 107, facing the gate window opened on the silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation), see FIG. 8 .

Step 209. Surface protection, sequentially deposit TEOS/Si ₃ N ₄ /TEOS as the protective layer 108 by plasma enhanced chemical vapor deposition method, the thicknesses are respectively 6000A/3000A/2000A, and the protective layer 108 is etched by yellow photolithography to form via contact holes , open the metal PAD for device interconnection and testing, see Figure 9.

In some embodiments, step 202 can also be omitted, and the _SiO2 gate dielectric layer is directly formed on the epitaxial wafer of the GaN device, but compared with the solution of omitting step 202 in this embodiment, the silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) can play the role of passivation and protection, and is mainly used to eliminate the surface state of the material, reduce surface damage, and improve the stability and reliability of the device.

After the above process, a complete GaN MOS-HEMT based on polysilicon oxidation as the gate dielectric layer is fabricated, and multi-layer wiring can be performed later as required. From the above process description, it can be seen that the process and conditions used in the entire device manufacturing process are compatible with the Si CMOS process platform, and the process complexity is low, the operability is strong, and the device performance and process are well coordinated. The contradiction between complexity. Therefore, the preparation method of GaN MOS-HEMT proposed in this patent provides a basis and reference for the design of GaN HEMT mass production scheme.

Example 2:

Different from Example 1, in this example:

In step 204 , the polysilicon layer 109 (Poly Si) is oxidized in an atmosphere of O ₂ :H ₂ =1:1 at 800° C. for 45 minutes until it is completely oxidized into a SiO ₂ film.

The structure of the transistor device manufactured by the above-mentioned manufacturing method of Embodiment 1 is shown in FIG. 9 .

The GaN MOS-HEMT device at least includes: a GaN epitaxial wafer; a gate electrode (G level), a source electrode (S level) and a drain electrode (D level) that are isolated and distributed to achieve electrical insulation, and the source electrode (S level) and The drain electrodes (level D) are respectively formed on the upper surface of the GaN epitaxial wafer; at the same time, the _SiO2 gate dielectric is formed between the upper surface of the GaN epitaxial wafer, the gate electrode (G level), the source electrode (S level) and the drain electrode (D level) Layer 107; the gate electrode (level G) is located on the upper surface of the SiO ₂ gate dielectric layer 107 .

Preferably, it also includes a silicon nitride dielectric layer 106 (Si _{3 N 4 Passivation) formed between the upper surface of the GaN epitaxial wafer and the SiO 2 gate dielectric layer 107, the thickness of the silicon nitride dielectric layer 106 (Si 3 N 4 Passivation )} The range is 30nm-35nm, a gate window is formed on the silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) corresponding to the position of the gate electrode (G level), and the depth of the gate window reaches the upper surface of the GaN epitaxial wafer, SiO ₂ The gate dielectric layer 107 extends from the silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) through the gate window to the inside of the gate window, so as to be in contact with the GaN epitaxial wafer.

It should be noted that, in other embodiments, the depth of the gate window can be etched to the inside of the GaN epitaxial wafer.

Preferably, the GaN epitaxial wafer includes a silicon substrate 101 (Silicon substrate), a GaN buffer layer 102 (GaN buffer layer), an AlGaN barrier layer 104 (AlGaN barrier layer) and a GaN cap formed sequentially on the silicon substrate 101 layer 105 (GaN cap layer), the GaN cap layer 105 (GaN cap layer) is used as the upper surface of the GaN epitaxial wafer, and a two-dimensional The thin electron gas layer (2-DEG), the SiO ₂ gate dielectric layer 107 extends from the silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) through the gate window to the upper surface of the GaN epitaxial wafer.

In other embodiments, the SiO ₂ gate dielectric layer 107 may also extend from the silicon nitride dielectric layer 106 (Si ₃ N ₄ Passivation) through the gate window to the inside of the GaN cap layer 105 (GaN cap layer) or the AlGaN barrier layer 104 (AlGaN barrier layer) or the upper surface of the GaN buffer layer 102 (GaN buffer layer).

Preferably, it also includes a protective layer 108 deposited on the gate electrode (G level) and the source and drain electrodes (S level, D level). The structure of the protective layer 108 is TEOS/Si ₃ N ₄ /TEOS in sequence. Contact holes (VIA) for exposing the gate electrode (G level) and source and drain electrodes (S level, D level) are formed on the upper surface by etching.

Preferably, the structure of the source-drain electrodes (S-level, D-level) is Ti/Al/Ti/TiN, and the thicknesses are 200A/1200A/200A/200A, respectively.

Preferably, the structure of the gate electrode (level G) is TiN/Ti/Al, and the thicknesses are 300A/200A/3000A, respectively.

Preferably, the structure of the protective layer 108 is TEOS/Si ₃ N ₄ /TEOS, and the thicknesses are 6000A/3000A/2000A, respectively.

The above uses specific examples to illustrate the present invention, which is only used to help understand the present invention, and is not intended to limit the present invention. For those skilled in the technical field to which the present invention belongs, some simple deduction, deformation or replacement can also be made according to the idea of the present invention.

Claims (10)

1. A method for preparing a GaN MOS-HEMT device, characterized in that, comprising: Prepare GaN epitaxial wafer; Forming a _SiO2 gate dielectric layer on the upper surface of the GaN epitaxial wafer; Etching the SiO ₂ gate dielectric layer to the outer surface of the GaN epitaxial wafer or inside the GaN epitaxial wafer to form an ohmic contact hole; depositing ohmic metal in the ohmic contact hole; Ohmic metal patterning and high temperature annealing to form source and drain electrodes; Make a gate electrode on the area where the gate is preset to be formed on the SiO ₂ gate dielectric layer. 2. The method according to claim 1, characterized in that the _SiO2 gate dielectric layer is formed by oxidation of a polysilicon layer. 3. The method according to claim 2, characterized in that before forming the SiO ₂ gate dielectric layer, a silicon nitride dielectric layer is also formed on the upper surface of the GaN epitaxial wafer. 4. The method according to claim 3, wherein forming a _SiO2 gate dielectric layer on the upper surface of the GaN epitaxial wafer comprises: Etching the silicon nitride dielectric layer to the surface of the GaN epitaxial wafer or the inside of the GaN epitaxial wafer to form a gate window in the area where the gate is preset to be formed; Depositing a polysilicon layer on the surface of the silicon nitride dielectric layer and in the gate window by LPCVD process; Oxidize the polysilicon layer at high temperature to oxidize the polysilicon layer into a SiO ₂ film to form a SiO ₂ gate dielectric layer. 5 . The method according to claim 4 , wherein the high-temperature oxidation of the polysilicon layer means that the polysilicon layer is completely oxidized into a SiO ₂ film under O ₂ , H ₂ atmosphere and high temperature environment. 6. The method according to claim 4, wherein the GaN epitaxial wafer comprises a substrate, a buffer layer, a barrier layer and a cap layer sequentially formed on the substrate, and the cap layer is used as the upper surface of the GaN epitaxial wafer Etching the silicon nitride dielectric layer to the upper surface of the GaN epitaxial wafer or the inside of the GaN epitaxial wafer refers to etching the silicon nitride dielectric layer to the upper surface of the cap layer or the inside of the cap layer or the inside of the barrier layer or completely etch Drop the barrier layer. 7. The method according to claim 1, further comprising: depositing a protective layer on the surface of the device after forming the gate electrode, and forming contact holes exposing the gate electrode and source-drain electrodes on the protective layer by etching. 8. A GaN MOS-HEMT device, characterized in that it comprises: GaN epitaxial wafer; isolation distribution to realize electrically insulated gate electrode, source electrode and drain electrode, the source electrode and drain electrode are respectively formed on the upper surface of the GaN epitaxial wafer; A _SiO2 gate dielectric layer is formed on the upper surface of the GaN epitaxial wafer, between the gate electrode, the source electrode and the drain electrode. It also includes a silicon nitride dielectric layer formed between the upper surface of the GaN epitaxial wafer and the _SiO2 gate dielectric layer, a gate window is formed on the silicon nitride dielectric layer corresponding to the gate electrode, and the _SiO2 gate dielectric layer is made of silicon nitride The dielectric layer extends to the inside of the gate window through the gate window to be in contact with the GaN epitaxial wafer; The gate electrode is located on the upper surface of the _SiO2 gate dielectric layer. 9. GaN MOS-HEMT device according to claim 8, is characterized in that, described GaN device GaN epitaxial wafer comprises substrate, the buffer layer that is formed on substrate successively, potential barrier layer and cap layer, and cap layer serves as On the upper surface of the GaN epitaxial wafer, a two-dimensional electron gas thin layer is formed between the buffer layer and the barrier layer, and the _SiO2 gate dielectric layer extends from the silicon nitride dielectric layer through the gate window to the upper surface of the cap layer or inside the cap layer or The interior of the barrier layer or the upper surface of the buffer layer. 10. The GaN MOS-HEMT device according to claim 9, further comprising a protective layer deposited on the gate electrode and the source-drain electrode, on the protective layer an etching method is used to form the gate electrode and the source electrode. Contact hole for the drain electrode.