CN107590089B - Control method of PCI-E channel by basic input and output system - Google Patents

Abstract

A method for controlling a PCI-E channel by a basic input and output system comprises the following steps: the basic input and output system obtains information on whether a first expansion card and a second expansion card are respectively inserted into a first PCI-E slot and a second PCI-E slot; and if the second expansion card is inserted into the second PCI-E slot, the basic input and output system instructs a central processing unit to reverse the order of the PCI-E channels electrically connected to the second PCI-E slot.

Description

Control method of PCI-E channel by basic input and output system

technical field

The invention relates to a control method, and in particular to a control method of a PCI-E channel by a basic input output system.

Background technique

The PCI-E interface is a commonly used interface for external expansion interface cards in computers. This technology was originally designed to transmit data at high speed. Among them, the PCI-E interface provides each device with its own dedicated bus. Data is transmitted serially in the form of packets through the sending and receiving signals called lanes, and each lane of the third-generation PCI-E interface has a unidirectional speed of 8 Gigabits/sec. Multiple channels can be combined to form x1, x2, x4, x8, x12, x16, or even x32 channel bandwidths.

In general, high-end computers usually have two or more PCI-E slots. The basic input output system (BIOS) in the computer will detect which PCI-E slot is inserted with the PCI-E expansion card, and instruct the central processing unit (CPU) how to allocate the PCI-E channel to the first PCI-E according to the detection result. The E slot (usually the PCI-E slot near the central processing unit) and the second PCI-E slot (usually the PCI-E slot farther from the central processing unit).

More specifically, FIG. 1 and FIG. 2 are schematic diagrams showing that the PCI-E channels of the conventional central processing unit are allocated to two PCI-E slots. Please refer to FIG. 1 and FIG. 2, since the PCI-E channel is formed by the first PCI-E pin group in each PCI-E slot (that is, the first PCI-E slot 11 in FIG. 1 and FIG. 2 is the most The first PCI-E pin group 21 on the left and the second PCI-E pin group 22) on the leftmost side of the second PCI-E slot 12 begin to be allocated to the right. In the existing control method, as far as the central processing unit 10 supports x16 PCI-E channels (for example, 16 PCI-E channels numbered 00-15), the 8 PCI-E channels numbered 00-07 The E channel is formed between the first eight processor pin groups 20 of the central processing unit 10 and the first eight first PCI-E pin groups 21 of the first PCI-E slot 11 . The 8 PCI-E channels numbered 08-15 will be switched to the first PCI-E pin group 21 or the second PCI in the second half of the first PCI-E slot 11 depending on the insertion status of the expansion card - The second PCI-E pin group 22 in the front half of the E slot 12 .

Therefore, if only the first PCI-E slot 11 has an expansion card inserted, the BIOS 50 will instruct the central processing unit 10 to switch the eight PCI-E channels numbered 08-15 to the first PCI-E The first PCI-E pin group 21 of the slot 11 . That is, the 1st to 16th first PCI-E pin groups 21 of the first PCI-E slot 11 will be sequentially assigned to the 16 PCI-E channels numbered 00-15, as shown in FIG. 1 . Display the PCI-E signal provided to the first PCI-E slot 11x16.

If two PCI-E slots are inserted with expansion cards, the BIOS 50 will instruct the central processing unit 10 to switch the eight PCI-E channels numbered 08-15 to the second PCI-E slot 12 The first half of the second PCI-E pin group 22. That is, the first to eighth first PCI-E pin groups 21 of the first PCI-E slot 11 will be sequentially assigned to the eight PCI-E channels numbered 00-07, and the second PCI-E The 1st to 8th second PCI-E pin groups 22 of slot 12 will be sequentially assigned to 8 PCI-E channels numbered 08-15, and provided to two PCIs as shown in Figure 2 -PCI-E signal of E slot x8, x8. In other words, currently, the second PCI-E slot 12 can only receive half of the PCI-E signals at most.

However, due to the large size of the heat sink of the current high-performance central processing unit 10, there may be mechanical interference with the first PCI-E slot 11 after installation, or, if the first PCI-E slot 11 When damage occurs, the user can only insert the expansion card into the second PCI-E slot 12 . However, at present, the second PCI-E slot 12 can only receive half the number of PCI-E signals, resulting in lower performance.

SUMMARY OF THE INVENTION

The present invention provides a method for controlling a PCI-E channel by a basic input and output system, which enables a second PCI-E slot to receive a complete PCI-E signal.

A method for controlling a PCI-E channel by a basic input and output system of the present invention is suitable for a mainboard module. The motherboard module includes a read only memory (ROM), a central processing unit (CPU), a memory (RAM) electrically connected to the central processing unit, a first PCI-E slot and a second PCI-E slot slot, wherein the read-only memory is electrically connected to the memory and stores a basic input output system (BIOS), the basic input output system is suitable for being loaded into the memory, the central processing unit, the first PCI-E slot and the second PCI The -E slot supports 2N PCI-E channels respectively. The control method of the PCI-E channel by the basic input and output system includes: the basic input and output system obtains whether the first PCI-E slot and the second PCI-E slot are respectively There is information that a first expansion card and a second expansion card are inserted; and if a second expansion card is inserted into the second PCI-E slot, the basic input output system instructs the central processing unit to reverse and the second PCI - The sequence of these PCI-E lanes that are electrically connected between the E slots.

In an embodiment of the present invention, the above-mentioned method for controlling the PCI-E channel by the basic input output system further includes: if the first expansion card is not inserted in the first PCI-E slot, the basic input output system instructs the central processing unit, providing to the second PCI-E slot 2N of these PCI-E lanes in reverse order.

In an embodiment of the present invention, the above-mentioned method for controlling a PCI-E channel by the BIOS further includes: if a first expansion card is inserted in the first PCI-E slot, the BIOS instructs the central processing A unit that provides a first PCI-E slot a of these PCI-E channels in the original order, and provides a second PCI-E slot 2N-a these PCI-E channels in an opposite order, where 1<a< 2N.

In an embodiment of the present invention, the above-mentioned method for controlling the PCI-E channel by the basic input output system further includes: if a first expansion card is inserted in the first PCI-E slot and the second PCI-E slot is There is no second expansion card inserted thereon, and the BIOS instructs the central processing unit to provide the first PCI-E slot with 2N originally ordered PCI-E channels.

In an embodiment of the present invention, the first to a first processor pin groups of the central processing unit are switchably connected to the first to a first PCI-E slots of the first PCI-E slot. The pin group or the (2N-a+1) to 2N second PCI-E pin groups of the second PCI-E slot to form the first to a of these PCI-E channels, the central processing unit The a+1-2Nth processor pin groups are switchably connected to the a+1-2Nth first PCI-E pin groups or the second PCI-E sockets of the first PCI-E slot. The 1st to (2N-a) second PCI-E pin groups of the slots are used to form a+1 to 2Nth PCI-E channels, wherein 1<a<2N.

In an embodiment of the present invention, the above-mentioned a is N.

In an embodiment of the present invention, the above-mentioned method for controlling the PCI-E channel by the basic input output system further includes: if the first expansion card is not inserted in the first PCI-E slot and the second PCI-E slot is A second expansion card is inserted thereon, and the 1st to a PCI-E channels are formed on the 1st to a processor pin groups of the central processing unit and the (2N-a+1th) of the second PCI-E slot. )～2N second PCI-E pin groups, the a+1～2Nth PCI-E channels are formed between the a+1～2Nth processor pin groups of the central processing unit and the second PCI-E Between the 1st to (2N-a) second PCI-E pin groups of the slot.

In an embodiment of the present invention, the above-mentioned method for controlling the PCI-E channel by the basic input output system further includes: if a first expansion card is inserted in the first PCI-E slot and the second PCI-E slot is A second expansion card is inserted thereon, and the first to a PCI-E channels are formed in the first to a processor pin groups of the central processing unit and the first to a first of the first PCI-E slots. Between the PCI-E pin groups, the a+1-2Nth PCI-E channels are formed on the a+1-2Nth processor pin groups of the central processing unit and the 1st-2Nth processor pin groups in the second PCI-E slot. Between (2N-a) second PCI-E pin groups.

In an embodiment of the present invention, the above-mentioned method for controlling the PCI-E channel by the basic input output system further includes if the first expansion card is inserted in the first PCI-E slot and the second PCI-E slot is No second expansion card is inserted, and the first to a PCI-E channels are formed in the first to a processor pin groups of the central processing unit and the first to a first PCI of the first PCI-E slot. Between -E pin groups, the a+1~2Nth PCI-E channels are formed between the a+1~2Nth processor pin groups of the central processing unit and the a+1th of the first PCI-E slot Between ~2N first PCI-E pin groups.

In an embodiment of the present invention, the above-mentioned 2N is 16.

Based on the above, since PCI-E channels need to be allocated from the first PCI-E pin group to the right in each PCI-E slot, but there is no limit to the numbering order of PCI-E channels from small to large Or from large to small, after the basic input output system of the present invention detects that a second expansion card is inserted in the second PCI-E slot, the basic input output system controls the PCI-E channel. Instructs the central processing unit to reverse the order of the PCI-E lanes provided to the second PCI-E slot, so that the 1st, 2nd, 3rd... first PCI-E pin groups of the second PCI-E slot follow The sequence is allocated to the 2Nth, 2N-1, 2N-2... PCI-E lanes of the central processing unit. If the first expansion card is not installed in the first PCI-E slot, all PCI-E channels will be allocated to the second PCI-E slot, so that the second PCI-E slot can receive the complete PCI -E signal. If the first expansion card is inserted into the first PCI-E slot, part of the PCI-E channel will be allocated to the first PCI-E slot, and another part of the PCI-E channel will be allocated to the second PCI- E slot, so that dual expansion cards can still work together.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following specific embodiments are given and described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

FIG. 1 and FIG. 2 are schematic diagrams showing that PCI-E channels of a conventional central processing unit are allocated to two PCI-E slots.

FIG. 3 to FIG. 5 are schematic diagrams of allocating PCI-E channels of a central processing unit to two PCI-E slots according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a method for controlling a PCI-E channel by a basic input output system according to an embodiment of the present invention.

Description of reference numbers:

10: Central processing unit

11: The first PCI-E slot

12: Second PCI-E slot

13: The first switch

14: The first input terminal

15: The first output terminal

16: Second switch

17: The second input terminal

18: The second output terminal

20: Processor pin group

21: The first PCI-E pin group

22: The second PCI-E pin group

50: Basic Input Output System (BIOS)

100: Basic input and output system control method for PCI-E channel

110 to 140: Steps

Detailed ways

Generally speaking, when the user presses the power button to turn on the computer system, the basic input output system (BIOS) 50 stored in the flash ROM will be electrically connected to the central processing unit through the chip set 10, and prepare to start initializing and checking the hardware components of the computer system. The basic input output system 50 sequentially initializes the central processing unit 10, the chipset, the memory, and the peripheral devices, and confirms which peripheral devices are connected to the motherboard. The operating system will be loaded into the memory to complete the booting of the computer system.

In the stage where the basic input output system 50 confirms which peripheral devices are connected to the motherboard, because generally medium and high-end motherboards usually have two PCI-E slots (the first PCI-E slot 11, the second PCI-E slot 11, the second PCI-E slot -E slot 12), the basic input output system 50 will detect which PCI-E slot is inserted with the PCI-E expansion card, and instruct the central processing unit 10 how to provide the PCI-E channel to the first PCI-E according to the detection result. The E slot 11 (usually a PCI-E slot close to the central processing unit 10 ) or/and the second PCI-E slot 12 (usually a PCI-E slot farther from the central processing unit 10 ).

The method 100 for controlling a PCI-E channel by the basic input output system 50 in this embodiment is for the basic input output system 50 to determine which PCI-E slot or slots are inserted with the PCI-E expansion card, and then, according to the detected The result indicates how the central processing unit 10 should assign the PCI-E channel to one or both of the PCI-E slots. Even if only the second PCI-E slot 12 is inserted with a PCI-E expansion card, the method 100 for controlling PCI-E channels by the basic input output system 50 of this embodiment can allocate all PCI-E channels to the first PCI-E channel. Two PCI-E slots 12, so that the second PCI-E slot 12 can receive a complete PCI-E signal. This will be described in detail below.

First of all, it should be noted that the motherboard module to which the PCI-E channel control method 100 of the basic input output system 50 of this embodiment is applicable includes a central processing unit (CPU) 10 , a A basic input output system 50 (BIOS) 50, a first PCI-E slot 11 and a second PCI-E slot 12, the first PCI-E slot 11 is a PCI-E slot close to the central processing unit 10, The second PCI-E slot 12 is a PCI-E slot away from the central processing unit 10 .

FIG. 3 to FIG. 5 are schematic diagrams of allocating PCI-E channels of the central processing unit 10 to two PCI-E slots according to an embodiment of the present invention. Please refer to FIG. 3 to FIG. 5 first. The central processing unit 10 , the first PCI-E slot 11 and the second PCI-E slot 12 respectively support 2N PCI-E channels. The first PCI-E slot 11 and the second PCI-E slot The two PCI-E slots 12 are respectively electrically connected to the central processing unit 10 . In this embodiment, 2N is taken as 16 as an example, but the number of 2N can also be 4, 8, or 32, etc., and it is not limited to 16.

The first to a first processor pin groups 20 of the central processing unit 10 are switchably electrically connected to the first to a first PCI-E pin groups 21 or the second of the first PCI-E slots 11 . (2N-a+1) to 2N second PCI-E pin groups 22 of the PCI-E slot 12 to form the first to a PCI-E channels, and the a+1 to a+1 to the central processing unit 10 The 2N processor pin groups 20 are switchably connected to the a+1-2N first PCI-E pin groups 21 or the second PCI-E slots 12 of the first PCI-E slot 11 . The 1st to (2N-a) second PCI-E pin groups 22 are formed to form a+1 to 2Nth PCI-E channels, wherein 1<a<2N. In this embodiment, a is taken as N as an example, but in other embodiments, a may not be half of 2N, that is, a is not N.

More specifically, in this embodiment, the central processing unit 10 , the first PCI-E slot 11 and the second PCI-E slot 12 respectively support 16 PCI-E channels (that is, the so-called x16 bandwidth). . The 16 groups of processor pin groups 20 of the central processing unit 10 correspond to the 16 PCI-E channels, and the 16 PCI-E channels are sequentially numbered from 00 to 15. The central processing unit 10 is numbered from the left of FIG. 3 . The 1st to 8th processor pin groups 20 correspond to the PCI-E channels numbered 00 to 07, the 1st to 8th processor pin groups 20 are connected to the first input end 14 of the first switch 13, and The first output terminal 15 of the first switch 13 is switchably electrically connected to the first PCI-E pin group 21 of the first PCI-E slot 11 from the left of FIG. The ninth to sixteenth second PCI-E pin groups 22 of the second PCI-E slot 12 form the first to a PCI-E channels.

The 9th to 16th processor pin groups 20 of the central processing unit 10 correspond to the PCI-E channels numbered 08 to 15 and are connected to the second input terminal 17 of the second switch 16 . The second output terminal 18 of the second switch 16 is switchably electrically connected to the ninth to sixteenth first PCI-E pin groups 21 of the first PCI-E slot 11 or the second PCI-E slot 12 . The first to eighth second PCI-E pin groups 22 are formed to form a+1 to 2Nth PCI-E channels. The first switch 13 and the second switch 16 here can be physical switches, software programs or any other switching modes. If the first switch 13 and the second switch 16 are physical switches, the first switch 13 and the second switch 16 may each have multiple small switches (not shown) to switch multiple channels. For example, if one small switch can switch two channels, the first switch 13 and the second switch 16 can each have four small switches. Of course, the number of small switches included in the first switch 13 and the second switch 16 is not limited thereto.

It is worth mentioning that the order of the PCI-E channels of the first PCI-E slot 11 is opposite to the order of the PCI-E channels of the second PCI-E slot 12 . This is because the operable PCI-E channels in each PCI-E slot are connected from the first PCI-E pin group in each PCI-E slot and afterward (that is, from the left on the drawing Sorting to the right) are allocated in order, as long as the first PCI-E pin group in each PCI-E slot and several other PCI-E pin groups in succession are assigned, and the assigned PCI-E The numbering of the channels may be continuous, and there is no restriction on whether the numbering sequence of the allocated PCI-E channels is from small to large or from large to small.

Therefore, in order to allow only the first PCI-E slot 11 to have the first expansion card inserted (as shown in FIG. 3 ), the first PCI-E slot 11 and the second PCI-E slot 12 can simultaneously have the first expansion card inserted. With the second expansion card (as shown in Figure 4), only the second PCI-E slot 12 has a second expansion card (as shown in Figure 5), these three modes can work, and only the second PCI-E slot 12 When a second expansion card is inserted, the second PCI-E slot 12 can also be assigned to complete 16 PCI-E channels. The lanes of the second PCI-E slot 12 are assigned opposite numbers from left to right. An example will be explained below.

FIG. 6 is a schematic diagram of a method for controlling a PCI-E channel by a basic input output system according to an embodiment of the present invention. Please refer to FIG. 3 to FIG. 6 at the same time, the control method 100 of the PCI-E channel by the basic input output system 50 of this embodiment includes the following steps.

First, in step 110, the BIOS 50 obtains information about whether the first expansion card and the second expansion card are inserted in the first PCI-E slot 11 and the second PCI-E slot 12, respectively.

There are actually three situations. First, only the first PCI-E slot 11 has the first expansion card inserted (step 120 in FIG. 3 and FIG. 6 ). Second, the first PCI-E slot 11 and the second PCI-E slot 12 have both the first expansion card and the second expansion card inserted (step 130 in FIG. 4 and FIG. 6 ). Third, only the second expansion card is inserted. A second expansion card is inserted into the PCI-E slot 12 (step 140 in FIG. 5 and FIG. 6 ).

Next, if the first expansion card is inserted in the first PCI-E slot 11 and the second expansion card is not inserted in the second PCI-E slot 12, that is, the situation in FIG. 3, the first to a The PCI-E channel is formed between the first to a first PCI-E pin groups 20 of the central processing unit 10 and the first to a first PCI-E pin groups 21 of the first PCI-E slot 11 . a+1-2N PCI-E channels are formed in the a+1-2Nth processor pin groups 20 of the central processing unit 10 and the a+1-2Nth first PCI-E slots of the first PCI-E slot. Between the E pin groups 21, the BIOS 50 instructs the central processing unit 10 to provide 2N originally ordered PCI-E channels to the first PCI-E slot 11 (step 120). More specifically, if only the first PCI-E slot 11 has the first expansion card inserted, the BIOS 50 will instruct the central processing unit 10 to allocate the 16 PCI-E channels to the first slot in the original order. PCI-E slot 11.

If a first expansion card is inserted into the first PCI-E slot 11 and a second expansion card is inserted into the second PCI-E slot 12, that is, the situation in FIG. 4, the first to a PCI-E The channels are formed between the first to a first PCI-E pin groups 20 of the central processing unit 10 and the first to a first PCI-E pin groups 21 of the first PCI-E slot 11 , the a+1th ~2N PCI-E channels are formed in the a+1~2Nth processor pin groups 20 of the central processing unit 10 and the 1st~(2N-a) second PCI- Between the E pin groups 22, the BIOS 50 instructs the central processing unit 10 to provide the first PCI-E slot 11a with the originally ordered PCI-E lanes, and to the second PCI-E slot 12 2N -a reverse-ordered PCI-E lanes (step 130).

More specifically, when the first PCI-E slot 11 and the second PCI-E slot 12 are simultaneously inserted with the first expansion card and the second expansion card, the basic input output system 50 will instruct the central processing unit 10, numbered 00- The 8 PCI-E channels of 07 will be allocated to the first eight first PCI-E pin groups 21 of the first PCI-E slot 11, and the 8 PCI-E channels numbered 08 to 15 are reversed. are allocated to the first eight second PCI-E pin groups 22 of the second PCI-E slot 12 . For the first PCI-E slot 11 and the second PCI-E slot 12, as long as the 8 consecutive PCI-E channels from the left are assigned to consecutively numbered PCI-E channels It can work, and the numbering can be from large to small or from small to large. In the situation shown in FIG. 4 , the numbers of the PCI-E channels to which the first eight first PCI-E pin groups 21 of the first PCI-E slot 11 are sequentially assigned are from small to large (00-07). The numbers of the PCI-E channels to which the first eight second PCI-E pin groups 22 of the second PCI-E slot 12 are sequentially allocated are in descending order (15-08). In this case, the first PCI-E slot 11 and the second PCI-E slot 12 can operate in a mode with a bandwidth of x8 and x8.

If the first expansion card is not inserted in the first PCI-E slot 11 and the second expansion card is inserted in the second PCI-E slot 12, that is, the situation in FIG. 5, the first to a PCI-E Channels are formed between the first to a processor pin groups 20 of the central processing unit 10 and the (2N-a+1) to 2N second PCI-E pin groups 22 of the second PCI-E slot 12 . During the time, the a+1-2Nth PCI-E channels are formed in the a+1-2Nth processor pin groups 20 of the central processing unit 10 and the 1st-(2N-aths of the second PCI-E slot 12 ) between the second PCI-E pin groups 22, the BIOS 50 instructs the central processing unit 10 to provide 2N PCI-E lanes in reverse order to the second PCI-E slot 12 (step 140).

More specifically, if only the second expansion card is inserted in the second PCI-E slot 12, the basic input output system 50 will instruct the central processing unit 10 to invert all 16 PCI-E channels to be allocated to the second expansion card. Two PCI-E slots 12, the 16 second PCI-E pin groups 22 of the second PCI-E slot 12 are sequentially assigned to PCI-E channels numbered from large to small (15-00), The second PCI-E slot 12 can receive the complete PCI-E signal.

To sum up, since PCI-E channels need to be allocated from the first PCI-E pin group to the right in each PCI-E slot, there is no limit to the numbering order of PCI-E channels from small to small. From big to big or from big to small, the basic input output system of the present invention controls the PCI-E channel after the basic input output system detects that there is a second expansion card inserted in the second PCI-E slot, the basic input output The output system instructs the central processing unit to reverse the order of the PCI-E lanes provided to the second PCI-E slot to make the 1st, 2nd, 3rd... first PCI-E pins of the second PCI-E slot The groups are sequentially assigned to the 2Nth, 2N-1, 2N-2... PCI-E lanes of the central processing unit. If the first expansion card is not installed in the first PCI-E slot, all PCI-E channels will be allocated to the second PCI-E slot, so that the second PCI-E slot can receive the complete PCI -E signal. If the first expansion card is inserted into the first PCI-E slot, part of the PCI-E channel will be allocated to the first PCI-E slot, and another part of the PCI-E channel will be allocated to the second PCI- E slot, so that dual expansion cards can still work together.

Although the present invention has been disclosed by the above examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be as defined in the appended claims.

Claims (9)

1. A method for controlling a PCI-E channel by a basic input and output system, applicable to a mainboard module, the mainboard module comprising a central processing unit, a basic input and output system electrically connected to the central processing unit respectively , a first PCI-E slot and a second PCI-E slot, wherein the central processing unit, the first PCI-E slot and the second PCI-E slot respectively support 2N PCI -E channel, the control method for the PCI-E channel of the basic input output system, characterized in that, comprising: The BIOS obtains information on whether a first expansion card and a second expansion card are inserted in the first PCI-E slot and the second PCI-E slot, respectively; and If the second expansion card is inserted into the second PCI-E slot, the BIOS instructs the central processing unit to reverse the electrical connection between the second PCI-E slot and the second PCI-E slot. The sequence of multiple PCI-E lanes connected; Wherein, the first to a first processor pin groups of the central processing unit are switchably connected to the first to a first PCI-E pin groups of the first PCI-E slot or (2N-a+1) to 2N second PCI-E pin groups of the second PCI-E slot to form the first to a plurality of PCI-E channels, the central processing The (a+1)-2Nth processor pin groups of the unit are switchably connected to the (a+1)-2Nth first PCI-E slots in the first PCI-E slot. The E pin group or the 1st to (2N-a) second PCI-E pin groups of the second PCI-E slot to form the (a+1) to 2Nth PCI-E pin groups. multiple PCI-E channels, where 1<a<2N. 2. BIOS as claimed in claim 1 is characterized in that to the control method of PCI-E channel, also comprises: If the first expansion card is not inserted into the first PCI-E slot, the BIOS instructs the central processing unit to provide the second PCI-E slot with 2N reversely ordered the multiple PCI-E lanes. 3. BIOS as claimed in claim 1 is to the control method of PCI-E channel, is characterized in that, also comprises: If the first expansion card is inserted into the first PCI-E slot, the BIOS instructs the central processing unit to provide the first PCI-E slot with a originally ordered The multiple PCI-E lanes are provided to the second PCI-E slot 2N-a reversely ordered multiple PCI-E lanes, where 1<a<2N. 4. BIOS as claimed in claim 1 is to the control method of PCI-E channel, it is characterized in that, also comprises: If the first expansion card is inserted into the first PCI-E slot and the second expansion card is not inserted into the second PCI-E slot, the BIOS indicates the The central processing unit provides the first PCI-E slot with 2N originally ordered PCI-E channels. 5 . The method for controlling a PCI-E channel by a basic input output system according to claim 1 , wherein a is N. 6 . 6. BIOS as claimed in claim 1 is characterized in that to the control method of PCI-E channel, also comprises: If the first expansion card is not inserted in the first PCI-E slot and the second expansion card is inserted in the second PCI-E slot, the first to a of the multiple PCI-E channels are formed in the first to a of the plurality of processor pin groups of the central processing unit and the plurality of (2N-a+1) to the second PCI-E slot Between the 2N second PCI-E pin groups, the (a+1)-2Nth multiple PCI-E channels are formed in the (a+1)-2Nth multiple PCI-E channels of the central processing unit. between the processor pin groups and the first to (2N-a) second PCI-E pin groups of the second PCI-E slot. 7. BIOS as claimed in claim 1 is characterized in that, also comprises: If the first expansion card is inserted into the first PCI-E slot and the second expansion card is inserted into the second PCI-E slot, the first to a of the multiple PCI-E channels are formed in the first to a of the plurality of processor pin groups of the central processing unit and the first to a of the first PCI-E slots of the first PCI-E slot. Between the E pin groups, the (a+1)-2Nth of the plurality of PCI-E channels are formed in the (a+1)-2Nth of the plurality of processor pin groups of the central processing unit and between the first to (2N-a) second PCI-E pin groups of the second PCI-E slot. 8. BIOS as claimed in claim 1 is characterized in that to the control method of PCI-E channel, also comprises: If the first expansion card is inserted into the first PCI-E slot and the second expansion card is not inserted into the second PCI-E slot, the first to a of the multiple PCI-E channels are formed in the first to a of the plurality of processor pin groups of the central processing unit and the first to a of the first PCI-E slots of the first PCI-E slot. Between the E pin groups, the a+1-2Nth PCI-E channels are formed between the (a+1)-2Nth processor pin groups of the central processing unit and all the processor pin groups (a+1)-2Nth. between the (a+1)-2Nth first PCI-E pin groups of the first PCI-E slot. 9 . The method for controlling a PCI-E channel by a basic input output system according to claim 1 , wherein 2N is 16. 10 .

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