CN107579011A - Method for interconnecting stacked semiconductor devices - Google Patents

Abstract

Methods for fabricating semiconductor devices are described. The method includes forming an edge on the first and second dies. The edge extends laterally away from the first and second dies. A second die is stacked on the first die and after stacking, one or more vias are drilled through the edges. The semiconductor device includes redistribution layers extending over at least one of the first and second dies and the respective edges, respectively. The one or more vias extend through the respective edges, and the one or more vias communicate with the first and second dies via the edges.

Description

Method for interconnecting stacked semiconductor devices

This application is a divisional application of an application with a filing date of September 26, 2014, an application number of 201410504407.8, and an invention title of "Method for Interconnecting Stacked Semiconductor Devices".

technical field

Embodiments described herein relate generally to multilayer fabrication and electrical interconnection in microelectronic devices.

Background technique

A multilayer semiconductor device includes a plurality of dies that are stacked and bonded with electrical connections extending therebetween. In one example, a stacked device is formed from two or more wafers (including multiple dies) that are coupled together at an interface between the two or more wafers. The coupled wafers are diced and wire bonded to form multiple devices.

In some examples, some dies (eg, chips within a die) of the wafer are defective and unusable. Due to wafer-to-wafer coupling, these defective dies remain contained in the multilayer semiconductor device, and the resulting device is defective and unusable even though many other dies within the device are perfectly usable. Thus, wafer-based fabrication reduces the overall yield of usable multilayer devices.

In other examples, interconnection between dies within a multilayer semiconductor device is provided by wire bonding between layers. For example, two or more semiconductor dies are stacked (eg, bonded) on a substrate, and wires run along wire bond pads of the semiconductor dies to the substrate. On the substrate, the electrical interconnects are further routed to a ball grid array on the other side of the substrate. The stacked semiconductor die are molded to protect the die and wires. Wires provide indirect coupling between two or more layers of a multilayer device. Indirect coupling between two or more layers using bond wires limits data and power transfer (eg, speed of data transfer and corresponding performance). Additionally, the introduction of the substrate and mold cap over the stacked die increases the height (z-height) of the multilayer device.

Improved multilayer fabrication techniques and faster interlayer interconnection techniques that address these and other technical challenges are desired.

Description of drawings

1 is a cross-sectional view of a multilayer semiconductor device including a via extending through an edge extending laterally from a die.

FIG. 2 is a detailed cross-sectional view of the multilayer semiconductor device of FIG. 1 .

FIG. 3 is a process flow diagram illustrating one example of a method for fabricating a multilayer semiconductor device.

FIG. 4 is a table showing height differences of semiconductor devices.

FIG. 5 is a flowchart illustrating one example of a method for manufacturing a multilayer semiconductor device.

6 is a table comparing Z-heights of semiconductor devices including wire bonds to semiconductor devices including vias within lateral edges.

FIG. 7 is a block diagram illustrating another example of a method for manufacturing a multilayer semiconductor device.

FIG. 8 is a block diagram illustrating another example of a method for manufacturing a multilayer semiconductor device.

9 is a cross-sectional view of another example of a multilayer semiconductor device including vias extending through one or more lateral edges.

FIG. 10 is a flowchart illustrating another example of a method for manufacturing a multilayer semiconductor device.

Figure 11 is a schematic diagram of an electronic system according to some embodiments of the present disclosure.

detailed description

The following description and drawings illustrate specific embodiments sufficiently to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in or substituted for those of other embodiments. Embodiments set forth in the claims encompass all available equivalents of those claims.

FIG. 1 shows one example of a semiconductor device 100 including a plurality of dies 102 . For example, as shown in FIG. 1 , semiconductor device 100 includes at least a first die 104 and a second die 106 . As shown, the first die 104 and the second die 106 are coupled along the upper and lower surfaces of the respective dies. As further shown in FIG. 1 , semiconductor device 100 includes one or more edges 108 extending laterally from each of dies 102 , eg, in a dimension of edge lateral extension 110 . In one example, as shown with respect to first die 104 and second die 106 , respective edges 108 extend laterally away from respective edges of first die 104 and second die 106 .

In one example, edge 108 is composed of, but is not limited to, a polymer material such as a dielectric mold compound configured to mold around first die 104 and second die 106 and thereby protect the die within. In another example, first die 104 and second die 106 are composed of a material that is harder than the molding compound used in edge 108 , but are not limited to such. For example, first die 104 and second die 106 are composed of silicon. In another example, edge 108 is composed of a softer polymer (eg, lower modulus of elasticity) configured to protect first die 104 and second die 106 of semiconductor device 100 . The softer polymer of edge 108 is easier to penetrate (eg, laser drilling, mechanical drilling, FIB removal, etching, etc.) as described herein.

Referring again to FIG. 1 , as shown, a plurality of vias 112 extend through one or more dies 102 . As will be described herein, conductive vias 112 allow communication and data transfer between each of dies 102 and external circuitry including, but not limited to, ball grids disposed along the surface of semiconductor device 100 Array 114, contact grid array, pin grid array, etc. As shown in the cross-sectional view of FIG. 1 , a plurality of vias 112 are formed through the edge 108 opposite the first die 104 and the second die 106 . As will be described herein, in one example, vias 112 are formed after stacking dies 102 into the structure shown in FIG. 1 . For example, vias 112 are drilled into edge 108 using one or more of mechanical, chemical (photolithographic) and laser drilling methods.

As will be described further herein, in one example, each of dies 102 includes a redistribution layer, for example, a patterned series of conductive traces provided adjacent each of dies 102 . The redistribution layer extends over the footprint of die 102 and into edge 108 . Conductive traces formed along the redistribution layer are configured for coupling with vias 112 . Accordingly, each of dies 102 of semiconductor device 100 is capable of communicating with one or more other dies 102 and, optionally, ball grid array 114 through vias 112 . By providing each of the dies 102 with an edge 108 and corresponding vias 112 therein, with an underlying substrate having a ball grid array overlaid on the mold cap (adjusted to the size of the free leads of the package) and Direct coupling between the one or more dies 102 and the ball grid array 114 is achieved compared to the additional indirect coupling provided by wire bonding of the one or more dies 102 . That is, in one example, the edges 108 extending from the plurality of dies 102 (e.g., in the size of the edge lateral extension 110) provide a mechanism for closely receiving the plurality of vias 112 therein, which allows for Direct communication between the dies 102 of the semiconductor device 100 without the additional need for a wire bonded die cap and substrate or the like covering the plurality of dies 102 to provide such communication. Accordingly, the height (Z-height) of the semiconductor device 100 is substantially less than the height of a semiconductor device comprising a plurality of dies interconnected using wire bonds and then packaged within a mold cap and having an underlying substrate. For example, in some examples, the Z height savings for semiconductor device 100 having via 112 provided in edge 108 may be up to 0.2 mm relative to a comparable wire bonded device.

Referring again to FIG. 1 , as further shown, in one example, semiconductor device 100 includes a ball grid array 114 including a plurality of solder balls 116 disposed along one or more dies 102 . In the example shown in FIG. 1 , the first die 104 (eg, the redistribution layer of the first die 104 described herein) is directly coupled with the solder balls 116 . Thus, the data transfers of each of the dies 102 via the vias 112 are sent via the vias 112 to the first die 104 and any other dies 102 accordingly. The solder balls 116 provided in the ball grid array 114 provide input and output to and from the semiconductor device 100 while avoiding otherwise requiring the underlying substrate of the plurality of dies 102 to receive and communicate information from the semiconductor device. That is, by directly coupling the ball grid array 114 to the redistribution layer of the first die 104, the semiconductor device 100 shown in FIG. 1 does not require additional substrates for some semiconductor devices, thereby achieving additional space saves and provides a more compact device. By providing a plurality of vias 112 through the edge 108, and a ball grid array 114 coupled directly along the first die 104, high-speed transmission within (and to and from) the semiconductor device 100 is facilitated, while at the same time making the semiconductor The overall height of device 100 is minimized.

Referring now to FIG. 2 , a more detailed cross-sectional view of the semiconductor device 100 previously shown in FIG. 1 is provided. In the detailed view of FIG. 2 , a plurality of dies 102 are again shown in a stacked configuration, and each of dies 102 includes a respective edge 108 extending laterally from die 102 , eg, in an edge lateral extension 110 . In one example, each of dies 102 is part of a die assembly 201 that includes a respective die 102, edge 108, and redistribution layer 202 (and optional molding compound 200).

As shown in FIG. 2 , via 112 or vias are provided through edge 108 and extend continuously between dies 102 . In another example, one or more vias 112 extend through one or more edges 108 to provide a gap between two or more dies 102 of semiconductor device 100 or between dies 102 and the ball grid array (via further communication between distribution layers 202). That is, the vias 112 provided in the edge 108 extend partially or fully through the stack of die assemblies 201 . Other vias 112 provided through the edges 108 extend through two or more edges 108 to provide communication between the two or more dies 102 of the stacked semiconductor device 100 accordingly. In one example, the vias 112 are drilled from both sides of the edge 108 , eg, from the upper surface 203 and the bottom surface 205 of the semiconductor device 100 . In another example, a plurality of vias 112 are drilled from one or both sides of the semiconductor device 203 , 205 . In another example, vias 112 are drilled after stacking. Thus, vias 112 are easier to align through previously stacked die 102 . As opposed to forming multiple individual vias and then stacking and aligning the vias (eg, dies), drilling is done in a single efficient operation, which consolidates the via formation in a single step.

As described above, each of die assemblies 201 includes die 102 and redistribution layer 202 formed adjacent to die 102 . As shown, redistribution layer 202 extends beyond a footprint (eg, the lateral footprint of die 102 ) and into edge 108 . For example, in one example, the die 102 is encapsulated in a molding compound 200, such as the panel frame described herein. After being received into the panel frame, mold compound 200 is introduced into the panel frame and allowed to harden around each of dies 102 . Patterning techniques are used to provide conductive traces of redistribution layer 202 along each of dies 102 . For example, as shown in FIG. 2 , the redistribution layer 202 extends laterally from and across the plurality of dies 102 over the plurality of edges 108 of the die assembly of each of the die assemblies 201 , respectively. 108. Redistribution layer 202 thus provides a "fan-out" structure that allows distributed interconnection of each of die 102 with other die within semiconductor device 100 and with ball grid array 114 (e.g., via vias 112 ). Accordingly, the fan-out redistribution layer 202 cooperates with the plurality of vias 112 provided through the edge 108 to minimize the overall height of the semiconductor device 100 accordingly, while at the same time between each of the dies 102 A direct connection is provided, and a direct connection is provided to the ball grid array 114 underneath the first die 104 . The redistribution layer provides conductive traces extending laterally from the dies, which are then interconnected by vias 112 . In other words, vias 108 and redistribution layer 202 provide interconnects housed within edge 108 without the need for a larger die cap (eg, to otherwise encapsulate free leads).

As further shown in FIG. 2 , a molding compound 200 (eg, a dielectric resin forming a corresponding polymer) is provided laterally and on top of the plurality of dies 102 prior to stacking the dies. In another example, molding compound 200 is provided on the side of plurality of dies 102 opposite from along the upper surface of each of dies 102 . The molding compound 200 extends laterally to form the edge 108 having a lateral extension 110 relative to the edge of the die 102 . As previously described, after molding the plurality of dies 102 (as described herein in a flat panel with a wafer or panel structure), the plurality of dies 102 are cut from the panel for operability Tests are performed and then stacked into a structure such as that shown in FIG. 2 of the stacked structure of semiconductor device 100 . In another example, multiple dies are tested prior to being singulated from a raw silicon wafer and forming a reconstituted die panel (described herein).

Each of dies 102 are coupled to each other with a layer of adhesive 204 or other bonding substance provided between each of die assemblies 201 . As shown in FIG. 2 , adhesive 204 aligns with each of dies 102 and holds dies 102 in an aligned configuration. In one example, after dies 102 are stacked, a plurality of vias 112 are drilled through semiconductor device 100 to thereby provide a plurality of vias 112 in die 102 through redistribution layer 202 of each of die assemblies 201 . interconnection between each die.

In another example, in the structure shown in FIG. 2 , the via holes 112 are respectively formed in each of the die assemblies 201 before stacking the die assemblies. Accordingly, vias 112 are aligned during the stacking process to accordingly ensure communication between each of die assemblies 201 (and ball grid array 114 ). In one example, the vias 112 are filled with a conductive material, such as copper, which is provided by sputtering or vapor deposition to interconnect each of the dies 102 of the semiconductor device 100 and to connect the dies 102 to the ball grid array. 114 connections.

Referring again to FIG. 2 , each of vias 112 is shown within edge 108 and spaced laterally relative to each of dies 102 as previously described herein. That is, dies 102 are interconnected by conductive vias 112 provided by laterally extending edges 108 . The connection between each of die 102 and ball grid array 114 is incorporated into vias by providing interconnection between die 102 in a lateral portion of each of die assembly 201 . 112 and redistribution layer 202 (eg, lateral edge 108 ) fanned out from each of dies 102 . Accordingly, components of other semiconductor devices, such as a conductive substrate provided under the stacked dies, and a mold cap provided for encapsulating and protecting the dies, and each of the dies with the underlying substrate are avoided accordingly. wire bonding between substrates. Instead, with semiconductor device 100 , each of dies 102 is molded with a molding compound, providing laterally extending edges 108 for redistribution layer 202 and providing space for laterally disposed vias 112 . Thus, the vertical height or Z-height of the semiconductor device 100 is minimized relative to the Z-height of other structures of the semiconductor device using wire bonds and the underlying substrate (and corresponding die caps on top of the wire bonds).

Additionally, since the via 112 is provided through the edge 108 , the via 112 is easier to form within the semiconductor device 100 . For example, in at least some examples, vias are provided through the silicon of die 102 . Silicon is more difficult to drill through because it is brittle and harder (eg, has a higher modulus of elasticity). However, the polymer in molding compound 200 for semiconductor device 100 provides a softer material (relative to silicon) for easy drilling of each of dies 112 . The softer material of the edge 108 accordingly ensures that vias are easily formed in the semiconductor device 100 and, therefore, conductive material is easily deposited within the vias 112 to interconnect the redistribution layers 202 of the respective dies 102 of the die assembly 201 Each redistribution layer in . Similarly, since vias 112 are easily formed through the molding compound of edge 108 , damage to semiconductor device 100 is minimized, eg, before or after forming the stacked structure of dies 102 . In contrast, drilling through the silicon of one or more silicon dies is problematic because of the risk of debris or damage to the semiconductor within the die. One example of molding compound 200 includes, but is not limited to, an epoxy resin that includes one or more additives configured to tailor properties of edge 108 (eg, packaging of semiconductor device 100 ) to meet packaging requirements. For example, epoxy resins include additives to adjust one or more properties of modulus of elasticity, coefficient of thermal expansion, curing temperature, curing time, glass transition temperature, thermal conductivity, and the like.

FIG. 3 shows a process flow diagram of a series of schematic diagrams of one example of a process for the fabrication of a semiconductor device such as semiconductor device 100 shown in FIGS. 1 and 2 . In a first stage 301 , a plurality of dies 302 are shown in a monolithic semiconductor wafer 300 . For example, a plurality of dies 302 are formed in a silicon wafer as previously known (by means of masking and etching of the wafer). Dies 302 in silicon wafer 300 are probed to determine which dies are operational (operational dies without manufacturing or performance defects). Semiconductor wafer 300 is diced to separate each of dies 302 accordingly. Optionally, after dicing and then separation, die 302 is probed.

The operable die 306 is separated from the remaining die 302 , and in stage 303 the operable die 306 is disposed within the panel frame 304 . As shown in FIG. 3 , in one example, panel frame 304 has a substantially similar structure to semiconductor wafer 300 shown in stage 301 . In another example described herein, the panel frame 304 has another shape, such as a square or a rectangle. A plurality of operable dies 306 are assembled into the panel frame 304 and a reconstituted die panel 308 is formed. For example, a molding compound such as a resin that hardens into a dielectric polymer is supplied to the panel frame 304 . The molding compound hardens around each of the operable dies 306 to correspondingly form the separate die assembly 201 (comprising die 102 and corresponding edge 108 ) shown in FIG. 2 . In the configuration shown in stage 303 , the reconstituted die panel 308 facilitates stacking, eg, to form one or more semiconductor devices 100 as previously described herein.

In another example, the redistribution layer 202 for each of the dies 306 is formed after forming the reconstituted die panel (eg, after molding the operable dies 306 ). For example, fabrication and lithography are used to etch the conductive traces of redistribution layer 202 on mold compound 200 and die 306 . As previously mentioned, redistribution layer 202 has a fan-out configured to extend over the footprint of operable die 306 as well as edge 108 (see, eg, FIG. 2 ).

Referring now to stage 305 , reconstituted die panel 308 is shown in an exploded structure with each of plurality of die panels 310 stacked. As shown, the operational dies 306 of each of the plurality of reconstituted die panels 310 are shown in a substantially similar configuration and are correspondingly aligned between each of the reconstituted die panels 310 . That is, the operable die 306 of each of the die panels 310 , for example, including the first and second reconstituted die panels 312 , 314 , are aligned so that in subsequent steps in the process, the stacked When the dies are separated (diced), stacked semiconductor devices are provided accordingly. As previously described, in one example, adhesive 204 is applied between each of the plurality of reconstituted die panels 310 to ensure coupling between the plurality of reconstituted die panels 310, including holding the tubes therein. Core alignment.

At stage 307 , a plurality of vias 112 are formed in the stacked plurality of reconstituted die panels 310 . For example, as shown at stage 307 , stacked panel assembly 316 includes a plurality of reconstituted die panels 310 in a stacked and bonded configuration. Accordingly, the plurality of dies 102 (corresponding to operational dies 306 ) of panel 310 are aligned in a configuration corresponding to the arrangement of devices 100 shown in FIGS. 1 and 2 . Vias 112 are formed within edge 108 (including redistribution layer 202 shown in FIG. 2 ) extending laterally away from each of dies 102 (306 shown in FIG. 3 ).

In one example, vias 112 are formed in a batch process, such as including drilling through edge 108 of each of respective dies 102 . That is, in the stacked panel assembly 316 (before dicing), a plurality of vias 112 are drilled through the stacked panel assembly 316 to facilitate corresponding Rapid formation of the via hole 112 . In another example, the stacked panel assembly 316 is diced into a plurality of semiconductor devices 100 . Thereafter, the plurality of separate semiconductor devices 100 are respectively drilled to form vias 112 extending through the edge 108 . After via 112 is formed, a conductive material such as copper is sputtered or vapor deposited within the channel of via 112 to electrically couple die 306 (eg, through redistribution layer 202 of edge 108 ).

As shown at stage 309, a ball grid array 114 (also shown in Figures 1 and 2) is also provided. In one example, the ball grid array 114 of each of the semiconductor devices 100 is formed along the semiconductor devices in a manner similar to stage 307 while still remaining within the stacked panel assembly 316 shown in stage 307 . Optionally, the ball grid array 114 is formed along the semiconductor device 100 after dicing, for example into the semiconductor device 100 shown in stage 309 .

Referring again to stage 309 , the completed semiconductor device 100 is shown with stacked die 102 and vias 112 extending through edge 108 . A ball grid array 114 is also shown on the bottom layer of the semiconductor device 100 , eg, coupled to a redistribution layer associated with the first die 104 (as shown in FIG. 2 ).

The process shown in FIG. 3 schematically provides a plurality of semiconductor devices 100 , such as the devices shown in FIGS. 1 and 2 . Since each of the panel frames 304 and the corresponding reconstituted die panel 310 includes only operational dies 306 , a semiconductor device 100 including one or more damaged or defective dies 102 is substantially avoided. That is, referring again to stage 305 , each of the operational dies 306 contained in each of the plurality of reconfigured die panels 310 was previously tested and known to be operational. Accordingly, the semiconductor device 100 resulting from the stacked panel assembly 316 is operable accordingly. The process shown in the figure minimizes, or avoids, defective or damaged semiconductors relative to, for example, existing fabrication techniques using monolithic semiconductor wafers with operable, defective and damaged semiconductors therein. Contains defective or damaged semiconductors. In previous fabrication techniques, defective or damaged semiconductors were included in finished devices, resulting in the scrapping of an otherwise entirely usable device. In other words, using the processes described herein, one or more (eg, a plurality) of defective or damaged die 302 provided in one or more semiconductor wafers 300 will not enter the manufacturing process as described above. in an otherwise fully operable semiconductor device 100 .

Thus, the yield of the semiconductor device 100 is substantially higher than other processes that use the entire semiconductor wafer 300 including operable and defective or damaged dies. In addition to higher yields, the configuration of vias 112, such as through edge 108, provides direct interconnection between each of dies 102 without the need for larger mold caps and substrates, while the lead In the case of bonded semiconductor devices, larger mold caps and substrates are required. Therefore, the semiconductor device 100 produced by the process shown in FIG. 3 has more reliable operability characteristics and minimized vertical height (Z high).

Referring now to FIG. 4 , two further stages 403 , 405 are provided as an alternative to the stages 303 and 305 shown in FIG. 3 . For example, the panel frame 400 shown in FIG. 4 has a square or rectangular (eg, non-circular) configuration relative to the wafer structure of the panel frame 304 shown in stage 303 . Accordingly, the panel frame 400 arranges the operable dies 306 in a grid such as a pattern with a square rectangular structure. The reconstituted die panel 402 shown in stage 403 is then stacked into a plurality of reconstituted die panels 404 as shown in stage 405 in FIG. 4 . As further shown in FIG. 4 , the plurality of reconstituted die panels 404 includes at least first and second reconstituted die panels 406 , 408 .

The process previously described in FIG. 3 is then performed in a substantially similar manner to the plurality of reconstituted die panels 404 provided in the stack. That is, in one example, vias 112 are formed through plurality of edges 108 extending laterally away from each of dies 102 . In one example, the via 112 is formed in the edge 108 while the die 102 is being held in the stack (eg, prior to dicing). In a similar manner, at stage 307, the ball grid array 114 is also applied to the first reconfigured die panel 406 of the semiconductor device 100 while maintaining it in the stacked panel assembly shown in FIG. Die panel 406 . In another example, the vias 112 and the ball grid array 114 are formed on an individual semiconductor device 100, such as after the semiconductor device 100 is diced from the stacked plurality of reconstituted die panels 404, as previously described herein. .

FIG. 5 shows a cross-sectional view of a semiconductor device 500 including a wire bond between an underlying substrate 506 and a die 502 of the device 500 . As further shown in FIG. 5 , one or more leads 504 are bonded to each of dies 502 and extend through semiconductor device 500 (eg, through mold cap 510 ). Each die is connected to a substrate 506 . As shown, at least some of the plurality of leads 504 first extend from the respective die 502 to the substrate 506 (which includes a plurality of conductive traces), and then extend from the substrate 506 through additional leads 504 to One or more other dies 502 , while interconnects between each of dies 502 are provided. As further shown in FIG. 5 , ball grid array 508 is provided along an opposite surface of substrate 506 and is interconnected to die 502 by wires 504 extending from substrate 506 to die 502 .

In contrast to the assembly shown in FIG. 5 , the semiconductor device 100 described herein ( FIGS. 1 and 2 ) includes a plurality of dies 102 in a stacked structure including laterally extending from each die 102 ( See, for example, the plurality of laterally extending edges 108 of laterally extending 110). Edge 108 provides a mold compound, resin, etc. that is configured for drilling and forming of vias 112 therein. As previously described herein, each of die assemblies 201 is formed with redistribution layer 202 , for example to provide a fan-out structure of conductive traces extending beyond the horizontal footprint of each of dies 102 . Thus, with vias 112 extending through redistribution layer 202, electrical interconnection between each of dies 102 is provided in a compact lateral location relative to dies 102 (eg, in edge 108). even. Die-to-die interconnection is provided in a lateral space adjacent to each of dies 102 without additionally requiring overmold cap 510 to accommodate multiple leads 504 of semiconductor device 500 shown in FIG. 5 . Additionally, vias 112 extend between each of dies 102 . For example, vias 112 extend between two or more dies 102 to provide direct connections between dies 102 and thus avoid intermediate substrate 506 as shown in FIG. 5 .

Furthermore, the semiconductor device 100 shown in FIGS. 1 and 2 does not require a substrate 506 for input to or output from the device 100 . Alternatively, device 100 including die 102 interconnected with vias 112 and redistribution layer 202 is configured to provide input and output through ball grid array 114 coupled along redistribution layer 202 of first die 104 . In other words, the substrate 506 and mold cap 510 shown in FIG. 5 are no longer required in the semiconductor device 100 shown in FIGS. 1 and 2 . Instead, edge 108 extending laterally from die 102 provides space for redistribution layer 202 including its conductive traces and vias 112 drilled through edge 108 . Thus, by using the semiconductor device 100, a space saving is achieved in the vertical direction (Z height) relative to the semiconductor device 500 shown in FIG. 5 (requiring a larger mold cap 510 and substrate 506). Additionally, semiconductor device 100 shown in FIG. 1 includes relatively direct connections (without intermediate substrate 506 ) through vias 112 between each of dies 102 . This arrangement provides direct and thus faster and more reliable data transmission between the die 102 and the ball grid array 114 (see FIG. 2 ) associated with the redistribution layer 202 of the first die 104 .

Referring now to FIG. 6 , a Z-height comparison table is provided for various semiconductor devices having structures provided herein, such as those shown with device 100 of FIGS. 1 and 2 . As described herein, semiconductor device 100 includes one or more die assemblies 201 each having die 102 , edge 108 , and one or more vias extending through edge 108 to redistribution layer 202 . The Z-height 602 of each die assembly and the corresponding molding compound used in the edge 108 of each die assembly is shown in the "Semiconductor Device with Via in Edge" row of the table. The total Z height 602 corresponds to the number of stacked die assemblies 201 (each having a height of approximately 25 microns and the mold compound having a height of 10 microns) for a particular package type. The semiconductor devices 100 are arranged in ascending order, ie, a first device including a single die package (single die package, or SDP), a second device with two die packages (dual die package, DDP), and so on (e.g., QDP includes four components, ODP includes eight components, and HDP includes 16 components).

The corresponding Z-height 604 of the semiconductor device including the wire bonds and the substrate (see semiconductor device 500 shown in FIG. 5 ) is provided in the first row of the table. As shown, the die assembly Z-height of the wire bonded device is 25 microns, and the die cap and pitch Z-height of each die assembly varies depending on the number of die assemblies of the device. The bottom row shows the total Z-height for each device, based on the die assembly Z-height and die cap and pitch Z-height multiplied by the number of die assemblies for the device.

As shown in FIG. 6 , with respect to the corresponding overall Z-height of a corresponding device having the arrangement shown in FIG. The total Z-height 602 of each of the devices out of the redistribution layer 202 is smaller. The savings in Z-height of each of the respective die assemblies 201 is transferred to the stacked semiconductor device 100 having two or more die assemblies. That is, a device including more than two dies (eg, die assembly 201 ) having structures described herein increases relative to a corresponding die assembly used in a package using wire bonds, mold caps, and substrates. The Z height of each of the stacked die assemblies 201 is saved.

FIG. 7 illustrates one example of a method 700 for fabricating a stacked semiconductor device, such as semiconductor device 100 previously described herein. In describing method 700, reference is made to one or more components, features, functions, etc. described herein. Where convenient, reference has been made to parts and features with reference numerals. Reference numerals are exemplary rather than exclusive. For example, components, features, functions, etc., described in method 700 include, but are not limited to, correspondingly numbered elements, other corresponding features (numbered or unnumbered) described herein, and their equivalents.

At 702 , method 700 includes forming edge 108 on first die 104 and second die 106 . Edge 108 extends laterally away from first and second die 104 , 106 . For example, as shown in FIG. 1 , a plurality of edges 108 extend from each of the respective dies in an edge lateral extension 110 .

At 704 , the second die 106 is stacked on the first die 104 . For example, as shown in FIG. 2 , die assemblies 201 including respective dies 102 and respective redistribution layers 202 are coupled together, eg, in a stacked configuration. In one example, stacking a die such as the second die 106 on the first die 104 includes applying an adhesive to at least the surface between the first and second die 104, 106 to form a bond between the laminated structures. Bond the dies together accordingly.

At 706 , one or more via holes 112 are drilled through edge 108 after stacking die assemblies 201 in the structure shown in FIG. 2 . One or more vias 112 extend at least between the first and second dies 104 , 106 . In another example, method 700 includes drilling through edge 108 prior to stacking, for example, while holding plurality of dies 102 within a panel frame such as panel frame 304 shown at stage 303 in FIG. One or more vias 112 . The plurality of dies 102 are then arranged in the stack and the corresponding vias 112 are aligned in such a way that the plurality of dies 102 (eg, die assembly 201 ) are aligned relative to each other. After drilling one or more vias 112 , for example by vapor deposition, sputtering, or electroplating, a conductive material is applied through the vias 112 to interconnect the dies 102 accordingly. For example, plurality of vias 112 provides interconnection through redistribution layer 202 associated with each of dies 102 .

Additionally, in another example, one or more vias 112 provide interconnection between die 102 and ball grid array 114 along redistribution layer 202 associated with first die 104 .

Referring now to FIG. 8 , another example of a method 800 for fabricating a stacked semiconductor device 100 is provided. In describing method 800, reference is made to one or more components, features, functions, etc. described herein. Where convenient, reference has been made to parts and features with reference numerals. Reference numerals are exemplary rather than exclusive. For example, components, features, functions, etc., described in method 800 include, but are not limited to, correspondingly numbered elements, other corresponding features (numbered or unnumbered) described herein, and their equivalents.

Referring again to FIG. 8 , at 802 , method 800 includes sorting die 302 to obtain a plurality of operational dies, such as operational die 306 shown at stage 303 in FIG. 3 . A plurality of operational dies 306 are probed or tested to determine their operability. At 804, at least the first reconstituted die panel 308 is formed.

In one example, at 806 , forming the first reconfigured die panel (and additional die panels) includes arranging the picked plurality of operable dies 306 within the panel frame 304 . In another example, picked operable dies 306 are arranged within a non-circular panel frame, such as panel frame 400 shown in FIG. 4 . At 808 , resin is molded around the plurality of operational dies 306 within the panel frame 304 (or panel frame 400 ) to form a first reconstituted die panel 308 . As previously described herein, edges 108 are formed within the resin and extend laterally from each of plurality of operable dies 306 .

In one example, at 804, the process used to form the reconstituted die panels is repeated for additional die panels to thereby produce a plurality of reconstituted die panels 312 or 404. As previously described herein, multiple reconstituted die panels are then stacked into a stacked panel assembly 316 and the corresponding square or non-circular configuration shown in FIG. A stacked series of dies 102 is provided for each of the resulting semiconductor devices 100 .

While in the stacked panel assembly 316 , for example as shown in stage 307 of FIG. 3 , a plurality of vias 112 are formed through the associated edge 108 of each die in the die assembly 201 included in the semiconductor device 100 . For example, in the stacked panel assembly 316 shown at 307 , multiple vias 112 are formed in a batch process to correspondingly reduce the time required to generate the vias 112 when the semiconductor devices 100 are otherwise discrete. After the vias 112 are formed, the semiconductor device 100 is cut from the stacked panel assembly 316 to form the semiconductor device 100 shown at stage 309 in FIG. 3 and shown in further detail in FIGS. 1 and 2 .

Additionally, in another example, ball grid arrays 114 (shown in FIGS. 1 and 2 ) are provided in association with each of semiconductor devices 100 while semiconductor devices 100 are still part of stacked panel assembly 316 . connected first die 104 . In another example, the vias 112 and the ball grid array 114 associated with each of the semiconductor devices 100 are formed after the semiconductor devices are diced from the stacked panel assembly 316 .

FIG. 9 shows another example of a semiconductor device 900 including a plurality of dies 102 with respective edges 904 . As shown in FIG. 9 , dies 102 are provided in an interleaved structure (eg, a shifted or stepped structure). For example, each of die assemblies 902 is displaced relative to each other to form an interleaved series of dies in semiconductor device 900 . As shown in FIG. 9 , each of dies 102 is displaced relative to each other to expose at least one side including one or more bond pads 905 of each of dies 102 . In one example, each die 102 is displaced, eg, according to a die shift 906 that accordingly staggers the die relative to adjacent dies, respectively. In another example, the die 102 is displaced at different levels (and optionally in different directions) to correspondingly expose one or more bond pads 905 according to the displacement. That is, one or more dies 102 are displaced in one or more greater or lesser steps or in different directions depending on the position of the respective bond pads 905 .

As shown in FIG. 9 , each of the dies is staggered in the same direction that provides the staggered structure (staircase) to expose each of the dies 102 accordingly (except the bottommost die 102 of the semiconductor device 900 other than the corresponding bond pad 905. Each of dies 102 is included in a respective die assembly 902 as previously described herein. As shown, each of die assemblies 902 includes dies 102 and one or more corresponding edges 904 of each of dies 102 .

As further shown in FIG. 9 , each of the plurality of dies 102 is bonded to each other, eg, with an adhesive 908 provided on a surface facing adjacent dies 102 . Adhesive 908 holds each of dies 102 in a staggered configuration and correspondingly maintains die displacement 906 (an example of die displacement) as shown in FIG. remain in the exposed structure for final interconnection. In one example, the plurality of dies 102 are bonded together using adhesive 908 prior to application of a molding compound, such as molding compound 200 previously shown in FIG. 2 . As previously described, molding compound 202 cures into a dielectric polymer and accordingly provides edge 904 for each of die assemblies 902 . After bonding each of the dies 102 , a molding compound 202 is applied around the stacked dies 102 to form intermediate stages of the semiconductor device 900 accordingly.

One or more vias 912 are drilled through one or more edges 904 to respectively provide an interconnection between the die 102 and a corresponding redistribution layer 910 with adjacent ball grid array 114 associated with one or more dies 102 (eg, the bottommost die shown in FIG. 9 ). As shown in FIG. 9 , each of the vias 912 is coupled with a corresponding bond pad 905 for respectively covering the die 102 . A plurality of vias 912 associated with each of dies 102 respectively extend from bond pads 905 through one or more edges 904 associated with the respective die assembly 902 . That is, the uppermost die 102 of the semiconductor device 900 includes one or more vias 912 extending through respective edges of the lower die 102 .

After forming vias 912 (eg, by mechanical drilling, photolithography, laser drilling, etc.), a redistribution layer 910 similar to redistribution layer 202 shown in FIG. 2 is provided for at least one die 102. , for example corresponding to the die 102 at the bottom of the semiconductor device 900 adjacent to the ball grid array 114 . In one example, redistribution layer 910 provides a fan-out structure of conductive traces extending over the footprint of die 102 and the corresponding total footprint of stacked die 102 . That is, as shown in FIG. 9 , a redistribution layer 910 extends beneath each of dies 102 and provides conductive traces for interconnecting with vias 912 extending from dies 102 to A respective bond pad 905 for each of the dies extends across edge 904 . In another example, after the redistribution layer 910 is formed, the ball grid array 114 is applied to the semiconductor device 900 along the redistribution layer 910 to provide input and output connections of the semiconductor device 900 .

Referring now to FIG. 10 , another example of a method for forming a semiconductor (eg, semiconductor device 900 shown in FIG. 9 ) is provided. As with the method previously described and shown in FIG. 5 , the method is shown in a series of schematic stages 1001 , 1003 , 1005 , 1007 . At 1001, a plurality of dies 102 cut from one or more monolithic semiconductor wafers are tested for operability. Operable dies 102 (without defects or damage) are then assembled into die stack 1002 . For example, dies 102 of one or more die stacks 1002 are bonded. As shown in stage 1001, the die stack 1002 has a staggered structure (staircase, shifted, etc.) that correspondingly exposes bond pads at at least one surface of each of the dies 102 of the die stack 1002. Disc 905. As described above, in another example, the die 102 is displaced in one or more different levels or directions depending on the location and number of respective bond pads 905 .

Referring now to stage 1003 in FIG. 10 , each of the die stacks 1002 is disposed within a panel frame 1004 comprising a die stack 1004 sized and shaped to accommodate each of the die stacks 1002 . series cavity. After the die stacks 1002 are positioned within the cavities of the panel frame 1004, molding compound is applied around the plurality of die stacks 1002 within the panel frame 1004 to form the die assembly 902 previously shown in FIG. Edge 904. As described herein, in one example, molding compound 202 is a resin that forms a dielectric polymer with a lower modulus of elasticity than the material of the die (eg, silicon). Combined with the panel frame 1004, a reconstituted die panel 1006 is formed that includes a plurality of molded die stacks. Stage 3 shows a circular (wafer-shaped) panel frame 1004 . In another example, the panel frame has a different shape such as rectangle or square as shown in FIG. 4 .

As shown in stage 1003 , die assembly 902 formed from die stack 1002 includes edges 904 extending laterally from each of dies 102 . As shown in this structure, die stack 1002 is interleaved within mold compound 202 . Each of the edges 904 of the respective die 102 varies in lateral dimension accordingly in accordance with the offset position of each of the dies 102 within the die stack 1002 . The bond pads 905 exposed by the displacement of the die face the bottom of the die stack 1002 towards the edge 904 of the underlying die 1002 (as shown in FIG. 10 ).

At stage 1005 , a plurality of vias 912 are drilled into edge 904 under bond pads 905 to interconnect each of dies 102 with redistribution layer 910 provided along one of dies 102 . For example, in the example shown in FIG. 10 , the bottommost die (shown as the uppermost die in this inverted configuration) is provided with a redistribution layer 910 . Optionally, prior to forming the conductive traces of the redistribution layer 910, a plurality of vias 912 are drilled into the edge 904 to correspondingly form channels that will accommodate conductive material for interconnection with the subsequently formed redistribution layer 910 . A conductive material is applied to the channels of the vias 912 to ultimately interconnect the plurality of dies 102 of the die stack 1002 with the redistribution layers of the semiconductor device 900 . In another example, the redistribution layer 910 is formed prior to the drilling of the via holes 912 .

At stage 1007 , semiconductor device 900 is completed by applying ball grid array 114 to redistribution layer 910 previously formed at stage 1005 . As shown at stage 1007 , semiconductor devices 900 are then singulated from reconstituted die panel 1006 . Multiple semiconductor devices 900 are diced from the same reconstituted die panel 1006 .

As with the aforementioned semiconductor device 100, the semiconductor device 900 shown in FIGS. direct connection. Multiple vias 912 provide a direct connection to redistribution layer 910 without the need for an additional larger mold cap to accordingly contain and encapsulate the substrate (larger than the redistribution layer) extending from each of the dies to beneath the die stack. distribution layer 910) for multiple wire bonds. The staggered configuration of die stack 1002 exposes bond pads 905 of one or more dies 102 and thereby allows vias 912 extending from bond pads 905 through edge 904 to connect each of the corresponding dies 102 The dies are interconnected with the redistribution layer 910 . The direct connection between the bond pad 905 and the redistribution layer provided by the via 912 is compared to an otherwise deeper (thicker) mold cap required to reliably encapsulate the leads, such as 504 shown in FIG. Allows for a shallow layer of molding compound.

In addition, since the drilling through the semiconductor device 900 is done through the softer material (lower modulus of elasticity) of the mold compound 202 compared to the harder material of the silicon of the die 102, as previously described, by The vias 912 are provided through the molding compound 202 (dielectric polymer) such that damage to the semiconductor device 900 is minimized. Additionally, with the method shown in FIG. 10 , the process of forming redistribution layer 901 is isolated from one of dies 102 of die stack 1002 . For example, a redistribution layer 910 is provided to the bottommost die 102 of the die stack 1002 as described herein. Thus, vias 912 extend through lateral edges 904 of dies 102 of die stack 1002 to redistribution layer 910 associated with the bottommost die 102 . Redistribution layer 910 thus consolidates the interconnection of each of the plurality of redistribution layers otherwise associated with each die 102 into a single redistribution layer that also provides interconnection to ball grid array 114 . In another example, the bottommost die 102 includes a plurality of redistribution layers (eg, a plurality of adjacent layers 910 ) localized to the die, while the remaining die of the die 102 covering the bottommost die 102 Interconnect with via 912 . In another example, dies 102 each include a respective redistribution layer 910 , and dies 102 are interconnected with vias 912 through redistribution layer 910 .

An example of an electronic device using a semiconductor device 100, 900 as described in the present disclosure is included to illustrate an example of a higher level device application of the present disclosure. 11 is a block diagram of an electronic device 1100 that includes at least one semiconductor device constructed using fabrication methods and structures in accordance with at least one embodiment of the present disclosure. Electronic device 1100 is just one example of an electronic system using embodiments of the present disclosure. Examples of electronic device 1100 include, but are not limited to, personal computers, tablet computers, mobile phones, gaming devices, MP3 or other digital music players, and the like. In this example, electronic device 1100 includes a data processing system that includes a system bus 1102 to couple various components of the system. The system bus 1102 provides communication links among the various components of the electronic device 1100 and may be implemented as a single bus, a combination of buses, or in any other suitable manner.

Electronic components 1110 are coupled to system bus 1102 . Electronic assembly 1110 may include any circuit or combination of circuits. In one embodiment, the electronics assembly 1110 includes a processor 1112 which may be of any type. As used herein, "processor" means any type of arithmetic circuitry, such as, but not limited to, microprocessors, microcontrollers, Complex Instruction Set Computing (CISC) microprocessors, Reduced Instruction Set Computing (RISC) microprocessors processor, very long instruction word (VLIW) microprocessor, graphics processor, digital signal processor (DSP), multi-core processor, or any other type of processor or processing circuit.

Other types of circuits that may be included in electronic assembly 1110 are custom circuits, application specific integrated circuits (ASICs), etc., for example, for one or more circuits (such as communication circuits 1114) in a wireless device, such as a mobile Telephones, personal digital assistants, portable computers, two-way radios and similar electronic systems. An IC may perform any other type of function.

Electronic device 1100 (e.g., a drive such as a solid-state drive or flash memory) may also include external memory 1120, which in turn may include one or more memory elements suitable for a particular application, such as a main memory in the form of random access memory (RAM). Memory 1122, one or more hard drives 1124, or one or more drives that manage removable media 1126 such as compact discs (CDs), flash memory cards, digital video discs (DVDs), and the like.

Electronic device 1100 may also include one or more display devices 1116, one or more speakers 1118, a keyboard or controller 1130, which may optionally include a mouse, trackball, touch screen, voice recognition device, or Any other device that allows a system user to enter information into and receive information from electronic device 1100 .

To better illustrate the methods and apparatus disclosed herein, a non-limiting list of examples is provided here:

Example 1 is an apparatus directed to a method for fabricating a stacked semiconductor device, comprising: forming an edge on a first die and a second die, the edge extending laterally away from the first and second die; A second die is stacked on the first die; and after stacking, one or more vias are drilled through the edge, the one or more vias extending between the first and second dies.

In Example 2, the subject matter of Example 1 can optionally include filling the one or more vias with a conductive material to electrically interconnect the first and second dies.

In Example 3, the subject matter of any of Examples 1-2 can optionally include wherein forming the edge includes forming a dielectric portion over the first die and the second die, forming the edge with the dielectric portion .

In Example 4, the subject matter of any one of Examples 1-3 can optionally include wherein forming the dielectric portion includes molding resin around the first die and the second die, forming the edge with the resin.

In Example 5, the subject matter of any one of Examples 1-4 can optionally include forming a first reconstituted die panel comprising a first reconstituted die panel molded in a panel frame. a plurality of dies, the first plurality of dies comprising a first die; and forming a second reconstituted die panel comprising a second reconstituted die panel molded in another panel frame a plurality of dies, the second plurality of dies including the second die; and forming the edge includes surrounding peripheries of the dies in the first and second reconstituted die panels with a dielectric material.

In Example 6, the subject matter of any one of Examples 1-5 can optionally include sorting dies of the first and second plurality of dies to ensure that only operable Dies are used to form first and second reconstituted die panels.

In Example 7, the subject matter of any one of Examples 1-6 can optionally include separating the individual stacks of the first and second bonded dies from the first and second reconstituted die panels.

In Example 8, the subject matter of any one of Examples 1-7 can optionally include: wherein drilling the one or more vias consists of one or more of laser drilling, mechanical drilling, or chemical etching .

In Example 9, the subject matter of any one of Examples 1-8 can optionally include wherein the one or more vias drilled through the first and second dies are continuous.

In Example 10, the subject matter of any one of Examples 1-9 can optionally include: forming one or more of the conductive traces on one or more of the first or second die or the edge In the redistribution layer, one or more vias communicate with the conductive traces at the edge.

In Example 11, the subject matter of any one of Examples 1-10 can optionally include wherein stacking the first die on the second die includes interleaving the second die relative to the first die such that At least one bond pad of the second die is exposed.

In Example 12, the subject matter of any one of Examples 1-11 can optionally include: wherein drilling the one or more vias comprises drilling at least one via through an edge of the first die, the At least one via extends to at least one bond pad of the second die.

In Example 13, the subject matter of any one of Examples 1-12 can optionally include: a method for fabricating a stacked semiconductor device comprising: sorting out a plurality of operable ones of the die, for multiple The operability of the operable dies is tested; and forming at least a first reconfigured die panel includes: arranging the picked plurality of operable dies in a panel frame, and the plurality of operable dies in the panel frame Resin is molded around the core to form the first reconstituted die panel, with resin formed edges extending laterally from each of the plurality of operable dies.

In Example 14, the subject matter of any one of Examples 1-13 can optionally include repeating arranging and molding to form a second reconstituted die panel, the edges extending laterally away from the second reconstituted tube Each of the plurality of operable dies of the core panel.

In Example 15, the subject matter of any one of Examples 1-14 can optionally include: coupling the first reconstituted die panel to the second reconstituted die panel; One or more vias are drilled in the reconstituted die panel, one or more vias are within the edges of the plurality of operable dies, and one or more vias are drilled between the first and second reconstituted die panels extended.

In Example 16, the subject matter of any one of Examples 1-15 can optionally include wherein coupling the first reconstituted die panel to the second reconstituted die panel comprises coupling the first and second reconstituted The plurality of operable dies of each of the die panels are aligned.

In Example 17, the subject matter of any one of Examples 1-16 can optionally include: dividing the first and second reconstituted die panels into a plurality of multilayer packages, each of the multilayer packages comprising: At least two of the plurality of operable dies of the first and second reconfigurable die panels, and at least one of the one or more vias.

In Example 18, the subject matter of any one of Examples 1-17 can optionally include: wherein drilling the one or more vias in the coupled first and second reconfigured die panels includes passing through multiple Drill one or more vias from the edge of an operable die.

In Example 19, the subject matter of any one of Examples 1-18 can optionally include filling the one or more vias with a conductive material to electrically couple the first and second reconstructed die panels.

In Example 20, the subject matter of any one of Examples 1-19 can optionally include wherein forming at least a first reconstituted die panel comprises forming conductive traces over a plurality of operable dies and corresponding edges One or more redistribution layers of lines, and one or more vias communicate with the conductive traces at the edge.

In Example 21, the subject matter of any one of Examples 1-20 can optionally include wherein arranging the picked plurality of operable dies within a panel frame includes arranging the picked plurality of operable dies in In the one or more interleaved die stacks within the panel frame, each of the one or more interleaved die stacks includes two or more dies, and the two or more tubes At least one of the cores is interleaved with adjacent dies.

In Example 22, the subject matter of any one of Examples 1-21 can optionally include wherein molding resin around a plurality of operable dies includes each of the one or more interleaved die stacks A surrounding molded resin.

In Example 23, the subject matter of any one of Examples 1-22 can optionally include: a semiconductor device comprising: a first die; a second die stacked on the first die; extending laterally off the edge of each of the first and second dies; the first redistribution layer extending over the first die and the edge of the first die; and one of at least one of the edges extending through the respective edges One or more vias communicate with the first and second die through the edge.

In Example 24, the subject matter of any one of Examples 1-23 can optionally include: wherein the respective edges are molded resin edges molded around the respective first and second dies, one or A plurality of vias extend through at least one of the molded resin edges.

In Example 25, the subject matter of any one of Examples 1-24 can optionally include a dielectric portion formed over each of the first and second dies, the dielectric portion comprising one or more edges, and One or more vias extend through the dielectric portion.

In Example 26, the subject matter of any one of Examples 1-25 can optionally include wherein the one or more vias are spaced laterally from the first and second dies.

In Example 27, the subject matter of any one of Examples 1-26 can optionally include a second redistribution layer extending over the second die and an edge of the second die.

In Example 28, the subject matter of any one of Examples 1-27 can optionally include the first and second redistribution layers providing a fan-out structure of conductive traces between the first and second Extending over and beyond the respective footprints of the die, and the one or more vias communicate with the first and second redistribution layers.

In Example 29, the subject matter of any one of Examples 1-27 can optionally include wherein the via is on at least one of the corresponding edges after stacking the second die on the first die Drilled vias formed in one.

In Example 30, the subject matter of any one of Examples 1-29 can optionally include a plurality of dies comprising first and second dies, an edge extending laterally from each of the plurality of dies, The plurality of dies are in a stack, and the one or more vias extend through at least two of the respective edges of the plurality of dies.

In Example 31, the subject matter of any one of Examples 1-30 can optionally include wherein the second die is interleaved with the first die, the second die includes at least one exposed bond pad dependent on the interleaving plate.

In Example 32, the subject matter of any one of Examples 1-31 can optionally include wherein one or more vias extend through an edge of the first die to at least one exposed bond of the second die pad.

Each of these non-limiting examples stands alone or can be combined with one or more of the other examples in any permutation or combination.

The above Detailed Description includes references to the accompanying drawings, which form a part of the Detailed Description. By way of illustration, the drawings show specific embodiments in which the disclosure may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate using, with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein, the use of Examples of any combination or permutation of those elements (or one or more aspects thereof).

In this document, as is common in patent documents, the term "a" is used to include one or more than one, independently of any other instance or use of "at least one" or "one or more". In this document, the term "or" is used to denote a non-exclusive or such that "A or B" includes "A but not B", "B but not A" and "A and B", unless otherwise indicated. In this document, the terms "including" and "wherein" are used as the plain-language equivalents of the respective terms "comprising" and "wherein." Likewise, in the following claims, the terms "comprises" and "comprises" are open ended, i.e., systems, devices, articles of manufacture, components, The formula, or process is still considered to fall within the scope of the claims. Furthermore, in the following claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

The foregoing description is intended to be illustrative and not limiting. For example, the examples described above (or one or more aspects thereof) may be used in conjunction with each other. For example, other embodiments may be utilized by one of ordinary skill in the art after reading the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b) and will enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together in order to simplify the disclosure. This should not be interpreted as saying that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations and permutations. The scope of the disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.

Claims (23)

1. A semiconductor assembly comprising: A first die assembly, the first die assembly comprising: a first die having a first die upper surface and a first die lower surface, and a first edge laterally extending from the first die, wherein the first edge includes a first upper edge face proximate to an upper surface of the first die and a first lower edge face proximate to a lower surface of the first die an edge face, the first die lower surface and the first lower edge face proximate input and output arrays of the semiconductor component; a second die assembly over the first die assembly, the second die assembly comprising: a second die having a second die upper surface and a second die lower surface, Extending laterally away from a second edge of the second die, wherein the second edge includes a second upper edge face proximate to an upper surface of the second die and a first edge face proximate to a lower surface of the second die two lower edge faces, and a plurality of conductive traces extending outward beyond the second die toward the second lower edge face; wherein at least the first upper edge surface is the uppermost surface of the first die assembly and the second lower edge surface is the lowermost surface of the second die assembly, and the plurality of conductive traces interposed between said first upper edge face and said second lower edge face; and one or more vias extending through at least one of the first edge and the second edge, the one or more vias passing through the plurality of conductive traces and the first edge or the At least one of the second edges is in communication with the first die and the second die. 2. The semiconductor assembly of claim 1, wherein the first edge and the second edge are molding resin molded around the respective first and second dies. 3. The semiconductor assembly of claim 1 , comprising a dielectric portion formed over each of the first die and the second die, the dielectric portion comprising one or more edges , the one or more vias extending through the dielectric portion. 4. The semiconductor assembly of claim 1, wherein the one or more vias are laterally spaced apart from the first die and the second die. 5. The semiconductor assembly of claim 1, wherein the plurality of conductive traces provide a fan-out structure of conductive traces extending beyond a footprint of the second die. 6. The semiconductor assembly of claim 1, wherein the vias are formed in at least one of the respective edges after stacking the second die on the first die drilled vias. 7. The semiconductor assembly of claim 1 , comprising a plurality of dies including the first die and the second die, an edge extending laterally from each die of the plurality of dies, The plurality of dies form a stack, and the one or more vias extend through at least two of respective edges of the plurality of dies. 8. The semiconductor assembly of claim 1 , wherein the second die is staggered relative to the first die, the second die including at least one exposed bond pad dependent on the staggering . 9. The semiconductor assembly of claim 8, wherein the one or more vias extend through the edge of the first die to the at least one exposed bond of the second die pad. 10. The semiconductor assembly of claim 1, wherein the first die assembly includes a further plurality of conductive traces extending outward beyond the first die and toward The first edge extends. 11. The semiconductor assembly of claim 1, wherein the second lower edge face of the second die is flush with the second die lower surface. 12. The semiconductor assembly of claim 1, wherein the second upper edge face is located above the second die upper surface of the second die. 13. The semiconductor assembly of claim 2, wherein the molding resin extends over one or more of the first die or the second die. 14. The semiconductor assembly of claim 1 , wherein at least a first portion of the plurality of conductive traces is located under the second die and a second portion of the plurality of conductive traces is located under the second die. Below the two edges. 15. A method for manufacturing a semiconductor component, comprising: forming a first die assembly comprising: A first edge is formed on the first die, the first edge extends laterally from the first die, and the first edge includes an exposed edge near a first die upper surface of the first die. upper edge face; forming a second die assembly comprising: A second edge is formed on the second die, the second edge extends laterally from the second die, and the second edge includes an exposed edge near a second die lower surface of the second die. the lower edge face, and forming a plurality of conductive traces extending beyond the second die to the exposed lower edge face; layering the exposed lower edge side of the second die assembly over the exposed upper edge side of the first die assembly, the plurality of conductive traces intervening on the exposed between the upper edge face and said exposed lower edge face; and forming one or more vias extending through at least one of the first edge and the second edge, the one or more vias in communication with the first die and the second die . 16. The method of claim 15, wherein forming the first edge and the second edge comprises molding a dielectric portion over the first die and the second die, using the dielectric portion to form the the first edge and the second edge. 17. The method of claim 15, comprising: forming a first reconstituted die panel including a first plurality of dies molded in a panel frame, the first plurality of dies including the first die, and forming a second reconstituted die panel including a second plurality of die molded in another panel frame, the second plurality of die including the second die panel ;as well as Forming the first and second edges includes surrounding peripheries of dies in the first and second reconstituted die panels with a dielectric material. 18. The method of claim 17 , comprising sorting the dies of the first plurality of dies and the second plurality of dies to ensure that only operable dies are used to form the The first reconfigured die panel and the second reconstituted die panel. 19. The method of claim 17, comprising separating separate assemblies of the first die and the second die from the first reconstituted die panel and the second reconstituted die panel . 20. The method of claim 15, wherein forming the one or more vias consists of one or more of laser drilling, mechanical drilling, or chemical etching. 21. The method of claim 15, wherein forming the one or more vias comprises forming one or more continuous vias through each of the first edge and the second edge . 22. The method of claim 15 , comprising forming a further plurality of conductive traces extending beyond the first die to the first edge, the one or more Vias communicate with the plurality of conductive traces of each of the first die assembly and the second die assembly. 23. The method of claim 15, wherein laminating the exposed lower edge side of the second die assembly over the exposed upper edge side of the first die assembly comprises Staggering the second die relative to the first die exposes at least one bond pad of the second die.