CN107579009A - A kind of multi-chip laminated packaging structure and preparation method thereof - Google Patents

Abstract

The invention discloses a multi-chip stacked packaging structure and a manufacturing method thereof. The stacked packaging structure includes at least two double-chip stacked packages stacked sequentially from bottom to top, and the double-chip stacked package includes a wire-bonded chip. , flip chip, passivation layer, rewiring layer, bonding wire and vertical array leads, the flip chip is bonded to the wire bonded chip and the two are injection molded together to form a plastic package, the upper surface of the plastic package A passivation layer is also provided on the lower surface and the rewiring layer is arranged between the plastic package and the passivation layer, and the electrical interconnection of the wire bonded chip and the flip chip is realized through the bonding wire and the vertical array lead. The invention reduces the total volume of the multi-chip package, reduces the thickness of the package, the upper and lower interconnections are completed through vertical array leads, the manufacturing process is simple, and the cost is low.

Description

A multi-chip stacked package structure and manufacturing method thereof

technical field

The invention belongs to the technical field of integrated circuit packaging, and in particular relates to a multi-chip stacked packaging structure and a manufacturing method thereof.

Background technique

With the rapid development of semiconductor integrated circuits, the functional requirements of integrated circuits are increasing, and the demand for multi-chip interconnection to improve integration is becoming more and more prominent. At the same time, in order to meet the needs of miniaturization and light weight, three-dimensional stacked packaging meets the above needs. develop quickly.

Three-dimensional stack packaging can increase the packaging density, reduce the interconnection length between chips, improve the operation performance of integrated circuits, and realize functional diversification through the combination of multiple chips. At present, in order to complete the vertical interconnection in the three-dimensional stacked package, through-silicon vias (TSVs) are generally used to realize the three-dimensional vertical interconnection. The stacking density is the largest and the external dimension is the smallest, but the process cost is relatively high. In addition, there is no good solution on how to accomplish the vertical stacking of wire-bonded chips and flip-chip chips in a three-dimensional structure.

Contents of the invention

In order to solve the above technical problems, the present invention provides a multi-chip stacked packaging structure and a manufacturing method thereof.

In order to achieve the above object, technical scheme of the present invention is as follows:

The present invention provides a multi-chip stacked package structure, which includes at least two double-chip stacked packages stacked sequentially from bottom to top. The double-chip stacked package includes a wire-bonded chip, a flip-chip chip, a passivation layer, Rewiring layer, bonding wire and vertical array leads, flip chip bonding on the wire bonding chip and the two are injection molded together to form a plastic package, and the upper and lower surfaces of the plastic package are also provided with a passivation layer The rewiring layer is arranged between the plastic package and the passivation layer, and realizes the electrical interconnection of the wire bonding chip and the flip chip through the bonding wire and the vertical array wire.

Preferably, the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer is arranged on the lower surface of the plastic package, and the second passivation layer is arranged on the upper surface of the plastic package; the rewiring layer includes the second A rewiring layer and a second rewiring layer, the first rewiring layer is arranged between the lower surface of the plastic package and the first passivation layer, and the second rewiring layer is arranged on the upper surface of the plastic package and the second passivation layer Between them, the bonding wire is electrically connected between the wire bonding chip and the first rewiring layer, and the vertical array wires are electrically connected between the first rewiring layer and the second rewiring layer.

Preferably, solder pads are further provided on the first redistribution layer and the second redistribution layer, and array bumps are further provided on the solder pads on the second redistribution layer.

Preferably, the pads are circular or square, and the array bumps are columnar or spherical.

Preferably, the size of the wire bonded chip is larger than the size of the flip chip.

Preferably, the wire bonded chip and the flip chip are bonded together by insulating glue.

The present invention also provides a method for manufacturing a multi-chip stacked packaging structure, comprising the following steps:

S1. Select the first carrier wafer, and make or mount a layer of temporary bonding mold on the upper surface of the first carrier wafer;

S2, making a passivation layer and a rewiring layer;

S3. Mount the back of the wire-bonded chip on the passivation layer, and then mount the back of the flip-chip on the front of the wire-bonded chip with insulating glue;

S4. Use bonding wires to bond wire-bonded chips, and then perform vertical bonding at the array position on the rewiring layer to form vertical array leads, and the height of the leads is higher than the highest level of the flip chip;

S5. Using an injection molding process to fix the wire-bonded chip, the flip-chip chip and all the leads to form a plastic package;

S6. Polish the excess solder balls and vertical array leads outside the plastic package to make it smooth, and make a rewiring layer and a passivation layer on the upper surface of the plastic package to complete the electrical interconnection of the two chips, and then make an array pad by electroplating. Finally, a two-chip stacked package is formed;

S7. A flip-chip bonding process is used to sequentially stack multiple independent double-chip stacked packages together from bottom to top to complete a multi-chip stacked package structure.

Preferably, the vertical array lead material in step S4 is copper wire.

Preferably, the wafer-level rewiring process is used in step S2, and the injection molding process in step S5 is powder injection molding.

Preferably, after making the array pads in step S6, wafer-level ball planting technology or electroplating technology is used to make spherical or columnar array bumps on the pads on the upper surface of the plastic package to form a complete two-chip stacked package ; Then use a debonding method to peel off the two-chip stacked package and the temporary bonding film, and then form a plurality of independent double-chip stacked packages by scribing the wafer.

The present invention has the following beneficial effects:

1. The upper and lower surfaces of each two-chip stacked package are interconnected through vertical array leads, which is relatively low in cost compared with the through-silicon via (TSV) process;

2. The size of the wire-bonded chip in each double-chip stacked package is larger than that of the flip-chip, which can realize the simultaneous integration of multiple flip-chips and wire-bonded chips in one package;

3. The front side of the wire-bonded chip and the back side of the flip-chip chip are bonded together, and the vertical direction saves the space where the arc height of the bonding wire exceeds the height of the chip;

4. The rewiring layers on both sides of each two-chip stacked package are manufactured through wafer-level technology, and the entire wafer is processed at the same time, which has high production efficiency and effectively reduces packaging costs;

5. The pads made on the first rewiring layer and the array bumps made on the second rewiring layer can realize three-dimensional stacking of multiple packages with the same structure.

Description of drawings

Fig. 1 is a structural schematic diagram of a multi-chip stacked packaging structure of the present invention after temporarily manufacturing a bonding film on a wafer.

FIG. 2 is a schematic structural view of a multi-chip stacked package structure of the present invention after the first rewiring layer and the first passivation layer are fabricated on the temporary bonding film.

Fig. 3 is a structural schematic diagram of a multi-chip stacked packaging structure of the present invention after mounting wire-bonded chips and flip-chips on the first passivation layer.

FIG. 4 is a structural schematic view of a multi-chip stacked package structure after adding bonding wires and vertical array leads according to the present invention.

FIG. 5 is a structural schematic diagram of a plastic package formed by injection molding on a multi-chip stacked package structure according to the present invention.

FIG. 6 is a structural schematic view of a multi-chip stacked package structure after fabrication of a second rewiring layer, a second passivation layer and pads according to the present invention.

FIG. 7 is a schematic structural view of a single double-chip stacked package after the array bumps on the multi-chip stacked package structure of the present invention are fabricated.

FIG. 8 is a schematic diagram of a stacked structure of a double-chip stacked package of a multi-chip stacked package structure according to the present invention.

Among them, 1. The first passivation layer 1, 2. The first rewiring layer, 3. Wire-bonded chip, 4-flip chip, 5. Bonding wire, 6. Vertical array leads, 7. Plastic package, 8. Second rewiring layer, 9. Second passivation layer, 10. Pad, 11. Array bump, 100. First double-chip stacked package, 200. Second double-chip stacked package, 300 , A third double-chip stacked package.

detailed description

Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

In order to achieve the purpose of the present invention, as shown in FIG. 8 , in one embodiment of the present invention, a multi-chip stack package structure is provided, which includes a third double-chip stack package 300 stacked sequentially from bottom to top, The second two-chip stack package body 200 and the first two-chip stack package body 100, each two-chip stack package body includes a wire-bonded chip 3, a flip-chip chip 4, a passivation layer, a rewiring layer, a bond The wire 5 and the vertical array lead 6, the flip-chip chip 4 is bonded to the wire-bonded chip 3 and the two are injection-molded together to form a plastic package 7, and passivation is also provided on the upper surface and the lower surface of the plastic package 7. The rewiring layer is arranged between the plastic package 7 and the passivation layer, and the electrical interconnection between the wire bonded chip 3 and the flip chip 4 is realized through the bonding wire 5 and the vertical array wire 6 .

Wherein, the passivation layer includes a first passivation layer 1 and a second passivation layer 9, the first passivation layer 1 is arranged on the lower surface of the plastic package 7, and the second passivation layer 9 is arranged on the upper surface of the plastic package 7; The rewiring layer includes a first rewiring layer 2 and a second rewiring layer 8, the first rewiring layer 2 is arranged between the lower surface of the plastic package 7 and the first passivation layer 1, and the second rewiring layer 8 is arranged on Between the upper surface of the plastic package 7 and the second passivation layer 9, the bonding wire 5 is electrically connected between the wire bonding chip 3 and the first rewiring layer 2, and the vertical array leads 6 are electrically connected to the first rewiring layer 2 and the second rewiring layer 8. The first rewiring layer 2 and the second rewiring layer 8 are also provided with pads 10, and the pads 10 on the second rewiring layer 8 are also provided with array bumps 11, and the pads 10 are circular or square. , the array bumps 11 are cylindrical or spherical.

In addition, the size of the wire-bonded chip 3 is larger than that of the flip-chip chip 4 , and the wire-bonded chip 3 and the flip-chip chip 4 are bonded together by insulating glue.

As shown in Figures 1-8, the present invention also provides a method for manufacturing a multi-chip stacked packaging structure, including the following steps:

S1, select the first carrier wafer 13, make or attach a layer of temporary bonding mold 12 on the upper surface of the first carrier wafer 13;

S2. Manufacturing a first passivation layer 1 and a first rewiring layer 2 by using a wafer-level rewiring process;

S3. Mount the back of the wire-bonded chip 3 on the first passivation layer 1, and then mount the back of the flip-chip 4 on the front of the wire-bonded chip 3 with insulating glue;

S4. Use the bonding wire 5 to bond the wire-bonded chip 3, and then perform vertical bonding at the array position on the first rewiring layer 2 to form a vertical array lead 6, and the height of the lead is higher than the highest level of the flip chip. ; Wherein, the material of vertical array lead 6 is copper wire;

S5. Fix the wire-bonded chip 3, the flip-chip chip 4 and all the leads to form a plastic package 7 by using an injection molding process; wherein, the injection molding process is a powder injection molding method;

S6, polishing the excess solder balls outside the plastic package 7 and the vertical array leads 6, and making a second rewiring layer 8 and a second passivation layer 9 on the upper surface of the plastic package 7 to complete the electrical interconnection of the two chips, and then Then the array pads are made by electroplating process, and then the spherical or columnar array bumps are made on the pads located on the upper surface of the plastic package 7 by wafer-level ball planting technology or electroplating technology to form a complete two-chip stacked package ; Then use the debonding method to peel off the two-chip stacked package and the temporary bonding film, and then form a plurality of independent double-chip stacked packages by scribing the wafer;

S7. A flip-chip bonding process is used to sequentially stack multiple independent double-chip stacked packages together from bottom to top to complete a multi-chip stacked package structure.

The above is only the preferred embodiment of the present invention, it should be pointed out that for those skilled in the art, without departing from the inventive concept of the present invention, some modifications and improvements can also be made, and these all belong to the present invention. protection scope of the invention.

Claims (10)

1. A multi-chip stacked package structure, characterized in that it comprises at least two double-chip stacked packages stacked sequentially from bottom to top, and the double-chip stacked package includes a wire-bonded chip, a flip chip, a blunt chip layers, rewiring layers, bonding wires and vertical array leads, the flip chip is bonded to the wire bonded chip and the two are injection molded together to form a plastic package, and the upper surface and the lower surface of the plastic package are also equipped with The passivation layer and the rewiring layer are arranged between the plastic package and the passivation layer, and realize the electrical interconnection of the wire bonding chip and the flip chip through the bonding wire and the vertical array lead. 2. The multi-chip stack package structure according to claim 1, wherein the passivation layer comprises a first passivation layer and a second passivation layer, the first passivation layer is arranged on the lower surface of the plastic package, and the second passivation layer The second passivation layer is arranged on the upper surface of the plastic package; the rewiring layer includes a first rewiring layer and a second rewiring layer, the first rewiring layer is arranged between the lower surface of the plastic package and the first passivation layer, and the second The second rewiring layer is arranged between the upper surface of the plastic package and the second passivation layer, the bonding wire is electrically connected between the wire bonding chip and the first rewiring layer, and the vertical array leads are electrically connected to the first rewiring layer and the second redistribution layer. 3. The multi-chip stack package structure according to claim 2, characterized in that, the first rewiring layer and the second rewiring layer are also provided with pads, and the pads on the second rewiring layer are also An array of bumps is provided. 4 . The multi-chip stack package structure according to claim 3 , wherein the bonding pads are circular or square, and the array bumps are cylindrical or spherical. 5. The multi-chip stack package structure according to claim 1, wherein the size of the wire-bonded chip is larger than that of the flip-chip bonded chip. 6 . The multi-chip stack package structure according to claim 1 , wherein the wire-bonded chip and the flip-chip chip are bonded together by insulating glue. 7. A method for manufacturing the multi-chip stack package structure according to any one of claims 1-6, comprising the following steps: S1. Select the first carrier wafer, and make or mount a layer of temporary bonding mold on the upper surface of the first carrier wafer; S2, making a passivation layer and a rewiring layer; S3. Mount the back of the wire-bonded chip on the passivation layer, and then mount the back of the flip-chip on the front of the wire-bonded chip with insulating glue; S4. Use bonding wires to bond wire-bonded chips, and then perform vertical bonding at the array position on the rewiring layer to form vertical array leads, and the height of the leads is higher than the highest level of the flip chip; S5. Using an injection molding process to fix the wire-bonded chip, the flip-chip chip and all the leads to form a plastic package; S6. Polish the excess solder balls and vertical array leads outside the plastic package to make it smooth, and make a rewiring layer and a passivation layer on the upper surface of the plastic package to complete the electrical interconnection of the two chips, and then make an array pad by electroplating. Finally, a two-chip stacked package is formed; S7. A flip-chip bonding process is used to sequentially stack multiple independent double-chip stacked packages together from bottom to top to complete a multi-chip stacked package structure. 8 . The method for manufacturing a multi-chip stack package structure according to claim 7 , wherein the material of the vertical array leads in step S4 is copper wire. 9 . 9. The manufacturing method of the multi-chip stacked packaging structure according to claim 7, characterized in that the wafer-level rewiring manufacturing process is adopted in step S2, and the injection molding process in step S5 is powder injection molding. 10. The manufacturing method of the multi-chip stacked packaging structure according to claim 7, characterized in that, after the arrayed pads are made in step S6, wafer-level ball planting technology or electroplating technology is used to place the solder on the upper surface of the plastic package. Make spherical or cylindrical array bumps on the disk to form a complete two-chip stacked package; then use the debonding method to peel off the two-chip stacked package and the temporary bonding film, and then form multiple independent stacked packages by dicing the wafer. double chip stack package.