CN107564879A - A kind of fan-out package device - Google Patents
A kind of fan-out package device Download PDFInfo
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- CN107564879A CN107564879A CN201710740313.4A CN201710740313A CN107564879A CN 107564879 A CN107564879 A CN 107564879A CN 201710740313 A CN201710740313 A CN 201710740313A CN 107564879 A CN107564879 A CN 107564879A
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Abstract
The invention discloses a kind of fan-out package device, the device includes：Package substrate, the package substrate includes Silicon Wafer basic unit, pad and the first wiring layer again, and the pad is arranged at Silicon Wafer basic unit side, described first again wiring layer be arranged at the opposite side of the Silicon Wafer basic unit, wherein, the pad and the described first wiring layer electrical connection again；Chip, the chip electrically connect with the pad of the package substrate.By the above-mentioned means, the present invention can prevent chip from shifting, while make again the line width of wiring layer and line-spacing narrower.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out type packaging device.
Background
As the size of the chip is smaller and smaller along with the development of semiconductor technology, the density of I/O (input/output) pins on the surface of the chip is higher and higher, and fan-out type packaging has come to be used, which fans out the high density of I/O pins of the chip into low density of packaging pins.
At present, the existing fan-out packaging method includes the following procedures: providing a carrier plate, attaching a layer of double-sided adhesive film on the carrier plate, attaching the front side of the chip on the adhesive film, carrying out plastic packaging on the chip, stripping the adhesive film and the carrier plate, and forming a rewiring layer, ball planting and cutting on the front side of the chip.
The inventor of the invention finds that the adhesive film is adopted in the fan-out type packaging method, the temperature changes during the plastic packaging of the chip cause the adhesive film to stretch, and the plastic packaging material, the chip and the carrier plate have different Coefficients of Thermal Expansion (CTE) and warp during the plastic packaging, so that the chip generates offset during the plastic packaging. The chip offset causes difficulties in subsequent processes such as photolithography alignment. (ii) a In addition, the rewiring layer of the fan-out package device is limited in narrow line width/pitch.
Disclosure of Invention
The invention mainly solves the technical problem of providing a fan-out type packaging device which can prevent a chip from deviating; and the linewidth and the linedistance of the rewiring layer can be narrower.
In order to solve the technical problems, the invention adopts a technical scheme that: providing a fan-out packaged device, the device comprising: the packaging substrate comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, wherein the bonding pad is arranged on one side of the silicon wafer base layer, the first rewiring layer is arranged on the other side of the silicon wafer base layer, and the bonding pad is electrically connected with the first rewiring layer; a chip electrically connected with the pad of the package substrate.
The invention has the beneficial effects that: different from the situation of the prior art, the packaging substrate in the fan-out type packaging device adopted by the invention comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, wherein the bonding pad and the first rewiring layer are respectively positioned at two sides of the silicon wafer base layer, the bonding pad is electrically connected with the first rewiring layer, and a chip is electrically connected with the bonding pad; on one hand, the packaging substrate comprises a bonding pad, and the chip is electrically connected with the bonding pad of the packaging substrate, so that the conditions that the temperature change of the chip during plastic packaging causes the expansion of a glue film, the warping occurs due to the difference of thermal expansion Coefficients (CTE) of a plastic packaging material, the chip and a carrier plate during plastic packaging, and the like, which are caused by the adoption of a glue film packaging method, and the chip is deviated during plastic packaging are avoided; on the other hand, the packaging substrate comprises a silicon wafer base layer, and the silicon wafer base layer has better thermal conductivity, so that the heat dissipation of the fan-out type packaging device is facilitated; on the other hand, the welding pads of the packaging substrate and the first rewiring layer are positioned on two opposite sides of the silicon wafer base layer, and technical support is provided for subsequently providing a fan-out type packaging structure with a welding ball structure on two sides; in another aspect, the sector packaging method provided by the invention is to fabricate the chip by first fabricating the rewiring layer and then forming the rewiring layer, and the method is narrower in linewidth and linedistance of the rewiring layer than the method of fabricating the chip and then performing rewiring on the chip.
Drawings
FIG. 1 is a schematic flow chart diagram of one embodiment of a fan-out packaging method of the present invention;
FIG. 2 is a top view of one embodiment of a wafer in the field of semiconductor packaging;
FIG. 3 is a schematic structural diagram of one embodiment of a silicon wafer substrate with through-silicon vias;
FIG. 4 is a flow diagram illustrating one embodiment of a fan-out packaging method of the present invention;
FIG. 5 is a schematic diagram of a structure of an embodiment of a fan-out packaged device corresponding to steps S201-S206 in FIG. 4;
FIG. 6 is a schematic diagram of an embodiment of a fan-out packaged device corresponding to steps S207-S217 of FIG. 4;
FIG. 7 is a schematic structural diagram of another embodiment of a fan-out packaged device corresponding to step S207 in FIG. 4;
FIG. 8 is a schematic structural diagram of another embodiment of a fan-out packaged device corresponding to step S217 in FIG. 4;
FIG. 9 is a flow diagram illustrating another embodiment of a fan-out packaging method of the present invention;
FIG. 10 is a schematic diagram of a structure of one embodiment of a fan-out packaged device corresponding to steps S301-S309 of FIG. 9;
FIG. 11 is a schematic structural diagram of another embodiment of a fan-out packaged device corresponding to step S307 in FIG. 9;
FIG. 12 is a flow diagram illustrating another embodiment of a fan-out packaging method of the present invention;
FIG. 13 is a schematic diagram of a structure of one embodiment of a fan-out packaged device corresponding to steps S407-S422 in FIG. 12;
FIG. 14 is a schematic structural diagram of another embodiment of a fan-out packaged device corresponding to step S412 in FIG. 12;
FIG. 15 is a schematic structural diagram of another embodiment of a fan-out packaged device corresponding to step S422 in FIG. 12;
FIG. 16 is a flow diagram illustrating another embodiment of a fan-out packaging method of the present invention;
FIG. 17 is a schematic diagram of a structure of one embodiment of a fan-out packaged device corresponding to steps S507-S519 of FIG. 16;
FIG. 18 is a schematic structural diagram of one embodiment of a fan-out packaged device of the present invention;
FIG. 19 is a schematic structural diagram of another embodiment of a fan-out packaged device of the present invention;
FIG. 20 is a schematic structural diagram of another embodiment of a fan-out packaged device of the present invention;
fig. 21 is a schematic structural diagram of another embodiment of a fan-out packaged device in accordance with the present invention.
Detailed Description
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a fan-out packaging method according to an embodiment of the present invention, the method including:
s101: and providing a packaging substrate, wherein the packaging substrate comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, the bonding pad is arranged on one side of the silicon wafer base layer, the first rewiring layer is arranged on the other side of the silicon wafer base layer, and the bonding pad is electrically connected with the first rewiring layer.
In one application scenario, the silicon wafer substrate may be directly provided with the bonding pads, as shown in fig. 2, and fig. 2 is a top view of an embodiment of the wafer in the semiconductor packaging field. The wafer 10 includes a base layer 120 and a pad 100, the base layer 120 has a front surface and a back surface, the pad 100 is formed on the front surface of the base layer 120, and correspondingly, a first redistribution layer is formed on the back surface of the base layer 120; in this embodiment, the base layer 120 is made of silicon, and the thermal conductivity of silicon is better, so that the thermal dissipation performance of the subsequent fan-out package device can be enhanced.
Specifically, the step S101 includes: providing a silicon wafer substrate provided with bonding pads, namely providing a wafer 10 as shown in FIG. 2; a first redistribution layer and a second redistribution layer are formed on two opposite sides of the silicon wafer substrate, the second redistribution layer is formed on the pad and electrically connected with the pad, that is, the second redistribution layer is formed on the pad 100 on the front side of the substrate 120 as shown in fig. 2, and the first redistribution layer is formed on the back side of the substrate 120.
Since the silicon wafer base layer itself is poor in conductivity, in order to achieve the purpose of electrically connecting the pad with the first redistribution layer, in one embodiment, the state including the silicon wafer base layer is set so that the side thereof having the pad is positioned below before the first redistribution layer is formed; and forming a through silicon via at a position, back to the bonding pad, of the silicon wafer base layer. Referring to fig. 3, one side of the silicon wafer base layer 20 having the bonding pad 22 faces downward, and a through silicon via 24 is formed at a position corresponding to the bonding pad 22 on a side of the silicon wafer base layer 20 opposite to the bonding pad 22 by using a plasma etching method, in other embodiments, the through silicon via may be formed in other manners or the bonding pad may be electrically connected to the first redistribution layer in other manners; in one application scenario, the angle between the side a of the through-silicon via 24 and the side b of the silicon wafer base layer 20 is 60-80 ° (e.g., 60 °, 70 °, 80 °, etc.), and the aspect ratio of the through-silicon via 24 is less than 10:1, i.e., h/d < 10 (e.g., h/d ═ 0.5, 2, 5, 8, 9, etc.).
S102: the chip is electrically connected to the bonding pad of the package substrate.
Specifically, when a second redistribution layer is formed on the pad on the front surface of the silicon wafer substrate, the step S102 is specifically: electrically connecting the chip with the second rewiring layer and electrically connecting the chip with the bonding pad through the second rewiring layer; in an application scene, the chip is provided with the metal salient points, the chip is electrically connected with the second rewiring layer in a mode of reflow soldering of the metal salient points and the second rewiring layer, and the mode can avoid the situation that the position of the chip deviates due to the fact that a glue film is heated and softened in the subsequent chip plastic package process.
The above-described packaging method will be described in further detail below in terms of several specific embodiments.
In a first embodiment, please refer to fig. 4, fig. 4 is a flow chart illustrating a fan-out packaging method according to an embodiment of the present invention; the method comprises the following steps:
s201: providing a silicon wafer base layer provided with a bonding pad; specifically, referring to fig. 5a, in an application scenario, the package substrate includes a silicon wafer substrate 30 directly provided with a bonding pad 32, i.e. a wafer directly accessible by a general packaging and testing factory;
s202: forming a first passivation layer on one side of the silicon wafer base layer, wherein the bonding pad is arranged on the first passivation layer, and arranging a first opening at a position, corresponding to the bonding pad, of the first passivation layer; specifically, referring to fig. 5b, in one embodiment, a first passivation layer 34 is first coated on the surface of the silicon wafer substrate 30, and then a first opening 340 is formed at a position of the first passivation layer 34 corresponding to the pad 32 by exposure, development or other means, so that the pad 32 is exposed; in another embodiment, a dielectric layer (not shown) may be further formed on the surface of the first passivation layer 34 opposite to the silicon wafer substrate 30, and an opening (not shown) is also formed on the dielectric layer at a position corresponding to the pad 34 so as to expose the pad 32.
S203: forming a first seed layer on the surface of the first passivation layer opposite to the silicon wafer base layer; specifically, referring to fig. 5c, in one embodiment, the material of the first seed layer 36 is one or a mixture of titanium, aluminum, copper, gold, and silver, and the process of forming the first seed layer 36 is a sputtering process or a physical vapor deposition process.
S204: forming a first mask layer on the surface of the first seed layer, which is opposite to the silicon wafer base layer, and arranging a second opening at the position, corresponding to the bonding pad, of the first mask layer; specifically, referring to fig. 5d, the material of the first mask layer 38 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in the embodiment, the material of the first mask layer 38 is photoresist, a second opening 380 penetrating through the first mask layer 38 is formed in the first mask layer 38 by using a photolithography process, and the second opening 380 is located above the pad 32.
S205: forming a second rewiring layer in the second opening; specifically, referring to fig. 5e, in one embodiment, an electroplating process is used to form a second redistribution layer 31 in the second opening 380, and the material of the second redistribution layer 31 is copper or other suitable metal. In this embodiment, the height of the second redistribution layer 31 is lower than the depth of the second opening 380, and in other embodiments, the height of the second redistribution layer 31 may be the same as the depth of the second opening 380.
S206: removing the first seed layer except the first mask layer and the second rewiring layer; specifically, referring to fig. 5f, in one embodiment, the first mask layer 38 is removed by photolithography to expose a portion of the first seed layer 36; then, removing part of the exposed first seed layer 36 by using a wet etching process or a dry etching process, and only remaining the first seed layer 36 positioned below the second rewiring layer 31; wherein, the bonding pad 32, the first seed layer 36 and the second rewiring layer 31 are electrically connected;
s207: electrically connecting the chip with a bonding pad of a package substrate; specifically, in an application scenario, as shown in fig. 6a, a metal bump 400 is disposed on a surface of a chip 40, and the metal bump 400 of the chip 40 is reflow-soldered to the second redistribution layer 31, so that the chip 40 is electrically connected to the second redistribution layer 31 and is electrically connected to a pad 32 through the second redistribution layer 31; in another application scenario, step S207 further includes: forming a passivation layer 50 on the second redistribution layer 31, and providing an opening 500 on the passivation layer 50 (as shown in fig. 7 a), providing a metal bump 520 on the surface of the chip 52, and performing reflow soldering on the metal bump 520 of the chip 52 and the second redistribution layer 31 through the opening 500, so that the chip 52 is electrically connected to the second redistribution layer 31 and the pad 32 through the second redistribution layer 31 (as shown in fig. 7 b); in the above two embodiments, the chip 40 or 52 is flip-chip mounted, and in other embodiments, the chip 40 or 52 may also be face-mounted, which is not limited in the present invention.
S208: plastically packaging the chip and one side of the silicon wafer base layer, where the second rewiring layer is formed; in particular, see fig. 6 b; in one embodiment, a liquid or powder resin is filled on the surface of the silicon wafer substrate 30 having the bonding pads 32, so that the chip 40 and the second rewiring layer 31 are entirely covered in the resin material, and the molding layer 42 is formed after curing.
S209: grinding one side of the silicon wafer base layer, which is opposite to the bonding pad, so that the thickness of the silicon wafer base layer is smaller than or equal to a preset thickness; specifically, referring to fig. 6c, in an application scenario, the thickness of the silicon wafer substrate 30 of a wafer directly taken from an encapsulation factory is generally large, so in this embodiment, the side of the silicon wafer substrate 30 opposite to the bonding pad 32 needs to be ground to make the thickness smaller than or equal to a predetermined thickness, for example, the predetermined thickness is 100um, and the thickness of the ground silicon wafer substrate 30 is 50, 60, 80um, and the like.
S210: arranging the state of the silicon wafer base layer to enable one side with the bonding pad to be positioned below the bonding pad, and forming a silicon through hole in the position, back to the bonding pad, of the silicon wafer base layer; specifically, referring to fig. 6d, the manner of forming the through silicon via 44 is already mentioned in the above embodiments, and is not described herein again.
S211: forming a third mask layer on one side of the silicon wafer base layer, which is opposite to the bonding pad, and forming a sixth opening in a position, corresponding to the bonding pad, of the third mask layer; specifically, referring to fig. 6e, the material of the third mask layer 46 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in the embodiment, the material of the third mask layer 46 is photoresist, and a sixth opening 460 penetrating through the third mask layer 46 is formed in the third mask layer 46 by using a photolithography process, so as to expose the pad 32.
S212: forming a third sub-layer on the surface of the third mask layer, which is opposite to the surface of the silicon wafer base layer; specifically, referring to fig. 6f, in one embodiment, the material of the third sub-layer 41 is one or a mixture of titanium, aluminum, copper, gold, and silver, and the process for forming the third sub-layer 41 is a sputtering process or a physical vapor deposition process.
S213, forming a fourth mask layer on the surface of the third sub-layer opposite to the silicon wafer base layer, and forming a seventh opening on the fourth mask layer; specifically, referring to fig. 6g, the material of the fourth mask layer 43 is one or more of photoresist, silicon oxide, silicon nitride, and amorphous carbon, in this embodiment, the material of the fourth mask layer 43 is photoresist, and a seventh opening 430 penetrating the fourth mask layer 43 is formed in the fourth mask layer 43 by using a photolithography process.
S214: forming a first rewiring layer in the seventh opening; specifically, referring to fig. 6h, in one embodiment, a first redistribution layer 45 is formed in the seventh opening 430 by an electroplating process, and the material of the first redistribution layer 45 is copper or other metal. In fig. 6h, the seventh opening 430 is filled with the first redistribution layer 45, in other embodiments, the first redistribution layer 45 may also be filled with a layer in the seventh opening 430, and the thickness thereof may be designed according to practical situations, which is not limited by the present invention.
S215: removing the fourth mask layer and the third sublayer except the first rewiring layer; specifically, the step is similar to the step S206, and the structure thereof can be seen in fig. 6i, in which the first redistribution layer 45 and the third sublayer 41 are electrically connected to the pad 32.
S216: arranging a first blocking layer on the surface, opposite to the silicon wafer base layer, of the first rewiring layer, and forming an eighth opening on the first blocking layer; specifically, referring to fig. 6j, the material of the first barrier layer 47 has an insulating property, and in one embodiment, an eighth opening 470 is formed on the first barrier layer 47 by photolithography or other etching methods;
s217: arranging a solder ball; in an application scenario, please refer to fig. 6k, solder balls may be directly disposed in the eighth opening 470, for example, the solder balls 49 are planted in the eighth opening 470 by a ball-planting machine, and the material of the solder balls 49 is tin or tin alloy. Wherein the solder balls 49 and the first redistribution layer 45 are electrically connected; in another application scenario, referring to fig. 8, ball mounting may be performed in a manner of forming an under-ball metal layer on the first redistribution layer 45; specifically, a fourth sub-layer 60 is formed on the surface of the first barrier layer 47 opposite to the silicon wafer base layer 30 (as shown in fig. 8 a), and the fourth sub-layer 60 may be formed by sputtering a titanium layer and then sputtering a copper layer on the titanium layer; forming a fifth mask layer 62 on the surface of the fourth seed layer 60 opposite to the silicon wafer base layer 30, and forming a ninth opening 620 (shown in fig. 8 b) on the fifth mask layer 62 at a position corresponding to the eighth opening 470; forming an under ball metal layer 64 in the ninth opening 620 (as shown in fig. 8 c), wherein the material of the under ball metal layer 64 may be copper, and may be formed by electroplating; removing the fifth mask layer 62 and the fourth sub-layer 60 under the fifth mask layer 62 (as shown in fig. 8 d); forming solder balls 66 on the positions corresponding to the under-ball metal layers 64, dropping the solder balls 66 to the positions corresponding to the under-ball metal layers 64 by a ball-mounting machine, and reflowing (as shown in fig. 8 e); the solder balls 66, the ubm layer 64, the fourth sub-layer 60, and the first redistribution layer 45 are electrically connected.
In a second embodiment, please refer to fig. 9, fig. 9 is a schematic flow chart of another fan-out packaging method according to another embodiment of the present invention, the method is mainly different from the first embodiment in that providing a package substrate includes: the reinforcing plate is attached to one side, back to the bonding pad, of the silicon wafer base layer, and the specific flow is as follows:
s301: providing a silicon wafer base layer provided with a bonding pad, and attaching a reinforcing plate to one side of the silicon wafer base layer, which is back to the bonding pad; specifically, referring to fig. 10a, the silicon wafer substrate 70 with a thickness less than or equal to a predetermined thickness may be selected at the beginning according to actual requirements, for example, when the predetermined thickness is 100um, the silicon wafer substrate 70 with a thickness of 50, 60, 80um, etc. may be directly selected; in order to prevent the strength of the silicon wafer substrate 70 from being insufficient in the subsequent preparation process, in this embodiment, a reinforcing plate 74 is attached to a side of the silicon wafer substrate 70 opposite to the bonding pad 72, the reinforcing plate 74 may be made of glass, metal, silicon wafer, or the like, and the reinforcing plate 74 and the silicon wafer substrate 70 may be attached and fixed by a double-sided adhesive film.
S302-S308 are the same as S202-S208 in the above embodiments, and are not repeated herein, and the schematic structural diagrams thereof can be seen in FIGS. 10b-10 h.
S309: removing the reinforcing plate; specifically, as shown in fig. 10i, in one embodiment, the reinforcing plate 74 and the silicon wafer substrate 70 are adhered by a double-sided adhesive film, which can be directly peeled off, so as to remove the reinforcing plate 74.
S310-S317 are the same as S210-S217 in the above embodiment, and the structure thereof can be seen in FIGS. 6d-6k, wherein the manner of disposing solder balls in step S317 can be seen in FIG. 8. .
In a third embodiment, please refer to fig. 12, fig. 12 is a schematic flow chart of a fan-out package method according to another embodiment of the present invention, the method mainly differs from the first embodiment in that a side of a silicon wafer base layer having a bonding pad can be subjected to multiple wiring, that is, at least one redistribution layer is formed on a side of a second redistribution layer opposite to the silicon wafer base layer, in this embodiment, the side of the silicon wafer base layer having the bonding pad includes two wiring layers, and the specific flow is as follows:
S401-S406 are the same as S201-S206 in the above embodiments, and are not described herein, and their structures can be seen in FIGS. 5a-5 f.
S407: forming a first dielectric layer on the surface of the second rewiring layer opposite to the silicon wafer base layer, and arranging a third opening on the first dielectric layer; specifically, referring to fig. 13a, in one embodiment, the first dielectric layer 80 is made of a photoresist, and after a layer of photoresist is coated on the surface of the second redistribution layer 31, a third opening 800 is formed in the first dielectric layer 80 by using a photolithography process.
S408: forming a second seed layer on the surface of the first dielectric layer opposite to the silicon wafer base layer; specifically, referring to fig. 13b, in one embodiment, a second seed layer 82 may be formed on a surface of the first dielectric layer 80 opposite to the silicon wafer substrate 30 by using a sputtering process, and the material of the second seed layer 82 is copper, titanium, or other metal.
S409: forming a second mask layer on the surface of the second seed layer, which is opposite to the silicon wafer base layer, and arranging a fourth opening on the second mask layer; specifically, referring to fig. 13c, in one embodiment, the second mask layer 84 is made of a photoresist, and a photolithography process is used to form the fourth opening 840.
S410: forming a third rewiring layer in the fourth opening; specifically, referring to fig. 13d, an electroplating process may be used to form a third redistribution layer 86 in the fourth opening 840, where the material of the third redistribution layer 86 may be a metal such as copper; in fig. 13d, the third redistribution layer 86 fills the entire fourth opening 840, in other embodiments, the third redistribution layer 86 may only be fully covered by one layer in the fourth opening 840, and the thickness may be set according to actual conditions.
S411: removing the second mask layer and the second seed layer except the third rewiring layer; specifically, referring to fig. 13e, after the second mask layer 84 is removed, the exposed second seed layer 82 is etched away; the second redistribution layer 31, the second seed layer 82, and the third redistribution layer 86 are electrically connected.
S412: electrically connecting the chip with a bonding pad of a package substrate; specifically, the step is similar to step S207 in the foregoing embodiment, the metal bump 880 is disposed on the surface of the chip 88, and the metal bump 880 of the chip 88 and the third redistribution layer 86 may be subjected to reflow soldering so as to electrically connect the chip 88 and the third redistribution layer 86 and to the pad 32 through the third redistribution layer 86 (as shown in fig. 13 f), or the passivation layer is disposed on the third redistribution layer 86 (as shown in fig. 14), a second passivation layer is formed on the third redistribution layer, a fifth opening is disposed on the second passivation layer, a metal bump is disposed on the surface of the chip, and the metal bump of the chip and the third redistribution layer through the fifth opening are subjected to reflow soldering so as to electrically connect the chip and the third redistribution layer and to the pad through the third redistribution layer.
S413-S422 are the same as S208-S217 in the above embodiments, and are not described herein again, and the structure thereof can be shown in fig. 13g-13p, wherein the ball-mounting manner in step S422 can also be a manner of forming an under-ball metal layer first and then mounting balls on the under-ball metal layer, as shown in fig. 15.
In a fourth embodiment, please refer to fig. 16, fig. 16 is a schematic flow chart of a fan-out package method according to another embodiment of the present invention, which is mainly different from the first embodiment in that electrical connection with a chip can be performed after rewiring is performed on both sides of a silicon wafer substrate, and the specific flow is as follows:
S501-S506 are the same as S201-S206 in the above embodiments, and are not described herein, and the structure thereof can be seen in FIGS. 5a-5 f.
The structures of S507-S513 and S209-S215 in the above embodiments can be seen in FIGS. 17a-17 g.
S514: providing a carrier plate, and connecting one side of the silicon wafer base layer, on which the first rewiring layer is formed, with the carrier plate; specifically, referring to fig. 17h, the carrier may be made of glass, metal, or the like, and the carrier and one side of the first redistribution layer may be connected by a double-sided adhesive film.
S515: arranging the silicon wafer base layer in a state that one side with the bonding pad is positioned above, and electrically connecting the chip with the bonding pad of the packaging substrate; specifically, this step is the same as step S207 in the above embodiment, and may adopt a manner of flip-chip mounting the chip on the second redistribution layer (as shown in fig. 17 i), or may adopt a manner of disposing a passivation layer on the second redistribution layer, which is not described herein again.
S516: the die and the side of the silicon wafer substrate on which the second rewiring layer is formed are subjected to plastic packaging, specifically, the step is the same as step S208 in the above embodiment, as shown in fig. 17 j.
S517: removing the carrier plate; specifically, as shown in fig. 17k, when the carrier board and the first redistribution layer are connected by adhesive film, the carrier board may be removed by tearing off the adhesive film.
S518: arranging a first blocking layer on the surface, opposite to the silicon wafer base layer, of the first rewiring layer, and forming an eighth opening on the first blocking layer; specifically, this step is the same as step S216 in the above-described embodiment, as shown in fig. 17 l.
S519: disposing solder balls on the first redistribution layer; specifically, this step is the same as step S217 in the above-described embodiment, as shown in fig. 17m or fig. 8.
The above illustration shows only four embodiments, and it is within the scope of the present invention to provide a fan-out package method involving rewiring of the silicon wafer substrate on the side opposite to the bond pads.
Referring to fig. 18, fig. 18 is a schematic structural diagram of an embodiment of a fan-out package device of the present invention, where the device 9 includes: the package substrate 90 includes a silicon wafer base layer 900, a pad 902, and a first redistribution layer 904, wherein the pad 902 is disposed on one side of the silicon wafer base layer 900, the first redistribution layer 904 is disposed on the other side of the silicon wafer base layer 900, the pad 902 is electrically connected to the first redistribution layer 904, and the chip 92 is electrically connected to the pad 902 of the package substrate 90.
In one application scenario, the thickness of the silicon wafer substrate 900 is equal to or less than a predetermined thickness, for example, the predetermined thickness is 100um, and the thickness of the silicon wafer substrate 900 may be 50, 70, 80um, etc. The silicon wafer substrate 900 may be directly provided with bonding pads 902, such as wafers that may be generally directly accessible to a packaging and testing facility; the thickness of the silicon wafer substrate layer of the directly taken wafer may be directly less than or equal to the predetermined thickness, and may also exceed the predetermined thickness, and when the thickness of the silicon wafer substrate layer of the wafer exceeds the predetermined thickness, the back surface of the silicon wafer substrate layer 900 needs to be ground, so that the thickness of the silicon wafer substrate layer in the fan-out package device provided by the invention is less than or equal to the predetermined thickness.
In another application scenario, due to poor conductivity of the silicon wafer base layer 900, in order to electrically connect the pad 902 and the first redistribution layer 904 on two opposite sides of the silicon wafer base layer 900, a through silicon via 906 is disposed on a side of the silicon wafer base layer 900 opposite to the pad 902, and the position of the through silicon via 906 corresponds to the position of the pad 902, so that the first redistribution layer 904 is electrically connected to the pad 902 through the through silicon via 906.
In another application scenario, with continued reference to fig. 18, the package substrate 90 further includes a second redistribution layer 908, and the second redistribution layer 908 is disposed on the pad 902 and electrically connected to the pad 902.
The structure of the fan-out package device provided by the present invention will be further described with respect to several specific embodiments.
Continuing to refer to fig. 18, in one embodiment, the side of the silicon wafer base layer 900 facing away from the pad 902 includes, in addition to the first redistribution layer 904: a third mask layer 901 disposed between a side of the silicon wafer base layer 900 opposite to the pad 902 and the first redistribution layer 904, and a sixth opening (not labeled) is disposed at a position corresponding to the pad 902; a third sublayer 903 disposed between the third mask layer 901 and the first redistribution layer 904; wherein, the first redistribution layer 904, the third sublayer 903 and the pad 902 are electrically connected; a first blocking layer 905 disposed on a side of the first redistribution layer 904 opposite to the silicon wafer base layer 900, and an eighth opening (not labeled) is formed on the first blocking layer 905; a solder ball 907 disposed in the eighth opening (not labeled) and electrically connected to the first redistribution layer 904. The side of the silicon wafer base layer 900 provided with the pad 902 includes, in addition to the second rewiring layer 908, the device further including: a first passivation layer 909 disposed between the pad 902 side of the silicon wafer substrate 900 and the second redistribution layer 908, and a first opening (not labeled) is disposed at a position of the first passivation layer 909 corresponding to the pad 902; a first seed layer 910 disposed between the first passivation layer 909 and the second rewiring layer 908; the pad 902, the first seed layer 910, and the second redistribution layer 908 are electrically connected. A metal bump 920 is arranged on the chip 92, and the chip 92 is in reflow soldering with the second re-wiring layer 908 through the metal bump 920; and a plastic sealing layer 911, wherein the plastic sealing layer 911 covers the chip 92 and one side of the silicon wafer base layer 900 provided with the bonding pad 902.
Referring to fig. 19, fig. 19 is a schematic structural diagram of another embodiment of a fan-out package device according to the present invention; in this embodiment, the difference between the packaged device and the packaged device in fig. 18 is that the solder balls are disposed on the side of the silicon wafer substrate opposite to the bonding pads, and the under-ball metal layer is disposed in this embodiment. Specifically, the packaged device includes, in addition to the structure in fig. 18 described above, further: a fourth sub-layer 1002 covering the eighth opening (not labeled) of the first barrier layer 1000 and disposed on a side of the first barrier layer 1000 opposite to the silicon wafer base layer 1004; the ubm layer 1006 is disposed on a side of the fourth sub-layer 1002 opposite to the silicon wafer base layer 1004; a solder ball 1008 disposed on a side of the ubm layer 1006 opposite to the si wafer base layer 1004; the solder balls 1008, the ubm layer 1006, the fourth sub-layer 1002, and the first redistribution layer 1001 are electrically connected.
Referring to fig. 20, fig. 20 is a schematic structural diagram of a fan-out package device in accordance with another embodiment of the present invention; in this embodiment, the difference between the packaged device and the packaged device in fig. 19 is that rewiring may be performed several times on the side of the silicon wafer substrate on which the pads are disposed, taking twice the wiring as an example on the side of the silicon wafer substrate on which the pads are disposed, that is, the side of the second rewiring layer 1102 opposite to the silicon wafer substrate 1100 further includes a third rewiring layer 1104. Specifically, the structure of the packaged device that is the same as that in fig. 19 is not described herein again, and the packaged device in this embodiment further includes: a first dielectric layer 1106 disposed between the second redistribution layer 1102 and the third redistribution layer 1104, wherein a third opening (not shown) is disposed on the first dielectric layer 1106; a second seed layer 1108 disposed between the first dielectric layer 1106 and the third redistribution layer 1104; wherein the second redistribution layer 1102, the second seed layer 1108, and the third redistribution layer 1104 are electrically connected; the surface of the chip 112 is provided with a metal bump 1120, and the chip 112 is reflow-soldered to the third redistribution layer 1104 through the metal bump 1120.
Referring to fig. 21, fig. 21 is a schematic structural diagram of a fan-out package device according to still another embodiment of the present invention; in the present embodiment, the packaged device differs from the packaged device in fig. 20 above in the manner in which the chip is electrically connected to the third rewiring layer. Specifically, as shown in fig. 21, the device further includes: the second passivation layer 1200 is disposed on a side of the third redistribution layer 1202 opposite to the silicon wafer base layer 1204, the second passivation layer 1200 is provided with a fifth opening, the surface of the chip 122 is provided with a metal bump 1220, and the metal bump 1220 of the chip 122 is reflow-welded to the third redistribution layer 1202 through the fifth opening.
In other embodiments, the package device may also have other structures, and the present invention is not limited thereto.
In summary, different from the situation of the prior art, the package substrate in the fan-out package method adopted by the present invention includes a silicon wafer base layer, a pad and a first redistribution layer, where the pad and the first redistribution layer are respectively located at two sides of the silicon wafer base layer, the pad is electrically connected to the first redistribution layer, and the chip is electrically connected to the pad; on one hand, the packaging substrate comprises a bonding pad, and the chip is electrically connected with the bonding pad of the packaging substrate, so that the situation that the position of the chip is deviated due to the fact that a glue film is heated and softened in the subsequent chip plastic packaging process is avoided; on the other hand, the packaging substrate comprises a silicon wafer base layer, and the silicon wafer base layer has better thermal conductivity, so that the heat dissipation of the fan-out type packaging device is facilitated; on the other hand, the bonding pads of the packaging substrate and the first rewiring layer are positioned on two opposite sides of the silicon wafer base layer, and technical support is provided for a fan-out type packaging structure with a double-sided solder ball structure.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A fan-out packaged device, the device comprising:
the packaging substrate comprises a silicon wafer base layer, a bonding pad and a first rewiring layer, wherein the bonding pad is arranged on one side of the silicon wafer base layer, the first rewiring layer is arranged on the other side of the silicon wafer base layer, and the bonding pad is electrically connected with the first rewiring layer;
a chip electrically connected with the pad of the package substrate.
2. The device of claim 1,
the packaging substrate further comprises a second re-wiring layer, and the second re-wiring layer is arranged on the bonding pad and electrically connected with the bonding pad.
3. The device of claim 1,
the thickness of the silicon wafer base layer is less than or equal to a preset thickness; and a through silicon via is formed on one side of the silicon wafer base layer, which is opposite to the bonding pad, and the position of the through silicon via corresponds to that of the bonding pad, so that the first rewiring layer is electrically connected with the bonding pad through the through silicon via.
4. The device of claim 1, wherein one side of the pad of the silicon wafer substrate includes a second re-routing layer, the device further comprising:
the first passivation layer is arranged between one side of the bonding pad of the silicon wafer base layer and the second rewiring layer, and a first opening is formed in the position, corresponding to the bonding pad, of the first passivation layer;
a first seed layer disposed between the first passivation layer and the second re-wiring layer;
wherein the bonding pad, the first seed layer, and the second re-wiring layer are electrically connected.
5. The device of claim 4, wherein a side of the pad of the silicon wafer substrate includes a third rewiring layer in addition to a second rewiring layer, the second rewiring layer side facing away from the silicon wafer substrate, the device further comprising:
a first dielectric layer disposed between the second redistribution layer and the third redistribution layer, and having a third opening formed thereon;
a second seed layer disposed between the first dielectric layer and the third re-wiring layer;
wherein the second re-wiring layer, the second seed layer, and the third re-wiring layer are electrically connected.
6. The device of claim 5,
the surface of the chip is provided with a metal bump, and the chip is in reflow soldering with the third rewiring layer through the metal bump; or,
the device further comprises a second passivation layer, wherein the second passivation layer is arranged on one side, back to the silicon wafer base layer, of the third rewiring layer, a fifth opening is formed in the second passivation layer, a metal bump is arranged on the surface of the chip, and the metal bump of the chip is in reflow soldering with the third rewiring layer through the fifth opening.
7. The device of claim 1, further comprising:
and the plastic packaging layer covers the chip and one side of the silicon wafer base layer, which is provided with the bonding pad.
8. The device of claim 1, wherein a side of the silicon wafer base layer facing away from the pad includes a first redistribution layer, the device further comprising:
the third mask layer is arranged between one side, back to the bonding pad, of the silicon wafer base layer and the first rewiring layer, and a sixth opening is formed in the position corresponding to the bonding pad;
a third sublayer disposed between the third mask layer and the first redistribution layer;
wherein the first redistribution layer, the third sublayer, and the pad are electrically connected.
9. The device of claim 8, further comprising:
the first blocking layer is arranged on one side, back to the silicon wafer base layer, of the first rewiring layer, and an eighth opening is formed in the first blocking layer;
and the solder balls are arranged in the eighth openings and are electrically connected with the first rewiring layer.
10. The device of claim 8, further comprising:
the first blocking layer is arranged on one side, back to the silicon wafer base layer, of the first rewiring layer, and an eighth opening is formed in the first blocking layer;
the fourth sub-layer covers the eighth opening and is arranged on one side, opposite to the silicon wafer base layer, of the first barrier layer;
the under-ball metal layer is arranged on one side, back to the silicon wafer base layer, of the fourth sub-layer;
the solder balls are arranged on one side, back to the silicon wafer base layer, of the under-ball metal layer;
wherein the solder balls, the UBM layer, the fourth sub-layer, and the first redistribution layer are electrically connected.
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| CN201710740313.4A CN107564879A (en) | 2017-08-24 | 2017-08-24 | A kind of fan-out package device |
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| CN201710740313.4A CN107564879A (en) | 2017-08-24 | 2017-08-24 | A kind of fan-out package device |
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| CN114783890A (en) * | 2022-03-28 | 2022-07-22 | 华进半导体封装先导技术研发中心有限公司 | Passive adapter plate and preparation method thereof |
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| US20130210198A1 (en) * | 2012-02-10 | 2013-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for forming semiconductor structure |
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Application publication date: 20180109 |