CN107564815A - A kind of method for making power semiconductor - Google Patents

Abstract

A method for manufacturing a power semiconductor, the method comprising: Step 1, forming a gate oxide layer with a preset thickness on a substrate; Step 2, etching the gate oxide layer with a preset thickness, so that the gate oxide layer has various thickness, wherein the thickness of the gate oxide layer tends to increase gradually from the first end to the second end; step 3, forming a polysilicon layer on the gate oxide layer after etching. Compared with the existing power semiconductor production method, the power semiconductor produced by this method is more smooth, and the difficulty of the process (such as mark alignment, photolithography and etching, etc.) is effectively reduced, which also helps to improve the power semiconductor. The performance of the device and the reliability of the chip package function.

Description

A method of making a power semiconductor

technical field

The invention relates to the technical field of power electronics, in particular, to a method for manufacturing power semiconductors.

Background technique

Power semiconductors are the basis of power electronics technology and its application devices, and are the main source of promoting the development of power electronics converters. Power semiconductors are at the heart of modern power electronic converters and play an important role in device reliability, cost and performance. Among them, ordinary thyristors, gate turn-off thyristors and insulated gate bipolar transistors (IGBTs) have successively been called the development platforms of power semiconductor devices.

The thickness of the gate oxide layer of (planar) gate-controlled power semiconductor devices (such as IGBT) has a direct impact on the size of the gate capacitance, which in turn affects the threshold voltage and switching characteristics of the entire power semiconductor device. In order to reduce the gate capacitance, the prior art usually implements it by increasing the thickness of the gate oxide layer. However, if the threshold voltage is considered at the same time, then the thickness of the gate oxide layer needs to be optimally compromised. However, the optimal compromise of the thickness of the gate oxide layer used in existing power semiconductor devices makes the surface of the gate oxide layer uneven and easily causes discontinuous topography of the gate oxide layer.

Contents of the invention

In order to solve the above problems, the present invention provides a method for making a power semiconductor, the method comprising:

Step 1, forming a gate oxide layer with a preset thickness on the substrate;

Step 2: Etching the gate oxide layer with a preset thickness, so that the gate oxide layer has multiple thicknesses, wherein the thickness of the gate oxide layer presents a gradually increasing thickness from the first end to the second end trend;

Step 3, forming a polysilicon layer on the etched gate oxide layer.

According to an embodiment of the present invention, the thickness of the gate oxide layer at the thickest position after etching is more than 8 times the thickness at the thinnest position.

According to an embodiment of the present invention, in the second step, the thickness of the gate oxide layer increases linearly from the first end to the second end by etching the predetermined thickness of the gate oxide layer.

According to an embodiment of the present invention, in the second step, multiple layers of sequentially connected layer segments are formed by performing multiple etchings on the gate oxide layer with a preset thickness,

Each odd-numbered layer in the plurality of layers is a flat layer, and each even-numbered layer is an oblique layer; or,

Each odd-numbered layer in the plurality of layers is an oblique layer, and each even-numbered layer is a flat layer;

Wherein, the flat interval is an interval whose thickness at each position remains constant, and the inclined interval is an interval whose thickness increases linearly.

According to an embodiment of the present invention, in the second step, the gate oxide layer with the preset thickness is etched multiple times to form a plurality of layer segments connected in sequence, and the plurality of layer segments form a stepped The structure, wherein the thickness of the layer segment farther from the first end is greater.

According to an embodiment of the present invention, the length of the layer segment farthest from the first end among the plurality of layer segments is less than half of the half-cell thickness of the power semiconductor.

According to an embodiment of the present invention, the thickness of each position of the polysilicon layer is equal.

According to an embodiment of the present invention, before forming the gate oxide layer with a predetermined thickness, the method further forms a first window on the substrate, and uses the first window to form a An enhanced carrier layer of the first conductivity type, in which a P-base region is formed.

According to an embodiment of the present invention, after forming the polysilicon layer, the method further forms a second window in the polysilicon layer and the gate oxide layer, and uses the second window to form a An enhanced carrier layer of the first conductivity type, forming a P-base region in the enhanced carrier layer.

According to an embodiment of the present invention, after forming the P-base region, the method further forms a source region with the first conductivity type and an ohmic contact region with the second conductivity type in the P-base region, Wherein, the ohmic contact region is located in the middle of the P-base region.

According to an embodiment of the present invention, the thickness of the ohmic contact region is greater than the thickness of the source region.

According to an embodiment of the present invention, the method also includes:

forming a buffer layer on the other surface of the substrate;

A collector region is formed on the buffer layer.

According to an embodiment of the present invention, according to an embodiment of the present invention, the method further includes:

A short-circuit point is formed on the collector region.

The power semiconductor manufacturing method provided by the present invention can make the gate oxide layer in the power semiconductor change linearly, so it can effectively avoid the high convex and discontinuous defects on the device surface existing in the existing power semiconductor. Compared with the existing power semiconductors, the power semiconductors provided by the present invention are more flat, and the difficulty of the process (such as mark alignment, photolithography and etching, etc.) is effectively reduced, which also helps to improve the performance of power semiconductor devices. performance and reliability of the chip package function.

The gate oxide layer of the power semiconductor provided by the present invention can be manufactured by using standard photolithography and etching processes, without additionally developing a specific photolithography and etching process for the stepped gate structure, thus saving process development costs. At the same time, the gate oxide layer is a relatively gentle structure formed by multiple step-by-step photolithography and etching, so a single deep etching can be avoided, which also reduces the difficulty of the process.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Description of drawings

The drawings illustrate various embodiments of aspects of the invention and together with the description serve to explain the principles of the invention. Those skilled in the art will appreciate that the specific embodiments shown in the drawings are by way of example only and that they are not intended to limit the scope of the invention. It should be appreciated that in some examples, one element shown may also be designed as multiple elements, or that multiple elements may also be designed as one element. In some examples, an element shown as an internal component of another element may also be implemented as an external component of the other element, and vice versa. In order to more clearly and in detail exemplary embodiments of the present invention so that those skilled in the art can more thoroughly understand the advantages of aspects and features of the present invention, the accompanying drawings are now introduced, in which:

FIG. 1 is a schematic structural diagram of an existing power semiconductor;

2 is a schematic structural view of a power semiconductor half cell according to an embodiment of the present invention;

3 is a schematic structural view of a power semiconductor half cell according to an embodiment of the present invention;

4 is a schematic structural diagram of a power semiconductor half cell according to an embodiment of the present invention;

5 is a schematic structural diagram of a power semiconductor half cell according to an embodiment of the present invention;

6 is a schematic structural diagram of a power semiconductor half cell according to an embodiment of the present invention;

Fig. 7 is a schematic structural diagram of a power semiconductor half cell according to an embodiment of the present invention;

8 and 9 are flowcharts of fabricating the power semiconductor shown in FIG. 7 according to one embodiment of the present invention.

Detailed ways

The implementation of the present invention will be described in detail below in conjunction with the accompanying drawings and examples, so as to fully understand and implement the process of how to apply technical means to solve technical problems and achieve technical effects in the present invention. It should be noted that, as long as there is no conflict, each embodiment and each feature in each embodiment of the present invention can be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.

Also, in the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without the specific details or in the particular manner described.

In addition, the steps shown in the flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and, although a logical order is shown in the flow diagrams, in some cases, the sequence may be different. The steps shown or described are performed in the order herein.

As shown in Figure 1, for the existing planar gate-controlled power semiconductor devices, the gate oxide layer adopts a trapezoidal design scheme, by setting a thin gate oxide layer near the channel, A thick gate oxide layer is provided at the position of the channel to achieve the effects of reducing gate capacitance, optimizing switching characteristics of power semiconductor devices, and at the same time adjusting threshold voltage characteristics. However, how to design the ratio of thin and thick gate oxide layers (the ratio of packet length to thickness) will directly affect the size of the gate capacitance, and then affect the optimal compromise between switching characteristics and threshold voltage characteristics. Moreover, the most important thing is that the existing design scheme of the gate oxide layer has a great influence on the topography of the device surface, and it is easy to cause high protrusions and discontinuities on the device surface, thereby affecting the flatness of the device surface. This not only makes it more difficult to realize the process of the device, but also affects the performance of the device and the reliability of the chip package.

In view of the above-mentioned problems existing in the prior art, the present invention provides a new power semiconductor, the thickness of the gate oxide layer of the power semiconductor varies gently, which can improve the smoothness of the surface of the power semiconductor and reduce the process of the gate oxide layer. Difficulty, but also can improve chip performance and packaging reliability.

In order to more clearly illustrate the structure and advantages of the power semiconductor provided by the present invention, the power semiconductor provided by the present invention will be further described below in conjunction with different embodiments. At the same time, since the structure of the power semiconductor provided by the present invention is Symmetrical, so for the sake of description, the following examples are all described with a semi-cellular structure.

Embodiment one:

FIG. 2 shows a schematic structural diagram of a half-cell of a power semiconductor provided by this embodiment.

As shown in FIG. 2 , the power semiconductor provided by this embodiment preferably includes: a substrate 201 , a first conductive region, a gate oxide layer 202 and a polysilicon layer 203 . Among them, in this embodiment, the first conductive region is formed in the substrate 201, which includes: an enhanced carrier layer 204 with the first conductivity type, a P-base layer 205 with the second conductivity type, and a P-based layer 205 with the first conductivity type. type of source region 206 and an ohmic contact region 207 of a second conductivity type. In this embodiment, the conductivity type of the substrate 201 is the first conductivity type.

In this embodiment, the enhanced carrier layer 204 is formed in the substrate 201 . In the process of fabricating the enhanced carrier layer 204, an oxide layer is first deposited on the substrate 201, the thickness of the oxide layer is preferably no more than 0.5 μm, and then the formed oxide layer is etched, thereby fabricating out of the injection/doping window of the enhanced carrier layer 204. After the implantation/doping window of the enhanced carrier layer 204 is obtained, the implantation/doping window is used to implant/dope the enhanced carrier layer into the substrate 201, followed by high-temperature propulsion/diffusion, so that An enhanced carrier layer 204 with a higher doping concentration than the substrate 201 is formed. In this embodiment, the doping concentration of the enhanced carrier layer 204 is preferably greater than 1e15/cm ³ .

After the enhanced carrier layer 204 is obtained, a P-base layer 205 needs to be further formed in the enhanced carrier layer 204 . In this embodiment, since the enhanced carrier layer 204 is formed using the injection/doping window of the enhanced carrier layer 204, the high-temperature advance process increases the thickness of the oxide layer, so it is necessary to first adjust the thickness The added oxide layer is etched to form an implantation/doping window for the P-base region.

After the implantation/doping window of the P-base region is formed, the window can be used to perform implantation/doping of the P-base region to the enhancement carrier layer 204, followed by high-temperature advancement/diffusion treatment, so that the enhancement-type A P-base region 205 is formed in the carrier layer 204 . In this embodiment, the doping concentration of the P-base region 205 is preferably on the order of e17/cm ³ .

It should be noted that, in other embodiments of the present invention, according to actual needs, the doping concentration of the enhanced carrier layer 204 and/or the P-base region 205 may be other reasonable values, and the present invention is not limited thereto.

Similarly, the same method can be used to form the source region 206 and the ohmic contact region 207 in the P-base region 205 respectively, and the specific formation process will not be repeated here. In this embodiment, the thickness of the ohmic contact region 207 is preferably greater than the thickness of the source region 206 .

As shown in FIG. 2 , in this embodiment, a gate oxide layer 202 is formed on a substrate 201 , and an end of the gate oxide layer 202 close to the source region 206 is in contact with the source region 206 . A polysilicon layer 207 is formed on the gate oxide layer 202, and its thickness at various locations preferably remains constant.

In order to avoid the problems of difficult process and poor control of process uniformity caused by the excessive thickness difference between the thin and thick parts of the gate oxide layer in the existing power semiconductors, and the problems of high convexity and discontinuity on the surface of power semiconductor devices caused by this , the gate oxide layer of the power semiconductor provided in this embodiment adopts a novel mesa gate structure. Specifically, as shown in FIG. 2 , the gate oxide layer 202 has various thicknesses, and the thickness of the gate oxide layer increases linearly as the distance from the centerline of the first conductive region increases.

In the power semiconductor half-cell structure shown in FIG. 2, the first end (ie, the left end point in the figure) of the gate oxide layer 202 is located above the source region 206, and the second end (ie, the right end point in the figure) is connected to Cell edges are aligned. Wherein, the first end of the gate oxide layer 202 can be regarded as the starting point of the gate oxide layer, and the second end can be regarded as the end point of the gate oxide layer. In this embodiment, the thickness of the gate oxide layer 202 increases linearly from the starting point to the end point, the thickness D1 _of the gate oxide layer at the starting position is preferably a conventional thickness (for example, 0.1 μm), and the thickness D1 of the gate oxide layer at the end position is The thickness D2 is preferably more than ₁₀ times the thickness at the starting point (for example, 1 μm).

It should be pointed out that, in other embodiments of the present invention, according to actual needs, the thickness of the gate oxide layer 202 at the starting position can also be other reasonable thicknesses, and the thickness at the ending position can also be other than the starting position. The value of the thickness at the position (for example, the thickness of the gate oxide layer at the end position is more than 8 times the thickness at the start position, etc.), the present invention is not limited thereto.

In this embodiment, after the source region 206 and the ohmic contact region 207 are fabricated, the gate oxide layer 202 and the polysilicon layer 203 can be fabricated. Specifically, in this embodiment, a _SiO2 layer with a thickness of D2 is firstly formed _on the substrate 201 and the first conductive region, and then multiple photolithography and etching methods are used, so that the thickness of the _SiO2 layer is linear change.

After obtaining the SiO ₂ layer whose thickness varies linearly, a polysilicon layer with a specific thickness is formed on the SiO ₂ layer, and N-type polysilicon doping is performed. In this embodiment, the thickness of the polysilicon layer is preferably less than 0.5 μm, and its doping concentration is preferably above 1e19/cm ³ . Of course, in other embodiments of the present invention, the thickness and doping concentration of the polysilicon layer may also be other reasonable values according to actual needs, and the present invention is not limited thereto.

After the above process is completed, in this embodiment, photolithography or etching is also performed on a part of the _SiO2 layer and the polysilicon layer covering the ohmic contact region 207 and the source region 206, thereby finally forming a power semiconductor as shown in FIG. 2 structure.

It should be pointed out that in other embodiments of the present invention, the material of the gate oxide layer can also be selected from other reasonable materials, and the present invention is not limited thereto. At the same time, it should also be pointed out that in other embodiments of the present invention, the source region 206 and the ohmic contact region 207 can also be fabricated after the gate oxide layer 202 and the polysilicon layer 203 are fabricated. Those skilled in the art can already know it through the above description, so it will not be repeated here.

In this embodiment, the power semiconductor further includes a buffer layer 208 of the first conductivity type and a collector region 209 of the second conductivity type. Wherein, a buffer layer 208 is formed on the other surface of the substrate 201, which preferably includes a first buffer layer 208a and a second buffer layer 208b. It should be noted that in other embodiments of the present invention, the buffer layer 208 may only include a one-layer structure, or may include more than three layers, and the present invention is not limited thereto.

The collector region 209 is formed on the buffer layer 208 . As shown in FIG. 2 , in this embodiment, several short-circuit points 210 of the first conductivity type are formed in the collector region 209 .

In this embodiment, in the process of making the buffer layer 208, the collector region 209, and the short circuit point 210, firstly, high-temperature (for example, greater than 1000°C) diffusion or ion implantation + low-temperature (for example, lower than 500°C) annealing are used to One or more N buffer layer structures are formed on the surface of the substrate 201 to obtain a buffer layer 208 . Subsequently, a P+ collector region 209 is formed on the surface of the buffer layer 208 by high temperature diffusion or ion implantation+laser annealing. Finally, several N+ short-circuit points 210 are formed in the P+ collector region 209 by high temperature diffusion or ion implantation+laser annealing.

It should be pointed out that, in different embodiments of the present invention, for thicker power semiconductors, the order of the front process and the back process (that is, the process of making the buffer layer, the collector region and the short circuit point) can be adjusted. That is, the back process can be performed first and then the front process, or the front process can be performed first and then the back process. For power semiconductors that need to be thinned, it is necessary to perform the front process first and then the back process, and there must be no high temperature process in the back process.

It can be seen from the above description that the gate oxide layer in the power semiconductor provided by this embodiment changes linearly, so it can effectively avoid the defects of high protrusion and discontinuity on the surface of the device existing in the existing power semiconductor. Compared with the existing power semiconductors, the power semiconductors provided by this embodiment are smoother, and the difficulty of the process (such as mark alignment, photolithography and etching, etc.) is effectively reduced, which also helps to improve the power semiconductor devices. The performance and reliability of the chip package function.

The gate oxide layer of the power semiconductor provided in this embodiment can be fabricated by using standard photolithography and etching processes, without additional development of specific photolithography and etching processes for the stepped gate structure, thus saving process development costs. At the same time, the gate oxide layer is a relatively gentle structure formed by multiple step-by-step photolithography and etching, so a single deep etching can be avoided, which also reduces the difficulty of the process.

Embodiment two:

FIG. 3 shows a schematic structural diagram of a power semiconductor half cell provided by this embodiment.

Comparing Figure 2 and Figure 3, it can be seen that the power semiconductor provided by this embodiment is different from the power semiconductor provided by Embodiment 1 only in the gate oxide layer and the polysilicon layer, therefore, for the convenience of description, the above differences are highlighted at the same time In the following, only the gate oxide layer and the polysilicon layer of the power semiconductor in this embodiment will be further described.

As shown in FIG. 3 , in this embodiment, the gate oxide layer includes two layer segments, namely a first layer segment and a second layer segment. Wherein, the projected lengths of the first layer segment and the second layer segment on the substrate are L ₁ and L ₂ respectively. For the first layer section, as the distance from the centerline of the ohmic contact area increases, its thickness remains unchanged, that is, the thickness is always D ₁ ; while for the second layer section, as the distance from the centerline of the ohmic contact area The thickness increases linearly from D ₁ to D ₂ .

Of course, in other embodiments of the present invention, as the distance from the center line of the ohmic contact region increases, the thickness of the gate oxide layer in the power semiconductor can also be linearly increased first and then kept constant, that is, the gate oxide layer shown in FIG. 4 is formed. structure.

It should be pointed out that, for the power semiconductor shown in FIG. 4 , in order to avoid an excessively large proportion of the gate oxide layer with a large thickness, the length L2 of the _second layer segment is preferably less than half of the half-cell length of the power semiconductor. Control the threshold voltage of power semiconductors within a reasonable range.

Embodiment three:

FIG. 5 shows a schematic structural diagram of a power semiconductor half cell provided by this embodiment.

Comparing Figure 2 and Figure 5, it can be seen that the power semiconductor provided by this embodiment differs from the power semiconductor provided by Embodiment 1 only in the gate oxide layer and the polysilicon layer, therefore, for the convenience of description, the above differences are highlighted at the same time In the following, only the gate oxide layer and the polysilicon layer of the power semiconductor in this embodiment will be further described.

As shown in FIG. 5 , in this embodiment, the gate oxide layer includes three layer segments, namely a first layer segment, a second layer segment and a third layer segment. Wherein, the projected lengths of these three layers on the substrate are L ₁ , L ₂ and L ₃ respectively. For the first layer, as the distance from the center line of the ohmic contact area increases, its thickness remains unchanged, that is, the thickness remains at D1 _; for the second layer, as the distance from the center line of the ohmic contact area increases increases, its thickness increases linearly from D ₁ to D ₂ ; for the third layer, as the distance from the centerline of the ohmic contact area increases, its thickness remains unchanged, that is, the thickness remains at D ₂ .

It should be noted that, in other embodiments of the present invention, the number n of layers contained in the gate oxide layer may also be other reasonable values, and the present invention is not limited thereto. For example, when the gate oxide layer contains 7 layer segments, the structure of the power semiconductor will be as shown in Figure 6.

At the same time, it should be noted that, in order to avoid an excessively large proportion of the gate oxide layer with a large thickness, the length L _n of the last layer segment (that is, the nth layer segment) is preferably less than half of the length L of the half-cell of the power semiconductor , to control the threshold voltage of the power semiconductor within a reasonable range. i.e. exists:

L ₁ +L ₂ +...+L _n-1 >L/2

It should be pointed out that when the gate oxide layer includes multiple layers, it can be that the odd number of layers in the multiple layers is a flat layer (that is, as the distance from the centerline of the ohmic contact region increases, the thickness remains constant. variable intervals), the even-numbered intervals are oblique intervals (that is, the intervals whose thickness increases linearly with the increase of the distance from the centerline of the ohmic contact zone), or the odd-numbered intervals among these multiple intervals can be Inclined intervals and even-numbered intervals are base layer intervals, the present invention is not limited thereto.

In addition, for each of the multiple intervals, the projected lengths on the substrate are preferably equal, that is, there exists L ₁ =L ₂ =...=L _n , and the slope of each inclined interval is also Preferably equal.

Embodiment four:

FIG. 7 shows a schematic structural diagram of a power semiconductor half cell provided by this embodiment.

Comparing Figure 2 and Figure 7, it can be seen that the power semiconductor provided by this embodiment is different from the power semiconductor provided by Embodiment 1 only in the gate oxide layer and the polysilicon layer, therefore, for the convenience of description, the above differences are highlighted at the same time In the following, only the gate oxide layer and the polysilicon layer of the power semiconductor in this embodiment will be further described.

As shown in FIG. 7 , in this embodiment, the gate oxide layer includes four layer segments, namely, the first layer segment, the second layer segment, the third layer segment and the fourth layer segment. Wherein, these four layer segments are all flat layer segments, and their respective projected lengths on the substrate are L ₁ , L ₂ , L ₃ and L ₄ , thus forming a stepped gate oxide layer structure.

In this embodiment, the lengths of the multiple layer segments included in the gate oxide layer are preferably equal to each other, that is, L ₁ =L ₂ =L ₃ =L ₄ exists. At the same time, in order to avoid an excessively large proportion of the gate oxide layer with a large thickness, the length of the last layer segment is preferably less than half of the half-cell length L of the power semiconductor, so as to control the threshold voltage of the power semiconductor within a reasonable range.

It should be noted that, in other embodiments of the present invention, the number of layers included in the gate oxide layer may be other reasonable numbers, and the lengths of different layer segments may also be unequal, and the present invention is not limited thereto.

In order to more easily understand the characteristics of the power semiconductor provided in this embodiment, the manufacturing process of the power semiconductor provided in this embodiment will be further described below.

FIG. 8 and FIG. 9 show the flow chart of manufacturing the power semiconductor shown in FIG. 7 in this embodiment.

As shown in FIG. 8, in this embodiment, an oxide layer is first deposited on the substrate 201, and the thickness of the oxide layer is preferably not more than 0.5 μm, and then the formed oxide layer is etched, thereby producing a reinforced The injection/doping window of the type carrier layer 204 . After the implantation/doping window of the enhanced carrier layer 204 is obtained, the implantation/doping window is used to implant/dope the enhanced carrier layer into the substrate 201, followed by high-temperature propulsion/diffusion, so that An enhanced carrier layer 204 with a higher doping concentration than the substrate 201 is formed. In this embodiment, the doping concentration of the enhanced carrier layer 204 is preferably greater than 1e15/cm ³ .

After the enhanced carrier layer 204 is obtained, a P-base layer 205 needs to be further formed in the enhanced carrier layer 204 . As shown in FIG. 8 , in this embodiment, due to the process of forming the enhanced carrier layer 204 using the injection/doping window of the enhanced carrier layer 204 , the high temperature advance process increases the thickness of the oxide layer 211 , In this way, the implantation/doping window made for forming the enhanced carrier layer 204 will be covered by the oxide layer, so the oxide layer with increased thickness needs to be etched first to form the implantation/doping window of the P-base region. miscellaneous windows.

After the implantation/doping window of the P-base region is formed, the window can be used to perform implantation/doping of the P-base region to the enhancement carrier layer 204, followed by high-temperature advancement/diffusion treatment, so that the enhancement-type A P-base region 205 is formed in the carrier layer 204 . In this embodiment, the doping concentration of the P-base region 205 is preferably on the order of e17/cm ³ .

It should be noted that, in other embodiments of the present invention, according to actual needs, the doping concentration of the enhanced carrier layer 204 and/or the P-base region 205 may be other reasonable values, and the present invention is not limited thereto.

After the P-base region 205 is formed, a _SiO2 layer 211 with a thickness of D2 is formed on the substrate 201, and a stepped _SiO2 layer as shown in FIG. ₈ is produced by multiple photolithography and etching methods. The mesa, wherein the thickness of the thinnest part of the SiO ₂ mesa is D ₁ . In this embodiment, the value of D ₂ is preferably more than 10 times the value of D ₁ , and the value of D ₁ is preferably 0.1 μm.

After obtaining the SiO ₂ mesa, a polysilicon layer with a specific thickness is formed on the SiO ₂ mesa, and N-type polysilicon doping is performed. In this embodiment, the thickness of the polysilicon layer is preferably less than 0.5 μm, and its doping concentration is preferably above 1e19/cm ³ . Of course, in other embodiments of the present invention, the thickness and doping concentration of the polysilicon layer may also be other reasonable values according to actual needs, and the present invention is not limited thereto.

According to FIG. 9, it can be seen that after forming the polysilicon layer, the part of the _SiO2 layer and the polysilicon layer covering the ohmic contact region 207 and the source region 206 are photolithographically or etched, so that the final required gate oxide layer is formed. 202 and the polysilicon layer 203, at the same time, through the photolithography or etching process, the implantation/doping window for making the ohmic contact layer and the source region can also be formed.

After obtaining the implantation/doping windows of the ohmic contact layer and the source region, in this embodiment, the source region 206 and the ohmic contact region 207 are successively formed in the P-base region 205, because the source region 206 and the ohmic contact region The specific formation process of 207 is similar to the formation process of the P-base region, so it will not be repeated here. In this embodiment, the thickness of the ohmic contact region 207 is preferably greater than the thickness of the source region 206 .

At this point, the front side process of the power semiconductor is completed. After the front process is completed, the method provided in this embodiment will carry out the fabrication of the back process of the power semiconductor. Specifically, as shown in FIG. 9, one or more N buffers are first formed on the other surface of the substrate 201 by means of high temperature (for example greater than 1000°C) diffusion or ion implantation + low temperature (for example lower than 500°C) annealing. layer structure, thereby obtaining the buffer layer 208. In this embodiment, the buffer layer 208 includes a first buffer layer 208a and a second buffer layer 208b. Subsequently, a P+ collector region 209 is formed on the surface of the buffer layer 208 by high temperature diffusion or ion implantation+laser annealing. Finally, several N+ short-circuit points 210 are formed in the P+ collector region 209 by high temperature diffusion or ion implantation+laser annealing.

It should be pointed out that, in different embodiments of the present invention, for thicker power semiconductors, the order of the front process and the back process (that is, the process of making the buffer layer, the collector region and the short circuit point) can be adjusted. That is, the back process can be performed first and then the front process, or the front process can be performed first and then the back process. For power semiconductors that need to be thinned, it is necessary to perform the front process first and then the back process, and there must be no high temperature process in the back process.

In addition, it should be pointed out that, in other embodiments of the present invention, according to actual needs, the manufacturing process of the source region 206 and the ohmic contact region 207 can also be advanced before forming the gate oxide layer, and the present invention is not limited thereto.

It should be understood that the disclosed embodiments of the invention are not limited to the specific structures, process steps or materials disclosed herein, but extend to equivalents of these features understood by those of ordinary skill in the relevant art. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not meant to be limiting.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "one embodiment" or "an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment.

Although the above examples are used to illustrate the principles of the present invention in one or more applications, it will be obvious to those skilled in the art that the forms, usages and implementations can be changed without departing from the principles and ideas of the present invention. Various modifications can be made in the details without creative labor. Accordingly, the invention is defined by the appended claims.

Claims (13)

1. A kind of 1. method for making power semiconductor, it is characterised in that methods described includes：

   Step 1: the gate oxide of preset thickness is formed over the substrate；

   Step 2: the gate oxide of the preset thickness is performed etching so that the gate oxide has a variety of Thickness, wherein, the trend gradually increased is presented from first end to the second end for the thickness of the gate oxide；

   Step 3: form polysilicon layer on gate oxide after etching.
2. 2. the method as described in claim 1, it is characterised in that the most thick opening position of gate oxide after etching Thickness be more than 8 times of thickness of its most thin opening position.
3. 3. method as claimed in claim 1 or 2, it is characterised in that in the step 2, by right The gate oxide of the preset thickness performs etching so that the thickness of the gate oxide is along first end to the second end Linear increase.
4. 4. method as claimed in claim 1 or 2, it is characterised in that in the step 2, by right The gate oxide of the preset thickness carries out multiple etching, forms the multiple intervals being sequentially connected,

   Each odd number interval is flat bed section in the multiple interval, and each even number interval is oblique interval；Or,

   Each odd number interval is oblique interval in the multiple interval, and each even number interval is flat bed section；

   Wherein, the flat bed section keeps constant interval for the thickness of each opening position, and the tiltedly interval is thickness The interval linearly increased.
5. 5. method as claimed in claim 1 or 2, it is characterised in that in the step 2, by right The gate oxide of the preset thickness carries out multiple etching, forms the multiple intervals being sequentially connected, the multiple layer Section forms step structure, wherein, the thickness of the interval more remote apart from the first end is bigger.
6. 6. the method as described in claim 4 or 5, it is characterised in that in the multiple interval described in distance The length of the farthest interval of first end is less than the half of half cellular thickness of power semiconductor.
7. 7. such as method according to any one of claims 1 to 6, it is characterised in that the polysilicon layer everybody The thickness for putting place is equal.
8. 8. such as method according to any one of claims 1 to 7, it is characterised in that forming the default thickness Before the gate oxide of degree, methods described also forms first window over the substrate, and utilizes the first window The enhanced carrier layer with the first conduction type is formed in the substrate, in the enhanced carrier layer Middle formation P- bases.
9. 9. such as method according to any one of claims 1 to 7, it is characterised in that forming the polysilicon After layer, methods described also forms the second window in the polysilicon layer and gate oxide, and utilizes described second Window forms the enhanced carrier layer with the first conduction type in the substrate, in the enhanced current-carrying P- bases are formed in sublayer.
10. 10. method as claimed in claim 8 or 9, it is characterised in that after the P- bases are formed, Source area with the first conduction type is formed in the also described P- bases of methods described and with the second conduction type Ohmic contact regions, wherein, the ohmic contact regions are located at the centre position of the P- bases.
11. 11. method as claimed in claim 10, it is characterised in that the thickness of the ohmic contact regions is more than The thickness of the source area.
12. 12. the method as any one of claim 1~11, methods described also include：

    Cushion is formed on another surface of the substrate；

    Collector area is formed on the cushion.
13. 13. method as claimed in claim 12, methods described also include：

    Short dot is formed on the collector area.