CN107465474B - The clock synchronization system and method for digital control system bus apparatus - Google Patents
The clock synchronization system and method for digital control system bus apparatus Download PDFInfo
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- CN107465474B CN107465474B CN201610390830.9A CN201610390830A CN107465474B CN 107465474 B CN107465474 B CN 107465474B CN 201610390830 A CN201610390830 A CN 201610390830A CN 107465474 B CN107465474 B CN 107465474B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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Abstract
The invention discloses the clock synchronization systems and method of a kind of digital control system bus apparatus, and wherein clock synchronization system includes: the main website of EtherCAT main website, EtherCAT the first slave station and the first bus；Current time and bus communication period are sent to the first slave station in initialization by EtherCAT main website；First slave station generates synchronization signal according to reference clock in bus apparatus periodic communication and is sent to the main website of the first bus；The main website of first bus sends data frame to the slave station of first bus after receiving synchronization signal and synchronizing information is sent to EtherCAT main website；Temporal information is distributed to remaining EtherCAT slave station after receiving synchronizing information by EtherCAT main website.The time that the present invention compensates in the prior art in EtherCAT bus and mixed other buses in bus cannot be synchronous deficiency, completely eliminate time jitter, realize time synchronization.
Description
Technical field
The present invention relates to the clock synchronization systems and method of a kind of digital control system bus apparatus.
Background technique
The common bus of numerical control field includes EtherCAT, RTEX, Mechatrolink-II/III etc. at present.
EtherCAT is a kind of bus protocol based on Ethernet, uses the hardware device and drive software of standard ethernet
It realizes.It is usually used in order to make the time synchronization of EtherCAT main website and all EtherCAT slave stations in digital control system
" distribution clock " technology in EtherCAT agreement has the function of " distribution clock " by one nearest from EtherCAT main website
EtherCAT slave station 11 local clock is distributed to EtherCAT main website 10 and other slave stations 12,13 so that it is each from
The clock stood keeps synchronizing, specific as shown in Figure 1.The bussing techniques such as RTEX, Mechatrolink-II/III usually utilize bus
The included timing function of main website 20, realized by way of main website 20 regularly sends data frame same between each slave station 21,22,23
Step, it is specific as shown in Figure 2.Line not with the arrow indicates the connection relationship of each module in figure, and line with the arrow indicates time distribution
Direction.
In actual control digital control system, it is often necessary to while using EtherCAT bus and other buses, due to mark
Source between punctual is different, therefore the time in bus cannot synchronize.
In order to solve this problem, the clock source in current digital control system inside usually used digital control system, i.e. RTEX,
The main website of Mechatrolink-II/III is as fiducial time, and EtherCAT main website 10 is from RTEX, Mechatrolink-II/
After the main website chip 20 of III obtains the standard time, current time is sent to one nearest from EtherCAT main website
EtherCAT slave station 11, then other EtherCAT slave stations 12,13 are distributed to by this EtherCAT slave station 11, as shown in Figure 3.
The method of this time synchronization has an apparent defect, i.e., from " EtherCAT main website receives the standard time " to
The time interval of " an EtherCAT slave station nearest from EtherCAT main website receives the standard time " is unstable.EtherCAT
The operating system real-time of main website is poor, when leading to the standard received from the EtherCAT slave station of EtherCAT main website recently
Between have tens of delicate shakes, seriously affected the synchronism of EtherCAT bus, and then affect the performance of bus apparatus.
Summary of the invention
The technical problem to be solved by the present invention is in order to overcome in the prior art in EtherCAT bus and other buses
The defect that time when mixed in bus cannot synchronize provides clock synchronization system and the side of a kind of digital control system bus apparatus
Method.
The present invention is to solve above-mentioned technical problem by the following technical programs:
The present invention provides a kind of clock synchronization system of digital control system bus apparatus, its main feature is that, bus apparatus includes
EtherCAT main website, several slave stations of EtherCAT, the main website of the first bus and the first bus several slave stations, the time is same
Step system includes: control system；
The control system includes: the master of the EtherCAT main website, the first slave station of EtherCAT and first bus
It stands, first slave station of EtherCAT is one in several slave stations of EtherCAT；
EtherCAT main website is used to pass through current time and bus communication period in control system initialization
EtherCAT is sent to the first slave station of EtherCAT；
The first slave station of EtherCAT is used in bus apparatus periodic communication, with the local clock of the first slave station of EtherCAT
For benchmark clock, periodic synchronization signal is generated according to the reference clock, and the synchronization signal is sent to first always
The main website of line；
The main website of first bus is used for after receiving the synchronization signal, and the slave station of the first bus of Xiang Suoshu sends data
Frame, and synchronizing information is sent to EtherCAT main website；
EtherCAT main website is also used to after receiving the synchronizing information, by EtherCAT by EtherCAT first from
The temporal information stood is distributed to remaining EtherCAT slave station in several slave stations of EtherCAT.
The technical program controls the communication cycle of other buses by the first slave station of EtherCAT, realizes time synchronization.
Wherein, EtherCAT main website in synchronizing process and is not involved in, therefore can be to avoid caused by EtherCAT main website real-time difference
Time jitter accurately realizes the time synchronization between different bus.
Preferably, the EtherCAT main website includes control computer and ethernet controller, the control computer is also
For controlling EtherCAT communication and processing data, the ethernet controller is also used to sending and receiving data frame.
Preferably, the control computer is used in control system initialization, by current time and bus communication
Period is sent to the first slave station of EtherCAT by EtherCAT；
The main website of first bus is used for after receiving the synchronization signal, and the slave station of the first bus of Xiang Suoshu sends data
Frame, and the synchronization signal is sent to the control computer；
The control computer is also used to after receiving the synchronization signal, by EtherCAT by EtherCAT first
The temporal information of slave station is distributed to remaining EtherCAT slave station.
Preferably, the EtherCAT main website further include:
The control computer is substituted with programmable logic device, to control EtherCAT communication and processing data；
And/or the ethernet controller is substituted with ASIC, to sending and receiving data frame.
Preferably, first bus is RTEX bus or Mechatrolink-II/III bus.
The present invention also provides a kind of method for synchronizing time of digital control system bus apparatus, its main feature is that, bus apparatus includes
EtherCAT main website, several slave stations of EtherCAT, the main website of the first bus and the first bus several slave stations, the time is same
One step process includes:
Control system is constructed, the control system includes: the EtherCAT main website, the first slave station of EtherCAT and described
The main website of first bus, first slave station of EtherCAT are one in several slave stations of EtherCAT；
EtherCAT main website passes through current time and bus communication period when the control system initializes
EtherCAT is sent to the first slave station of EtherCAT；
The first slave station of EtherCAT is in bus apparatus periodic communication, using the local clock of the first slave station of EtherCAT as base
Punctual clock generates periodic synchronization signal according to the reference clock, and the synchronization signal is sent to the first bus
Main website；
After receiving the synchronization signal, the slave station of the first bus of Xiang Suoshu sends data frame for the main website of first bus,
And synchronizing information is sent to EtherCAT main website；
EtherCAT main website after receiving the synchronizing information, by EtherCAT by the first slave station of EtherCAT when
Between information be distributed to remaining EtherCAT slave station in several slave stations of EtherCAT.
Preferably, the EtherCAT main website includes control computer and ethernet controller, the control computer is also
For controlling EtherCAT communication and processing data, the ethernet controller is also used to sending and receiving data frame.
Preferably, the control computer is when the control system initializes, by current time and bus communication period
The first slave station of EtherCAT is sent to by EtherCAT；
After receiving the synchronization signal, the slave station of the first bus of Xiang Suoshu sends data frame for the main website of first bus,
And synchronizing information is sent to the control computer；
The control computer is after receiving the synchronizing information, by EtherCAT by the first slave station of EtherCAT
Temporal information is distributed to remaining EtherCAT slave station.
Preferably, the EtherCAT main website further include:
The control computer is substituted with programmable logic device, to control EtherCAT communication and processing data；
And/or the ethernet controller is substituted with ASIC, to sending and receiving data frame.
Preferably, first bus is RTEX bus or Mechatrolink-II/III bus.
On the basis of common knowledge of the art, above-mentioned each optimum condition, can any combination to get each preferable reality of the present invention
Example.
The positive effect of the present invention is that: the present invention is integrated into using the first slave station of EtherCAT as system clock source
Inside the control system, the communication cycle that other buses are controlled by the first slave station of EtherCAT, realizes time synchronization.The present invention
Time on middle different bus is realized by the hardware circuit of control system to be synchronized, and EtherCAT main website is simultaneously not involved in, therefore can
To completely eliminate time jitter caused by EtherCAT main website real-time difference in synchronizing process.
Detailed description of the invention
Fig. 1 is the time synchronization schematic diagram of EtherCAT main website and slave station in the prior art.
Fig. 2 is the time synchronization schematic diagram of RTEX, Mechatrolink-II/III main website and slave station in the prior art.
Fig. 3 is the time synchronization schematic diagram of EtherCAT bus and Mechatrolink-II/III bus in the prior art.
Fig. 4 is the schematic block diagram of the clock synchronization system of the digital control system bus apparatus of present pre-ferred embodiments.
Fig. 5 is the flow chart of the method for synchronizing time of the digital control system bus apparatus of present pre-ferred embodiments.
Specific embodiment
The present invention is further illustrated below by the mode of embodiment, but does not therefore limit the present invention to the reality
It applies among a range.
Embodiment
A kind of clock synchronization system of digital control system bus apparatus, as shown in figure 4, bus apparatus includes EtherCAT master
It stands, several slave stations of the main website of several slave stations of EtherCAT, the first bus and the first bus.Line not with the arrow indicates in figure
The connection relationship of each module, line with the arrow indicate the direction of time distribution.
Wherein, the function of the EtherCAT main website is transmitting-receiving EtherCAT data frame, realizes the data with slave station equipment
Exchange.Since the data frame structure of EtherCAT is compatible with standard ethernet, can be realized using the ethernet controller of standard
The transmitting-receiving of EtherCAT data frame.In the present embodiment, EtherCAT main website includes controlling computer 31 and ethernet controller 32,
The control computer 31 is used for sending and receiving data for controlling EtherCAT communication and processing data, the ethernet controller 32
Frame.The control computer 31 is connect with the ethernet controller 32, if the ethernet controller 32 and EtherCAT
Dry slave station is sequentially connected with, and the slave station of EtherCAT shown in figure includes 4, respectively the first slave station 331, the second slave station 332,
Third slave station 333 and the 4th slave station 334.
First bus is RTEX bus or Mechatrolink-II/III bus.The main website of first bus is
ASIC or programmable logic device (PLD), i.e. ASIC/PLD 34 in Fig. 4, the main website of first bus and the first bus
Several slave stations are sequentially connected with, and the slave station of EtherCAT shown in figure includes 3, respectively the 5th slave station 351, the 6th slave station
352 and the 7th slave station 353.
The clock synchronization system includes: control system 4.The control system 4 include: the EtherCAT main website (i.e.
Including the control computer 31 and the ethernet controller 32), the first slave station of EtherCAT 331 and first bus
Main website (i.e. ASIC/PLD 34 in Fig. 4).First slave station of EtherCAT 331 is also connect with the main website of first bus.
Wherein, first slave station of EtherCAT 331 recently and has generation lock-out pulse (SYNC) signal from EtherCAT main website
Function generates arteries and veins that is, according to the local clock of the first slave station of EtherCAT 331 with the preset time interval of EtherCAT main website
Punching.
The control computer 31 is used in the control system 4 initialization, by current time and bus communication period
The first slave station of EtherCAT 331 is sent to by EtherCAT.
The first slave station of EtherCAT 331 is used in bus apparatus periodic communication, with the sheet of the first slave station of EtherCAT 331
Ground clock is benchmark clock, generates periodic synchronization signal according to the reference clock, and the synchronization signal is sent to
1. the main website of first bus, i.e. arrow in Fig. 4, indicate to send synchronization signal from the first slave station 331 to ASIC/PLD 34, with
This realizes the time synchronization of the main website of EtherCAT and the first bus.Wherein, the synchronization signal is SYNC signal.
The main website of first bus is used for after receiving the synchronization signal, and the slave station of the first bus of Xiang Suoshu is sent
Data frame, i.e. arrow in Fig. 4 2., indicate from ASIC/PLD 34 respectively to the 5th slave station 351, the 6th slave station 352 and the 7th from
Stand 353 send data frames, with this realize first bus main website and first bus slave station time synchronization.
The main website of first bus is also used to after receiving the synchronization signal, and synchronizing information is sent to the control
3. computer 31 processed, i.e. arrow in Fig. 4, indicate to send synchronizing information from ASIC/PLD 34 to control computer 31, with this reality
The time synchronization of the main website of existing first bus and the control computer 31.Wherein, the synchronizing information can be the synchronization
Signal or interrupt signal.
EtherCAT main website is also used to after receiving the synchronizing information, by EtherCAT by EtherCAT first from
The temporal information stood is distributed to remaining EtherCAT slave station, i.e. arrow in Fig. 4 4., indicate from the first slave station 331 respectively to
Second slave station 332,334 transmission time information of third slave station 333 and the 4th slave station realize the first slave station of EtherCAT and its with this
The time synchronization of remaining EtherCAT slave station.
The time synchronization of all bus apparatus is realized by the clock synchronization system, and is controlled computer 31 and do not needed
Any time information is forwarded, temporal shake would not be also introduced, it is poor fundamentally to solve control 31 real-time of computer
Caused time jitter problem, ensure that the synchronization of time.
In addition, the EtherCAT main website can also substitute the control computer 31 with programmable logic device, to
Control EtherCAT communication and processing data；And/or the ethernet controller 32 is substituted with ASIC, to sending and receiving data frame.
It should be noted that the control system 4 includes the first slave station of EtherCAT, the first slave station of EtherCAT is provided
Reference clock, reference clock are not necessarily intended to be integrated on the circuit board of control system or in controller, also can integrate at it
In the ASIC or PLD of his type bus main website, the EtherCAT equipment outside control system also can be used, pass through circuit connecting wire
Realize time synchronization.
Slave station in EtherCAT bus other than the first slave station may be that system provides reference clock.
The synchronization signal of the present embodiment is not limited only to the SYNC signal using standard, when other also can be used based on benchmark
The signal of clock, or the time of reference clock is directly sent to the master device of other buses.
The method for synchronizing time of a kind of digital control system bus apparatus of the present embodiment, as shown in figure 4, bus apparatus includes
EtherCAT main website, several slave stations of EtherCAT, the main website of the first bus and the first bus several slave stations.
EtherCAT main website includes control computer 31 and ethernet controller 32, and the control computer 31 is for controlling
EtherCAT communication and processing data, the ethernet controller 32 are used for sending and receiving data frame.The control computer 31 and institute
The connection of ethernet controller 32 is stated, several slave stations of the ethernet controller 32 and EtherCAT are sequentially connected with, show in figure
EtherCAT slave station include 4, respectively the first slave station 331, the second slave station 332, third slave station 333 and the 4th slave station
334。
First bus is RTEX bus or Mechatrolink-II/III bus.The main website of first bus is
ASIC or programmable logic device (PLD), i.e. ASIC/PLD 34 in Fig. 4, the main website of first bus and the first bus
Several slave stations are sequentially connected with, and the slave station of EtherCAT shown in figure includes 3, respectively the 5th slave station 351, the 6th slave station
352 and the 7th slave station 353.
As shown in figure 5, the method for synchronizing time includes:
Step 501, building control system 4, the control system 4 include: that the EtherCAT main website (includes the control
Computer 31 processed and the ethernet controller 32), the main website of the first slave station of EtherCAT and first bus is (i.e. in Fig. 4
ASIC/PLD 34) first slave station of EtherCAT 331 also connect with the main website of first bus.Wherein, described
The first slave station of EtherCAT 331 recently and has the function of generating lock-out pulse (SYNC) signal, i.e. root from EtherCAT main website
According to the local clock of the first slave station of EtherCAT 331, pulse is generated with the preset time interval of EtherCAT main website.
Step 502, the control computer 31 are when the control system initializes, by current time and bus communication week
Phase is sent to the first slave station of EtherCAT 331 by EtherCAT.
Step 503, the first slave station of EtherCAT 331 are in bus apparatus periodic communication, with the first slave station of EtherCAT
Local clock is benchmark clock, generates periodic synchronization signal according to the reference clock, and the synchronization signal is sent
To the main website of the first bus, i.e. 1. arrow in Fig. 4, indicates to send synchronization signal from the first slave station 331 to ASIC/PLD 34,
With the time synchronization of this main website for realizing EtherCAT and the first bus.Wherein, the synchronization signal is SYNC signal.
Step 504, the first bus main website after receiving the synchronization signal, the slave station of the first bus of Xiang Suoshu is sent
2. and 3. data frame, and synchronizing information is sent to the control computer 31, i.e. arrow in Fig. 4, are indicated by ASIC/
PLD 34 sends data frame to the 5th slave station 351, the 6th slave station 352 and the 7th slave station 353 respectively, realizes that described first is total with this
The time synchronization of the main website of line and the slave station of first bus, and indicate to be sent out from ASIC/PLD 34 to control computer 31
Synchronizing information is sent, the main website of the first bus and the time synchronization of the control computer 31 are realized with this.Wherein, the synchronous letter
Breath can be the synchronization signal or interrupt signal.
Step 505, EtherCAT main website are after receiving the synchronizing information, by EtherCAT by EtherCAT first
The temporal information of slave station is distributed to remaining EtherCAT slave station in several slave stations of EtherCAT, i.e. arrow in Fig. 4 4., table
Show from the first slave station 331 respectively to the second slave station 332,334 transmission time information of third slave station 333 and the 4th slave station, with this reality
The time synchronization of existing EtherCAT the first slave station and remaining EtherCAT slave station.
The time synchronization of all bus apparatus is realized by the method for synchronizing time, and is controlled computer 31 and do not needed
Any time information is forwarded, temporal shake would not be also introduced, it is poor fundamentally to solve control 31 real-time of computer
Caused time jitter problem, ensure that the synchronization of time.
In addition, the EtherCAT main website can also substitute the control computer 31 with programmable logic device, to
Control EtherCAT communication and processing data；And/or the ethernet controller 32 is substituted with ASIC, to sending and receiving data frame.
Although specific embodiments of the present invention have been described above, it will be appreciated by those of skill in the art that these
It is merely illustrative of, protection scope of the present invention is defined by the appended claims.Those skilled in the art is not carrying on the back
Under the premise of from the principle and substance of the present invention, many changes and modifications may be made, but these are changed
Protection scope of the present invention is each fallen with modification.
Claims (10)
1. a kind of clock synchronization system of digital control system bus apparatus, which is characterized in that bus apparatus include EtherCAT main website,
Several slave stations of several slave stations of EtherCAT, the main website of the first bus and the first bus, the clock synchronization system include: control
System processed；
The control system includes: the main website of the EtherCAT main website, the first slave station of EtherCAT and first bus, institute
State one in several slave stations that the first slave station of EtherCAT is EtherCAT；
EtherCAT main website is used to pass through current time and bus communication period in control system initialization
EtherCAT is sent to the first slave station of EtherCAT；
The first slave station of EtherCAT is used in bus apparatus periodic communication, using the local clock of the first slave station of EtherCAT as base
Punctual clock generates periodic synchronization signal according to the reference clock, and the synchronization signal is sent to the first bus
Main website；
The main website of first bus is used for after receiving the synchronization signal, and the slave station of the first bus of Xiang Suoshu sends data frame,
And synchronizing information is sent to EtherCAT main website；
After EtherCAT main website receives the synchronizing information, the first slave station of EtherCAT passes through EtherCAT for temporal information
It is distributed to remaining EtherCAT slave station in several slave stations of EtherCAT.
2. clock synchronization system as described in claim 1, which is characterized in that the EtherCAT main website includes control computer
And ethernet controller, the control computer are also used to control EtherCAT communication and processing data, the Ethernet control
Device is also used to sending and receiving data frame.
3. clock synchronization system as claimed in claim 2, which is characterized in that the control computer is used in control system
When system initialization, current time and bus communication period are sent to the first slave station of EtherCAT by EtherCAT；
The main website of first bus is used for after receiving the synchronization signal, and the slave station of the first bus of Xiang Suoshu sends data frame,
And synchronizing information is sent to the control computer；
The control computer is also used to after receiving the synchronizing information, by EtherCAT by the first slave station of EtherCAT
Temporal information be distributed to remaining EtherCAT slave station.
4. clock synchronization system as claimed in claim 2 or claim 3, which is characterized in that the EtherCAT main website further include:
The control computer is substituted with programmable logic device, to control EtherCAT communication and processing data；
And/or the ethernet controller is substituted with ASIC, to sending and receiving data frame.
5. clock synchronization system as described in claim 1, which is characterized in that first bus be RTEX bus or
Mechatrolink-II/III bus.
6. a kind of method for synchronizing time of digital control system bus apparatus, which is characterized in that bus apparatus include EtherCAT main website,
Several slave stations of several slave stations of EtherCAT, the main website of the first bus and the first bus, the method for synchronizing time include:
Control system is constructed, the control system includes: the EtherCAT main website, the first slave station of EtherCAT and described first
The main website of bus, first slave station of EtherCAT are one in several slave stations of EtherCAT；
EtherCAT main website is sent out when the control system initializes, by current time and bus communication period by EtherCAT
Give the first slave station of EtherCAT；
The first slave station of EtherCAT is in bus apparatus periodic communication, when using the local clock of the first slave station of EtherCAT as benchmark
Clock generates periodic synchronization signal according to the reference clock, and the synchronization signal is sent to the main website of the first bus；
After receiving the synchronization signal, the slave station of the first bus of Xiang Suoshu sends data frame for the main website of first bus, and
Synchronizing information is sent to EtherCAT main website；
After EtherCAT main website receives the synchronizing information, the first slave station of EtherCAT passes through EtherCAT for temporal information
It is distributed to remaining EtherCAT slave station in several slave stations of EtherCAT.
7. the method for synchronizing time of digital control system bus apparatus as claimed in claim 6, which is characterized in that the EtherCAT
Main website includes control computer and ethernet controller, and the control computer is also used to control EtherCAT communication and processing number
According to the ethernet controller is also used to sending and receiving data frame.
8. method for synchronizing time as claimed in claim 7, which is characterized in that the control computer is at the beginning of the control system
When beginningization, current time and bus communication period are sent to the first slave station of EtherCAT by EtherCAT；
After receiving the synchronization signal, the slave station of the first bus of Xiang Suoshu sends data frame for the main website of first bus, and
The synchronization signal is sent to the control computer；
The control computer is after receiving the synchronization signal, by EtherCAT by the time of the first slave station of EtherCAT
Information is distributed to remaining EtherCAT slave station.
9. method for synchronizing time as claimed in claim 7 or 8, which is characterized in that the EtherCAT main website further include:
The control computer is substituted with programmable logic device, to control EtherCAT communication and processing data；
And/or the ethernet controller is substituted with ASIC, to sending and receiving data frame.
10. method for synchronizing time as claimed in claim 6, which is characterized in that first bus be RTEX bus or
Mechatrolink-II/III bus.
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| CN108768573B (en) * | 2018-04-13 | 2020-02-21 | 北京东土科技股份有限公司 | A clock synchronization method and device |
| CN109947030A (en) * | 2019-04-12 | 2019-06-28 | 南京埃斯顿自动化股份有限公司 | The method in dynamic following EtherCat bus synchronous period in servo internal control period |
| CN110932954A (en) * | 2019-11-20 | 2020-03-27 | 广东水利电力职业技术学院（广东省水利电力技工学校） | EtherCAT bus clock distribution system |
| CN111478834B (en) * | 2020-03-25 | 2022-04-29 | 武汉迈信电气技术有限公司 | EtherCAT master station synchronization method based on non-real-time system |
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| CN102325019A (en) * | 2011-08-23 | 2012-01-18 | 西安电子科技大学 | A Clock Synchronization Method for Real-time Industrial Ethernet EtherCAT Redundant System |
| CN104539412A (en) * | 2014-12-30 | 2015-04-22 | 深圳市英威腾电气股份有限公司 | Ethercat master-slave synchronization method and device and master-slave station system |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102325019A (en) * | 2011-08-23 | 2012-01-18 | 西安电子科技大学 | A Clock Synchronization Method for Real-time Industrial Ethernet EtherCAT Redundant System |
| CN104539412A (en) * | 2014-12-30 | 2015-04-22 | 深圳市英威腾电气股份有限公司 | Ethercat master-slave synchronization method and device and master-slave station system |
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