CN107464812A - A kind of manufacture method of semiconductor devices - Google Patents
A kind of manufacture method of semiconductor devices Download PDFInfo
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- CN107464812A CN107464812A CN201610331056.4A CN201610331056A CN107464812A CN 107464812 A CN107464812 A CN 107464812A CN 201610331056 A CN201610331056 A CN 201610331056A CN 107464812 A CN107464812 A CN 107464812A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The present invention provides a kind of manufacture method of semiconductor devices, is related to technical field of semiconductors.Including：Semiconductor substrate is provided, on a semiconductor substrate formed with target material layer；The core pattern by several mutually isolated strips of opening is formed in target material layer, and clearance wall is formed in the side wall of core pattern；The sacrifice layer that clearance wall, core pattern and target material layer are stated in covering is formed, the top surface of sacrifice layer is higher than the top surface of clearance wall；Circulation performs the first etch-back step and the second etch-back step several times successively, wherein, the etching of the first etch-back step removes partial sacrificial layer, and the etching of the second etch-back step removes portion gap wall；Remove remaining sacrifice layer and remaining core pattern；Using remaining clearance wall as mask, target material layer is etched, to form some grooves being located in target material layer.The method according to the invention, avoid clearance wall and collapse the appearance of problem, improve the yield and performance of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of system of semiconductor devices
Make method.
Background technology
Increasingly increase for the semiconductor storage demand of high power capacity, these semiconductors are deposited
The integration density of storage device is concerned by people, in order to increase the collection of semiconductor storage
Into density, many different methods are employed in the prior art, such as by reducing chip chi
It is very little and/or change inner structure unit and multiple memory cell are formed on single wafer, for
For the method for increasing integration density by changing cellular construction, trial ditch is carried out and has passed through
Change the horizontal layout of active area or change cell layout and carry out reduction unit area.
Nand flash memory is a kind of storage scheme more more preferable than hard disk drive, due to NAND
Flash memory reads and writes data in units of page, so be suitable for storing continuous data, as picture,
Audio or alternative document data；Simultaneously because its cost is low, capacity is big and writing speed is fast, wipes
Except the advantages of time is short, is in the field of storage of device for mobile communication and portable multimedia device
It is widely used.
During nand flash memory is prepared, spacer patterns technology (Spacer
Patterning technology, SPT) and self-aligned double patterning case technology (self aligned
Double patterning, SaDPT) it can be used for preparing the transistor (example of nanoscale
Such as, MOSFET).
The cardinal principle of SADP technologies is：First in preformed core (core) pattern two
Side forms clearance wall (spacer), then removes core pattern to form clearance wall, and pass through etching
The pattern of clearance wall is transferred in target material layer by technique, so that can be formed in unit area
Number of patterns it is double, i.e., the minimum spacing (pitch) between pattern can be decreased to the two of CD
/ mono-.In order to realize the high density of integration of nand flash memory, pattern film in preparation process
Lamination be pattern transfer and transmit width uniformity (Critical Dimension Uniformity,
CDU key).However, using the 24nm of SADP technologies and with lower node NAND
In the back end of line (BEOL) of flash memory, the problem of clearance wall of formation is easy to collapse,
And then cause the pattern distortion (for example, metal line pattern) formed in target material layer, from
And influence the performance and yield of semiconductor devices.
Therefore, in order to solve the above technical problems, being necessary to propose a kind of new semiconductor devices
Manufacture method.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply and be further described in mode part.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean to attempt the protection domain for determining technical scheme claimed.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of semiconductor devices
Manufacture method, methods described include：
Semiconductor substrate is provided, on the semiconductor substrate formed with target material layer；
The core by several mutually isolated strips of opening is formed in the target material layer
Pattern, and form clearance wall in the side wall of the core pattern；
The sacrifice layer for covering the clearance wall, the core pattern and the target material layer is formed,
The top surface of the sacrifice layer is higher than the top surface of the clearance wall；
Circulation performs the first etch-back step and the second etch-back step several times successively, wherein,
The first etch-back step etching removes the part sacrifice layer, makes remaining described sacrificial
The top surface of domestic animal layer is less than the top surface of the clearance wall higher than the top surface of the target material layer,
The etching of second etch-back step removes the part clearance wall, makes the remaining clearance wall
Top surface higher than the target material layer top surface be less than the remaining sacrifice layer top surface；
Remove the remaining sacrifice layer and the remaining core pattern；
Using the remaining clearance wall as mask, the target material layer is etched, is located at being formed
Some grooves in the target material layer.
Further, it is described to be more than or equal to 2 several times.
Further, the sacrifice layer includes Spun-on carbon.
Further, using based on O2、CO2、CO、N2、H2Or the plasma of its combination
Carry out the first etch-back step.
Further, using CxFyDry plasma etch process realization pair as etchant
Second etch-back step of the clearance wall.
Further, before the core pattern is formed, it is additionally included in the table of the target material layer
The step of metal hard mask layer is formed on face.
Further, the core pattern is bottom antireflective coating.
Further, the step of forming the core pattern and the clearance wall includes：
Bottom antireflective coating and low temperature oxide layer are sequentially formed in the target material layer；
The core photoresist of several spaced strips is formed in the low temperature oxide layer
Layer；
Using the core photoresist layer as mask, the low temperature oxide layer and the bottom are etched successively
Portion's ARC, to be formed by several mutually isolated core patterns of opening, and remove institute
State core photoresist layer；
Shape is deposited on the surface of the core pattern and on the surface of target material layer exposure
Into spacer material layer；
The spacer material layer is etched, between being formed in each core pattern sidewalls
Gap wall.
Further, the target material layer is interlayer dielectric layer.
Further, the material of the clearance wall includes oxide, nitride or its combination.
Further, deposit to form the spacer material layer using atomic layer deposition method.
Further, also etch and remove described in part simultaneously when performing the first etch-back step
Core pattern.
In summary, manufacturing method according to the invention, by circulate perform several times to sacrificial
First etch-back step of domestic animal layer and the second etch-back step to clearance wall, to reduce clearance wall
Height, avoid clearance wall and collapse the appearance of problem, and then make it that the pattern of clearance wall can essence
Target material layer really is transferred to, improves the yield and performance of device.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
The structure that the key step of Figure 1A to Fig. 1 F routine SADP technical matters processes is formed
Sectional view；
When Fig. 2A shows that spacer pattern is collapsed during conventional SADP technical matters
Structure top view；
Fig. 2 B, which are shown, to be corresponded to go out along Fig. 2 B section lines AA ' spacer patterns obtained
The sectional view of structure when now collapsing；
Fig. 3 A-3J show a kind of manufacture of semiconductor devices in one embodiment of the invention
The sectional view for the structure that the correlation step of method is formed；
Fig. 4 is a kind of signal of the manufacture method of semiconductor devices of one embodiment of the invention
Property flow chart.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is it is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, those skilled in the art be will fully convey the scope of the invention to and.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated.It is identical attached from beginning to end
Icon note represents identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term limits.These terms be used merely to distinguish an element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., herein can for convenience description and by use from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.For example, if the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, "one" and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, the presence or addition of element, part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
Herein with reference to the horizontal stroke of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Sectional view come describe invention embodiment.As a result, it is contemplated that due to such as manufacturing technology and/
Or from the change of shown shape caused by tolerance.Therefore, embodiments of the invention should not limit to
Given shape in area shown here, but it is inclined including the shape caused by for example manufacturing
Difference.For example, be shown as the injection region of rectangle generally has circle at its edge or bending features and
/ or implantation concentration gradient, rather than the binary change from injection region to non-injection regions.Equally,
The surface passed through when by injecting the disposal area formed the disposal area and injection can be caused to carry out
Between area in some injection.Therefore, the area shown in figure is substantially schematical, it
Shape be not intended display device area true form and be not intended limit the present invention
Scope.
In order to thoroughly understand the present invention, will be proposed in following description detailed step and in detail
Thin structure, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is detailed
Carefully it is described as follows, but in addition to these detailed descriptions, the present invention can also have other implementations
Mode.
Below, the main bag with reference to figure 1A- Fig. 1 F to the SADP technical matters processes of routine
Processing step is included to be briefly described.
First, as shown in Figure 1A, there is provided Semiconductor substrate (not shown), partly led described
Ultra-low-k dielectric layer 100 is sequentially formed with body substrate, metal hard mask layer 101, bottom resist
Reflectance coating 102a and low temperature oxide layer 103, on the low temperature oxide layer 103a
The photoresist layer 104 of patterning is formed, wherein the definition of photoresist layer 104 of the patterning has
The size of the predetermined core pattern formed and position.
Then, as shown in Figure 1B, with the photoresist layer 104 of the patterning be mask successively
The low temperature oxide layer 103a and the bottom antireflective coating 102a are etched, between formation
Every several core patterns 102 of setting.
Then, as shown in Figure 1 C, on the surface of the core pattern 102 and exposure gold
Belong to deposition on the surface of hard mask layer 101 and form spacer material layer 105a.
Then, as shown in figure iD, dry method etch technology etched gap wall material bed of material 105a is carried out,
The clearance wall 105 formed in the side wall of core pattern 102.Wherein, in this step, it is located at
Low temperature oxide layer 103a on the core pattern 102 is also etched removal.
Then, as referring to figure 1E, it is described to remove remaining core pattern 102, to form opening
The adjacent clearance wall 105 of 106 isolation.
Then, as shown in fig. 1F, it is mask with the clearance wall 105, etches the target
Material layer 100, to form some grooves 107 being located in the target material layer 100.
However, use the 24nm of SADP technologies and with lower node nand flash memory after
Hold in processing procedure (BEOL), isolate adjacent clearance wall 105 removing core pattern to form opening
The step of in, it is easy to there is the problem of clearance wall 105 collapses, such as Fig. 2A and Fig. 2 B institutes
Show, wherein Fig. 2 B show the corresponding clearance wall figure obtained along Fig. 2A section lines AA '
The sectional view of structure when case is collapsed, after clearance wall 105 collapses so that in target material
The pattern distortion (for example, metal line pattern) formed on layer, so as to influence semiconductor devices
Performance and yield.
Therefore, in view of the presence of above-mentioned technical problem, the present invention propose a kind of new semiconductor device
The manufacture method of part, as shown in figure 4, the manufacture method includes following key step：
In step S401, there is provided Semiconductor substrate, on the semiconductor substrate formed with
Target material layer；
In step S402, formed in the target material layer mutually isolated by opening
Several core patterns, and form clearance wall in the side wall of the core pattern；
In step S403, formed and cover clearance wall, the core pattern and the target
The sacrifice layer of material layer, the top surface of the sacrifice layer are higher than the top surface of the clearance wall；
In step s 404, circulation performs the first etch-back step and the second etch-back step successively
Suddenly several times, wherein,
The first etch-back step etching removes the part sacrifice layer, makes remaining described sacrificial
The top surface of domestic animal layer is less than the top surface of the clearance wall higher than the top surface of the target material layer,
The etching of second etch-back step removes the part clearance wall, makes the remaining clearance wall
Top surface higher than the target material layer top surface be less than the remaining sacrifice layer top surface；
In step S405, the remaining sacrifice layer and the remaining core pattern are removed；
In step S406, using the remaining clearance wall as mask, the target material is etched
The bed of material, to form the groove being located in the target material layer.
Manufacturing method according to the invention, by circulate perform several times to the first of sacrifice layer
Etch-back step and the second etch-back step to clearance wall, to reduce the height of clearance wall, keep away
Exempt from clearance wall to collapse the appearance of problem, and then cause the pattern of clearance wall to be accurately transferred to mesh
Material layer is marked, improves the yield and performance of device.
Below, Fig. 3 A- Fig. 3 J do to the manufacture method of the semiconductor devices of the present invention and retouched in detail
State, wherein, Fig. 3 A-3J show a kind of semiconductor devices in one embodiment of the invention
The sectional view for the structure that the correlation step of manufacture method is formed.
As an example, using the 24nm of SADP technologies and with lower node nand flash memory
Back end of line (BEOL) in, the manufacture method of semiconductor devices of the invention includes following
Step：
First, as shown in Figure 3A, there is provided Semiconductor substrate (not shown), partly led described
Formed with target material layer 200 on body substrate.
The Semiconductor substrate can be at least one of following material being previously mentioned：Silicon, absolutely
Silicon (SOI) on edge body, silicon (SSOI) is laminated on insulator, is laminated SiGe on insulator
(S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI)
Deng.
Preferably, isolation structure, the isolation can also be formed in the Semiconductor substrate
Structure is that shallow trench isolates (STI) structure or selective oxidation silicon (LOCOS) isolation structure.At this
Shallow trench isolation is preferably formed as in invention, various traps (well) are also formed with the Semiconductor substrate
The channel layer of structure and substrate surface.In general, the ion doping of trap (well) structure is formed
Conduction type is identical with channel layer ion doping conduction type, but concentration is compared with gate channel layer
Low, the depth of ion implanting is general to enclose relatively extensively, while need to reach the depth more than isolation structure.
In addition, active area can be defined in Semiconductor substrate.It can also wrap on the active region
Containing other active devices, for convenience, do not indicated in shown figure.
Preferably, can further form the grid structure on the substrate, can also enter
One step is included in the step of grid both sides form source-drain area, specifically, can pass through ion implanting
Or the method for diffusion forms the source-drain area, as it is further preferably, carrying out ion
A step of thermal annealing being can further include after injection or diffusion.The formation of the grid
Process can select method commonly used in the art, will not be repeated here.
It is noted that the making of front-end devices has been completed on the semiconductor substrate,
In order to which simplicity is not shown in figure, back end of line of the present embodiment mainly for semiconductor devices
(The back end of line, BEOL), for example, the NAND of 24nm processing procedures rear end system
Journey.
Target material layer 200 can be formed in interconnection wiring layer on substrate, interlayer dielectric
Layer, gate material layers or hard mask layer.The constituent material of the interconnection wiring layer be selected from tungsten,
At least one of tungsten silicide, aluminium, titanium and titanium nitride.
The constituent material of the interlayer dielectric layer can be selected from low-k (k) material or super
Low-k materials, low-k materials refer to the dielectric material that dielectric constant (k values) is less than 4, ultralow
K materials refer to the dielectric material that dielectric constant (k values) is less than 2.5.Generally use chemistry gas
Prepared by phase spin coating proceeding (SOG), whirl coating technology or chemical vapour deposition technique, its material
Can be silica glass (FSG), silica (silicon oxide), carbonaceous material, hole material
Expect (porous-like material) or homologue.As an example, ultralow-k material film is hole
Property material in hole includes pore-foaming agent, and pore-foaming agent can be any suitable material for producing hole, cause
Hole agent material can be hydrocarbon, the acrylates (acrylate) containing resist
The polymer of race, polymer of fluorination etc..Can be in a furnace or real by other techniques
Apply solidification, such as ultraviolet curing, rapid thermosetting, flash lamp solidification, laser curing etc..
Ultralow-k material film can also be selected from the common dielectric constant (k values) in this area and be less than 2.5
Material, for example, k values be 2.2 methane-siliconic acid salt compound (Methyl Silsesquioxane,
Abbreviation MSQ).
The one kind of the constituent material of the gate material layers in polysilicon and aluminium.It is described to cover firmly
The constituent material of film layer be selected from oxide, undoped silicon glass, silicon-on-glass, SiON, SiN,
At least one of SiBN, BN and high-g value.
Wherein, in the present embodiment, target material layer 200 is interlayer dielectric layer.
In one example, it is also formed with metallic hard on the surface of the target material layer 200
Mask layer 201.
Metal hard mask layer 201 can be improved to the oxide above metal hard mask layer with
The etching selection rate of the oxide in face, specifically, carry out pattern transfer when only to oxide
Etching, the metal hard mask layer 201 will not be etched, in this layer and following target
Material layer 200 plays a protective role, in addition, will scheme etching the metal hard mask layer 201
Following target material layer 200 will not also be made when case is transferred to the metal hard mask layer 201
Into influence.As long as it can realize that the metal hard mask layer 201 of the purpose can apply to
The present invention, in the present embodiment, the metal hard mask layer 201 can be TiN, BN or
Cu3N, during from above-mentioned three kinds of materials, its effect is more preferable, contraposition thereon, under oxygen
The selection rate of compound is higher, and the accuracy of pattern is higher during etching, and half be prepared
The integration density of conductor device is big, and memory capacity is bigger.
Metal hard mask layer 201 is alternative to be set, it is also possible to which other hard mask materials replace
For the metal hard mask layer 201, such as SiN, SiCN etc..
Then, as shown in Figure 3 D, formed in the target material layer 200 and pass through opening phase
Several core patterns 202 mutually isolated, and in the side wall of the core pattern 202 between formation
Gap wall 205.
In one example, the side by several mutually isolated core patterns 202 of opening is formed
Method comprises the following steps：
First, shown in Fig. 3 A, on the metal hard mask layer 201 sequentially forming bottom resists
Reflectance coating 202a and low temperature oxide layer 203a.
Bottom antireflective coating (Bottom Anti Reflective Coating, BARC) can be with
Using spin-coating organic polymer composition formula, dedicated for specific lithographic wavelength technique, including i-
Line, 248nm, 193nm and 193nm submergence, they are coated on wafer prior to photoresist,
And must be compatible in aspect of performance with photoresist；Bottom antireflective coating is water-soluble polymer,
For being reflected above photoresist as composite bed with reducing light in exposure device, so as to realize more preferably
Line width control, it is also possible to make reduce it is anti-light resistance erosion/gaseous volatilization/defect protective layer.Bottom
The structure of portion's anti-reflective coating one polymer generally includes two parts：Crosslink part and hydrophobic grouping.
The low temperature oxide layer can be formed with using plasma chemical vapor deposition method
(LTO) 203a, with SiH4And N2For O as reacting gas, temperature is 150 DEG C~300 DEG C,
The material of the low temperature oxide layer 101 is silica, the thickness of the low temperature oxide layer 203a
Spend and be
Then, continue as shown in Figure 3A, between being formed on the low temperature oxide layer 203a
Every the core photoresist layer 204 of several strips of arrangement.
Wherein, the forming method of the core photoresist layer 204 includes：First in low temperature oxide
Spin coating photoresist layer on layer 203a, then be exposed the photoetching processes such as development and photoresist layer is entered
Row patterning, to form several spaced core photoresist layers 204, wherein, core photoetching
Identical distance is spaced between glue-line 204.And the region of each covering of core photoresist layer 204 is
The region of preboarding nucleation patterns, and define the shape and size of core pattern.
Then, as shown in Figure 3 B, it is mask with the core photoresist layer 204, etches successively
The low temperature oxide layer 203a and bottom antireflective coating 202a, stops at the gold
Belong on the surface of hard mask layer 201, to be formed by several mutually isolated core patterns of opening
202, and remove the core photoresist layer 204.
It can be carried out by any engraving method well known to those skilled in the art to the cryogenic oxygen
Compound layer 203a and the bottom antireflective coating 202a etching, wherein it is possible to using dry
Method etches, and dry method etch technology includes but is not limited to：Reactive ion etching (RIE), ion beam
Etching, plasma etching or laser cutting.Bottom antireflective coating conduct after patterning
Core pattern 202.
The methods of method or wet-cleaning that ashing can be used, removes the core photoresist layer
204。
Afterwards, clearance wall can be formed in the side wall of core pattern 202, specific step can wrap
Include：
First, as shown in Figure 3 C, on the surface of the core pattern 202 and the metallic hard
Deposition forms spacer material layer 205a on the surface that mask layer 201 exposes.
The spacer material layer 205a can be oxide, nitride, oxynitride or its
Combination.It can be formed using any deposition process well known to those skilled in the art, including it is but unlimited
In chemical vapour deposition technique, physical vaporous deposition or atomic layer deposition method.In the present embodiment,
It is preferred that deposit to form the spacer material layer 205a using atomic layer deposition method.
Wherein, spacer material layer 205a is also formed on low temperature oxide layer 203a surfaces.
Afterwards, the spacer material layer 205a is etched, to be formed positioned at each core figure
Clearance wall 205 in the side wall of case 202.
The spacer material layer is etched from dry etching, in the present invention using CxFy
Dry plasma etch process as etchant is realized to the spacer material layer 205a
Etching, the CxFyEtchant can be CF4、CHF3、C4F8And C5F8In one kind
It is or a variety of.In the embodiment of the present invention, the dry etching can select CF4、
CHF3, in addition plus N2、CO2In a kind of as etching atmosphere, wherein gas flow be
CF410-200sccm, CHF310-200sccm, N2Or CO2Or O210-400sccm, institute
It is 30-150mTorr, preferably etching period 5-120s, 5-60s to state etching pressure, more excellent
Elect 5-30s as.
Due to the presence of the difference in height of the top and bottom of height core pattern, therefore in the step
Etching is mainly for the part on the top of core pattern and the surface of metal hard mask layer 202
Spacer material layer, to form the clearance wall 205 being only located in the side wall of core pattern 202.
Exemplarily, the spacing between adjacent segment wall 205 is equal, and it is essentially equal to pre-
It is scheduled on the size of the pattern formed in target material layer 200.
Wherein, in this step, the low temperature oxide layer 203a on the core pattern 202
Also removal is etched, only lefts in bottom antireflective coating as core pattern 202.
Then, as shown in Figure 3 D, formed and cover the clearance wall 205, the core pattern 202
With the sacrifice layer 206 of the target material layer 200, the top surface of the sacrifice layer 206 is higher than institute
State the top surface of clearance wall 205.
The material of the sacrifice layer 206, which can use, to be had relative to the high etching of clearance wall 205
The material of ratio is selected, in the present embodiment, the material of sacrifice layer 206 is preferably comprised Spun-on carbon
(Spin-on Carbon, abbreviation SOC).
Spun-on carbon layer includes the polymer rich in carbon, in the polymer rich in carbon, carbon
Content preferably account for the 85wt% (percentage by weight) to 90wt% of polymer total molecular weight.
Spun-on carbon layer can be coated by means of simple spin coating method, the spun-on carbon layer have it is excellent between
Gap filling capacity.
Then, as shown in FIGURE 3 E, it is described sacrificial to perform the first etch-back step etching removal part
Domestic animal layer 206, the top surface of the remaining sacrifice layer 206 is set to be higher than the target material layer 200
Top surface be less than the clearance wall 205 top surface.
Further, when in the target material layer 200 formed with metal hard mask layer 201,
The top surface of the remaining sacrifice layer 206 is less than higher than the top surface of the metal hard mask layer 201
The top surface of the clearance wall 205.
Wherein, using based on O2、CO2、CO、N2、H2Or the plasma of its combination enters
Row the first etch-back step.
Exemplarily, also etched simultaneously when carrying out the first etch-back step and remove part core
Pattern 202, the top surface of the top surface of remaining sacrifice layer 206 and the core pattern 202 after etching
Flush.
Then, as illustrated in Figure 3 F, perform the etching of the second etch-back step and remove the part gap
Wall 205, make the top surface of the remaining clearance wall 205 higher than the target material layer 200
Top surface is less than the top surface of the remaining sacrifice layer 206.
The second etch-back step for clearance wall 205 is performed from dry etching, in this reality
Apply in example, use CxFyAs etchant dry plasma etch process realize to for
Second etch-back of clearance wall 205, the CxFyEtchant can be CF4、CHF3、C4F8
And C5F8In one or more.In the embodiment of the present invention, the dry method
Etching can select CF4、CHF3, in addition plus N2、CO2In it is a kind of as etching gas
Atmosphere, wherein gas flow are CF410-200sccm, CHF310-200sccm, N2Or CO2
Or O210-400sccm, the etching pressure are 30-150mTorr, etching period 5-120s,
Preferably 5-60s, more preferably 5-30s.
In one example, formed with metal hard mask layer in the target material layer 200
When 201, the top surface of the remaining clearance wall 205 is higher than the metal hard mask layer 201
Top surface is less than the top surface of the remaining sacrifice layer 206.
Further, circulation performs the first etch-back step and second etch-back successively
Step is several times.The actual frequency several times can need suitably be adjusted according to actual process
It is whole, in the present embodiment, it is preferred that circulation performs the first etch-back step and described successively
Second etch-back step is more than or equal to 2 times.
Exemplarily, as shown in Fig. 3 E to 3H, circulation successively performs first etch-back
Step and the second etch-back step 2 time.
Then, as shown in fig. 31, the remaining sacrifice layer and the remaining core figure are removed
Case, the surface of expose portion metal hard mask layer 201, to form spaced clearance wall
205。
Exemplarily, there can be identical spacing between adjacent segment wall 205.Between specific
Away from can be also adjusted according to the size of the pattern being located in target material layer of predetermined formation.
Exemplarily, the core pattern is bottom antireflective coating, and the sacrifice layer is Spun-on carbon,
It, which can be used, is based on O2、CO2、CO、N2、H2Or the plasma of its combination is lost
Carve and remove, can also use the method for other wet etchings well known to those skilled in the art to go
Remove.
Finally, it is mask with the remaining clearance wall 205, etches the target material layer
200, to form some grooves 207 being located in the target material layer 200.
Exemplarily, when in the target material layer 200 formed with metal hard mask layer 201,
Metal hard mask layer 201 and target material layer 200 are then etched successively, to form groove 207.
Any engraving method well known to those skilled in the art can be used to carry out the erosion in this step
Carve, such as dry etching or wet etching, dry method etch technology include but is not limited to：Reaction
Ion(ic) etching (RIE), ion beam milling, plasma etching or laser cutting.Afterwards,
It is selectively removed the metal hard mask layer 201.
Finally, after the first etch-back step and the second etch-back step so that clearance wall
205 height reduction, still can be using it to cover without influenceing its function as mask layer
Film carry out pattern transfer, and its height reduction it is possible to prevente effectively from clearance wall 205 collapses problem
Occur.
For the semiconductor devices of back end of line, also metal can be filled in the groove 207 of formation
Material, and carry out chemical mechanical milling tech and stop in target material layer 200, if to be formed
Dry metal wire (not shown), wherein, metal material can use any tool well known in the art
The metal such as conductive material, including but not limited to copper, aluminium.
So far retouching for the key step of the manufacture method of the semiconductor devices to the present invention is completed
State, the making for complete semiconductor devices it may also be desirable to other preamble techniques, centre
Technique or subsequent technique, will not be described here.
In summary, manufacturing method according to the invention, by circulate perform several times to sacrificial
First etch-back step of domestic animal layer and the second etch-back step to clearance wall, to reduce clearance wall
Height, avoid clearance wall and collapse the appearance of problem, and then make it that the pattern of clearance wall can essence
Target material layer really is transferred to, improves the yield and performance of device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modifications can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (12)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided, on the semiconductor substrate formed with target material layer；
The core by several mutually isolated strips of opening is formed in the target material layer
Pattern, and form clearance wall in the side wall of the core pattern；
The sacrifice layer for covering the clearance wall, the core pattern and the target material layer is formed,
The top surface of the sacrifice layer is higher than the top surface of the clearance wall；
Circulation performs the first etch-back step and the second etch-back step several times successively, wherein,
The first etch-back step etching removes the part sacrifice layer, makes remaining described sacrificial
The top surface of domestic animal layer is less than the top surface of the clearance wall higher than the top surface of the target material layer,
The etching of second etch-back step removes the part clearance wall, makes the remaining clearance wall
Top surface higher than the target material layer top surface be less than the remaining sacrifice layer top surface；
Remove the remaining sacrifice layer and the remaining core pattern；
Using the remaining clearance wall as mask, the target material layer is etched, is located at being formed
Some grooves in the target material layer.
2. manufacture method as claimed in claim 1, it is characterised in that described big several times
In equal to 2.
3. manufacture method as claimed in claim 1 or 2, it is characterised in that the sacrifice
Layer includes Spun-on carbon.
4. manufacture method as claimed in claim 1, it is characterised in that use and be based on O2、
CO2、CO、N2、H2Or the plasma of its combination carries out the first etch-back step.
5. manufacture method as claimed in claim 1, it is characterised in that use CxFyAs
The dry plasma etch process of etchant is realized to be walked to the second etch-back of the clearance wall
Suddenly.
6. manufacture method as claimed in claim 1, it is characterised in that forming the core
Before pattern, in addition on the surface of the target material layer formed metal hard mask layer step
Suddenly.
7. manufacture method as claimed in claim 1, it is characterised in that the core pattern is
Bottom antireflective coating.
8. manufacture method as claimed in claim 7, it is characterised in that form the core figure
The step of case and the clearance wall, includes：
Bottom antireflective coating and low temperature oxide layer are sequentially formed in the target material layer；
The core photoresist of several spaced strips is formed in the low temperature oxide layer
Layer；
Using the core photoresist layer as mask, the low temperature oxide layer and the bottom are etched successively
Portion's ARC, to be formed by several mutually isolated core patterns of opening, and remove institute
State core photoresist layer；
Shape is deposited on the surface of the core pattern and on the surface of target material layer exposure
Into spacer material layer；
The spacer material layer is etched, between being formed in each core pattern sidewalls
Gap wall.
9. manufacture method as claimed in claim 1, it is characterised in that the target material
Layer is interlayer dielectric layer.
10. manufacture method as claimed in claim 1, it is characterised in that the clearance wall
Material includes oxide, nitride or its combination.
11. manufacture method as claimed in claim 8, it is characterised in that use atomic layer deposition
Area method deposits to form the spacer material layer.
12. manufacture method as claimed in claim 1, it is characterised in that performing described the
Also etched simultaneously during one etch-back step and remove the part core pattern.
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| CN110854074A (en) * | 2019-11-27 | 2020-02-28 | 上海华力微电子有限公司 | Method for improving inclination of 2D-NAND side wall |
| CN112017950A (en) * | 2020-07-17 | 2020-12-01 | 中国科学院微电子研究所 | Multiple patterning method |
| CN112687700A (en) * | 2020-12-24 | 2021-04-20 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN113130751A (en) * | 2021-03-02 | 2021-07-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| CN115568216A (en) * | 2022-10-11 | 2023-01-03 | 芯盟科技有限公司 | Active region structure and formation method of vertical channel memory |
| WO2023077336A1 (en) * | 2021-11-04 | 2023-05-11 | Yangtze Memory Technologies Co., Ltd. | Three dimensional (3d) memory device and fabrication method using self-aligned multiple patterning and airgaps |
| WO2024148747A1 (en) * | 2023-01-11 | 2024-07-18 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
| US12198932B2 (en) | 2021-03-02 | 2025-01-14 | Changxin Memory Technologies, Inc. | Method of manufacturing semiconductor structure including spacer filler etch and stacked mandrel layers and semiconductor structure |
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| CN113130751A (en) * | 2021-03-02 | 2021-07-16 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and semiconductor structure |
| US12198932B2 (en) | 2021-03-02 | 2025-01-14 | Changxin Memory Technologies, Inc. | Method of manufacturing semiconductor structure including spacer filler etch and stacked mandrel layers and semiconductor structure |
| WO2023077336A1 (en) * | 2021-11-04 | 2023-05-11 | Yangtze Memory Technologies Co., Ltd. | Three dimensional (3d) memory device and fabrication method using self-aligned multiple patterning and airgaps |
| CN115568216A (en) * | 2022-10-11 | 2023-01-03 | 芯盟科技有限公司 | Active region structure and formation method of vertical channel memory |
| WO2024148747A1 (en) * | 2023-01-11 | 2024-07-18 | 长鑫存储技术有限公司 | Manufacturing method for semiconductor structure, and semiconductor structure |
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