CN107452810B - Metal oxide thin film transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a metal oxide thin film transistor and a preparation method thereof. The source electrode is arranged on the substrate, the metal oxide channel layer is arranged on the source electrode, the drain electrode is arranged on the metal oxide channel layer, the gate electrode and the gate dielectric layer are formed by in-situ oxidation, and the gate electrode is formed by in-situ oxidation. The gate dielectric layer is embedded in the gate dielectric layer, and the gate dielectric layer is embedded in the metal oxide channel layer; the metal oxide thin film transistor has no less than two gate dielectric layers, and the gate dielectric layer and the gate dielectric layer are They are separated from each other to form a multi-conductive channel with carriers from bottom to top. On the one hand, the metal oxide thin film transistor provided by the invention can break through the limitation of the size of the traditional process, and at the same time, due to the parallel action of multiple channels, it can realize high output current under low operating voltage.

Description

A kind of metal oxide thin film transistor and preparation method thereof

technical field

The invention relates to the technical field of thin film transistors (TFTs), in particular to a metal oxide thin film transistor and a preparation method thereof.

Background technique

As the core component of the flat panel display, the thin film transistor together with the storage capacitor forms the drive circuit, and plays an important role in realizing large-area, high-definition, and high-frame-rate display. Currently, amorphous silicon (a-Si) TFT is the most mature and widely used TFT, but its field-effect mobility is low (< 1 cm ² /Vs), making it difficult to drive active display devices, and a-Si is photostable Bad sex. Although polysilicon TFT devices have higher mobility and better stability, they have poor device uniformity, high fabrication costs, and are incompatible with conventional IC processes. Organic thin film transistors (OTFTs) also suffer from low mobility and poor stability.

In recent years, metal oxide TFTs represented by IZO and IGZO are gradually replacing traditional a- Si TFT has become the core component of a new generation of flat panel display devices. In 2004, Nomura et al. reported for the first time in the journal Nature that the TFT with amorphous indium gallium zinc oxide (a-IGZO) as the channel layer [ Nature , 2004, 432(7061): 488-492], the device saturation mobility ( μ ) is 6~9 cm ² /Vs.

However, with the rapid development of integrated circuits and the demand for higher and higher resolution of displays, the electrical properties of thin film transistors should be further improved, and the device size should be further reduced. For conventional lateral TFT devices, this is usually achieved by reducing the channel length. However, due to the limitation of processing technology, generally in the order of micrometers, further reducing the size will greatly increase the fabrication cost, and the short channel effect has become a huge obstacle to further reducing the traditional device.

Using a vertical structure TFT, the thickness of the channel layer sandwiched between the source-drain electrodes is the length of the channel layer, so it can break through the limitations of traditional processing technology, and in principle, the channel length can be reduced to submicron or even nanometers It can greatly improve the operating current, response speed, and switching ratio of the device, and can also reduce the turn-on voltage and power consumption of the device. Y. Yang et al. [ Appl. Phys. Lett. , 2007, 91:092911], [ Appl. Phys. Lett. , 2004, 85(21): 5084-5086 ] reported a vertically stacked organic transistor (VOFET) . However, the source electrode of the transistor is located between the dielectric layer and the channel layer, and the thickness of the source electrode and the interface between the source electrode and the channel layer will affect the collection and transmission of carriers. So far, there have been no reports of metal oxide TFTs based on vertical structures.

SUMMARY OF THE INVENTION

In order to solve the deficiencies of the prior art, the purpose of the present invention is to provide a metal oxide thin film transistor and a preparation method thereof, which on the one hand can break through the size limitation of traditional technology, and on the other hand can realize high output current under low operating voltage .

According to an aspect of the present invention, a metal oxide thin film transistor is provided. It includes a substrate, a source electrode, a metal oxide channel layer, a gate electrode, a gate dielectric layer, and a drain electrode; the source electrode is arranged on the substrate, the metal oxide channel layer is arranged on the source electrode, and the drain electrode is arranged on the metal On the oxide channel layer, the gate electrode and the gate dielectric layer are embedded in the metal oxide channel layer, and the gate electrode is embedded in the gate dielectric layer; the metal oxide thin film transistor has many In the two gate dielectric layers, and the gate dielectric layers are separated from each other, a multi-conductive channel with carriers from bottom to top is formed.

One of the metal oxide thin film transistors described therein is a vertical buried gate structure. The metal oxide channel layer is In ₂ O ₃ , IZO, IGZO, HIZO or IGO. The mass percentage of In ₂ O ₃ in the composition of the metal oxide channel layer is greater than 50%. The gate electrode is one of Al, Hf, Ti, Zr, Mg, Mn, Cr, Zn, or an alloy composed of them. The gate electrodes are no less than two metal electrodes separated from each other and formed by using a certain pattern mask. The gate dielectric layer is formed by in-situ oxidation of the gate electrode under conventional thermal annealing process conditions to form an oxide layer with a thickness of less than 10 nm. The gate dielectric layer may also be a double gate dielectric layer composed of an insulating layer deposited on the gate electrode and an oxide layer formed by in-situ oxidation. Said source electrode and drain electrode are ITO, high conductivity IZO, Mo, Cu or Ag.

According to another aspect of the present invention, a method for fabricating a metal oxide thin film transistor is provided, the method comprising: forming a source electrode on a substrate; forming a first metal oxide channel layer on the source electrode ; Use a certain pattern mask on the first metal oxide channel layer, and then deposit metal to form no less than 2 gate electrodes separated from each other; On the first metal oxide channel layer and Continue to grow the same metal oxide as the first metal oxide channel layer on the gate electrode to form a complete metal oxide channel layer, and embed the gate electrode in the middle of the metal oxide channel layer; A drain electrode is formed on the material channel layer; the entire structure is annealed in an atmosphere of 200°C for 10 hours, so that an in-situ oxidation reaction occurs between the gate electrode and the metal oxide channel layer, so that the growth thickness around the gate electrode is less than 10nm gate dielectric layer. The gate dielectric layer and the gate dielectric layer are separated from each other to form multiple conductive channels with carriers from bottom to top.

Compared with the prior art, the beneficial effects of the present invention are:

1. The present invention adopts a vertical buried gate structure, on the one hand, it can break through the limitation of the size of the traditional process, and on the other hand, it can avoid the collection and transmission of carriers by the source electrode of the VOFET structure. 2. The gate electrode and the gate dielectric layer of the present invention are formed by in-situ oxidation under conventional thermal annealing conditions, which can simplify the manufacturing process and save the manufacturing cost. 3. The present invention has a multi-channel structure. On the premise of not changing the length of the channel, due to the parallel action of the multi-channel, high output current under low operating voltage can be achieved.

Description of drawings

The present invention is further described below in conjunction with the accompanying drawings;

1 is a cross-sectional view of a metal oxide thin film transistor provided by the present invention;

2a to 2e are cross-sectional views of a method for manufacturing a metal oxide thin film transistor provided by the present invention;

3 is a cross-sectional view of a metal oxide thin film transistor with dual dielectric layers provided by the present invention;

Figure 4 is a pattern mask on the metal oxide channel layer prior to example gate electrode deposition;

5 is a top view of a metal oxide thin film transistor of an embodiment;

6 is a TEM cross-sectional view of an in-situ metal oxide layer of an embodiment;

7 is a C-V curve of an in-situ metal oxide layer of an embodiment;

FIG. 8 is an output characteristic curve of the metal oxide thin film transistor of the embodiment;

FIG. 9 is a transfer characteristic curve of the metal oxide thin film transistor of the embodiment.

Symbol Description:

1, substrate; 2, source electrode; 3, first metal oxide channel layer; 4, gate electrode; 5, gate dielectric layer; 6, second metal oxide channel layer; 7, drain electrode; 8, Carrier movement direction; 9. The second insulating layer.

Detailed ways

The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that, in order to highlight the gist of the present invention, well-known processes are not described in detail herein. At the same time, the drawings are in a very simplified form and are not drawn to exact scale. The purpose of the embodiments of the present invention is to give a full and complete disclosure of the present invention, and not to limit the embodiments.

A metal oxide thin film transistor

1 , from bottom to top, it includes a substrate 1 , a source electrode 2 , a first metal oxide channel layer 3 , a gate electrode 4 , a gate dielectric layer 5 , a second metal oxide channel layer 6 , and a drain electrode 7 . The material of the substrate 1 is, for example, glass, quartz, or silicon wafer. The material of the source electrode 2 is, for example, conductive ITO, high-conductivity IZO, Mo, Cu, or Ag metal. The material of the first metal oxide channel layer 3 is, for example, In ₂ O ₃ , IZO, IGZO, HIZO or IGO, wherein the mass percentage of In ₂ O ₃ in the metal oxide component is greater than 50%, and the carrier concentration n is 10 ¹⁵ ~10 ¹⁸ /cm ³ range. On the first metal oxide channel layer 3, a mask with a certain pattern is used to form not less than two gate electrodes 4 spaced apart from each other. The material of the gate electrodes 4 is, for example, Al, Hf, Ti, Zr, Mg, One of Mn, Cr, Zn or an alloy composed of them. The second metal oxide channel layer 6 is formed on the first metal oxide channel layer 3 and the gate electrode 4, and the gate electrode 4 is buried in the middle of the channel layer. The first metal oxide channel layer 3 and the second metal oxide channel layer 6 use the same process parameters, and the first metal oxide channel layer 3 and the second metal oxide channel layer 6 form a complete metal oxide channel layer. The material of the drain electrode 7 is, for example, conductive ITO, high-conductivity IZO, Mo, Cu, or Ag metal. The gate dielectric layer 5 is an in-situ oxide layer with a thickness of less than 10 nm formed by thermal annealing at 200° C. for 10 hours, such as Al ₂ O ₃ , HfO ₂ , TiO ₂ , ZrO ₂ , MgO, MnO, Cr ₂ O _3. ZnO or a combination thereof. The gate dielectric layer can also be a double gate dielectric layer, that is, a second insulating layer 9 such as SiO ₂ and Si ₃ N ₄ is deposited on the gate electrode 4 to form a double gate dielectric layer with the in-situ oxide layer, as shown in FIG. 3 . The gate dielectric layer 5 is separated from the gate dielectric layer 5 to form multiple conductive channels with carriers from bottom to top.

Example 1

Referring to FIG. 1 , the substrate 1 is a SiO ₂ /Si substrate with a thickness of 500 nm, and the source electrode 2 and the drain electrode 7 are highly conductive IZO films with a thickness of 100 nm, n~10 ²⁰ /cm ³ . The first metal oxide channel layer 3 and the second metal oxide channel layer 6 are semiconductor IZO films with a thickness of 100 nm, n~10 ¹⁷ /cm ³ . The mass percentage of In ₂ O ₃ in the highly conductive IZO film and the semiconducting IZO film is both 90%. The gate electrode 4 is Al metal with a thickness of 20 nm. The Al metal is formed on the first semiconductor IZO film using the mask of the pattern shown in Figure 4. The pattern consists of 10 strips with a width of 500 nm and a length of 10 μm. The distance between the strips is also 500nm. The gate dielectric layer 5 is an Al ₂ O ₃ oxide layer formed by in-situ oxidation of Al metal and semiconductor IZO thin film under thermal annealing at 200°C for 10 hours, so that the Al metal is embedded in the middle of the Al ₂ O ₃ oxide layer, and the Al ₂ O ₃ The oxide layer is embedded in the middle of the semiconductor IZO film. The Al ₂ O ₃ oxide layer and the Al ₂ O ₃ oxide layer are separated from each other to form a multi-conductive channel with carriers from bottom to top. FIG. 5 is a top view of the metal oxide thin film transistor of the embodiment, and the effective area of the device is 100 μm ² ; FIG. 6 is a TEM cross-sectional view of the Al ₂ O ₃ oxide layer of the embodiment; FIG. 7 is the CV curve of the Al ₂ O ₃ oxide layer of the embodiment. , wherein the capacitance C of the Al ₂ O ₃ oxide layer is 1.2 μF/cm ² , and the calculated dielectric constant is 6.85; Figure 8 is the output characteristic curve of the IZO thin film transistor of the embodiment, in which the drain electrode voltage V _D changes from 0V to 5V, the gate electrode voltage V _G changes from 0V to 4V, it can be seen from the figure that the IZO TFT of this embodiment has good saturation characteristics, and a high output current of 4.5mA can be obtained at a lower voltage of V _G =4V; Fig. 9 is the transfer characteristic curve of the IZO thin film transistor of the embodiment. It can also be seen from the figure that the IZO TFT of the embodiment has a higher output current, and the current switching ratio is also greater than 10 ⁶ .

A kind of preparation method of metal oxide thin film transistor

A method for preparing a metal oxide thin film transistor will be described below, and the device structure of the metal oxide thin film transistor will be more clear from the description of the preparation method below. 2a to 2e are cross-sectional views of a method for fabricating a metal oxide thin film transistor according to the present invention. First, the substrate 1 is provided. The material of the substrate 1 is, for example, glass, quartz, or silicon wafer, etc. The substrate is cleaned to obtain a good growth surface. Next, a source electrode 2 is formed on the substrate 1, and the material of the source electrode 2 is, for example, conductive ITO, high-conductivity IZO, Mo, Cu or Ag metal. A first metal oxide channel layer 3 is then formed on the formed source electrode 2 . The material of the first metal oxide channel layer 3 is, for example, In ₂ O ₃ , IZO, IGZO, HIZO or IGO, wherein the mass percentage of In ₂ O ₃ in the metal oxide component is greater than 50%, and the carrier concentration n is 10 ¹⁵ ~10 ¹⁸ /cm ³ range. The first metal oxide channel layer 3 can be obtained by using a magnetron sputtering method to control the oxygen partial pressure in the reaction process. Then, the first metal oxide channel layer 3 is patterned using a mask with a certain pattern, and the patterning method is, for example, electron beam lithography, photolithography lift-off or nanoimprinting. On the patterned first metal oxide channel layer 3, no less than two elongated gate electrodes 4 are formed and spaced apart from each other. The material of the gate electrodes 4 is, for example, Al, Hf, Ti, Zr, Mg, One of Mn, Cr, Zn or an alloy composed of them. Next, a second metal oxide channel layer 6 is continuously grown on the first metal oxide channel layer 3 and the gate electrode 4, and the gate electrode 4 is buried in the middle of the channel layer. The first metal oxide channel layer 3 and the second metal oxide channel layer 6 use the same process parameters, and the first metal oxide channel layer 3 and the second metal oxide channel layer 6 form a complete metal oxide channel layer. Next, a drain electrode 7 is formed on the complete metal oxide channel layer, and the material of the drain electrode 7 is, for example, conductive ITO, high-conductivity IZO, Mo, Cu or Ag metal. Finally, the structure shown in Figure 2e is thermally annealed in the atmosphere at 200°C for 10 hours, so that an oxidation reaction occurs between the gate electrode 4 and the metal oxide channel layer, so that an in-situ oxidation with a thickness of less than 10 nm is formed around the gate electrode 4 The gate dielectric layer 5 is, for example, Al ₂ O ₃ , HfO ₂ , TiO ₂ , ZrO ₂ , MgO, MnO, Cr ₂ O ₃ , ZnO or a combination thereof, as shown in FIG. 1 . In the present invention, a second insulating layer 9 such as SiO ₂ and Si ₃ N ₄ can also be deposited on the gate electrode 4 to form a double gate dielectric layer with the in-situ oxide layer. As shown in FIG. 3 , the double dielectric layer can adjust the dielectric constant and reduce leakage current. The formed gate dielectric layer 5 is separated from the gate dielectric layer 5 to form multiple conductive channels with carriers from bottom to top.

Example 2

2a to 2e, the present invention provides a method for preparing an IZO thin film transistor. A SiO ₂ /Si substrate with a thickness of 500 nm is grown on the substrate 1 after ultrasonic cleaning with acetone, ethanol, deionized water, etc., and nitrogen drying. Next, a highly conductive IZO (n~10 ²⁰ /cm ³ ) with a thickness of 100 nm is formed on the substrate by DC magnetron sputtering as the source electrode 2 , the sputtering power density is 0.88W/cm ² , the voltage is 400V, and the working gas is for pure argon. Then, a first semiconductor IZO thin film (n~10 ¹⁷ /cm ³ ) with a thickness of 100 nm is deposited on the formed source electrode 2 as the first metal oxide channel layer 3, and the sputtering power density is 0.22W/cm ² . The voltage is 280V, the pressure is 0.266Pa, and the oxygen partial pressure O ₂ /Ar+O ₂ is 14%. The pattern as shown in Figure 4 is formed on the first semiconductor IZO film by electron beam lithography. The pattern consists of 10 strips, the width of the strips is 500 nm, the length is 10 μm, and the distance between the strips is also 500nm. Next, the gate electrode 4 is formed by depositing Al metal with a thickness of 20 nm on the patterned first semiconductor IZO film by DC magnetron sputtering. The sputtering power is 0.22 W/cm ² , the voltage is 400 V, and the working gas is pure argon. Next, a second semiconductor IZO film with a thickness of 100 nm is deposited on the first semiconductor IZO film and the Al metal using the same process parameters as the first semiconductor IZO film. The first semiconductor IZO film and the second semiconductor IZO film form a complete IZO channel layer. The Al metal is embedded in the middle. Next, a 100nm-thick highly conductive IZO (n~10 ²⁰ /cm ³ ) is formed on the complete IZO channel layer as the drain electrode 7 , and the process parameters of the drain electrode 7 and the source electrode 2 are exactly the same. Finally, the whole structure was thermally annealed at 200 °C for 10 hours in the atmosphere, so that Al+In ₂ O ₃ =Al ₂ O ₃ +In occurred between the Al metal and the IZO channel layer, Δ G = –752.6 KJ/mol ( T =200 °C) oxidation reaction, thereby forming an in-situ Al ₂ O ₃ oxide layer with a thickness of less than 5 nm around the Al metal as the gate dielectric layer 5 . The Al ₂ O ₃ oxide layer and the Al ₂ O ₃ oxide layer are separated from each other to form 10 conductive channels for carriers from bottom to top.

The above are only preferred embodiments and are not intended to limit the present invention. The protection scope of the present invention is based on the claims of the present invention. Any simple modifications and equivalent changes made to the above embodiments according to the technical essence of the present invention fall within the protection scope of the present invention.

Claims (6)

1. A metal oxide thin film transistor comprises a substrate, a source electrode, a metal oxide channel layer, a gate electrode, a gate dielectric layer and a drain electrode; the method is characterized in that: the source electrode is arranged on the substrate, the metal oxide channel layer is arranged on the source electrode, the drain electrode is arranged on the metal oxide channel layer, the gate electrode and the gate dielectric layer are embedded in the metal oxide channel layer, and the gate electrode is embedded in the gate dielectric layer; the metal oxide thin film transistor is provided with not less than 2 gate dielectric layers, and the gate dielectric layers are mutually separated to form a multi-conductive channel with carriers from bottom to top;

the gate dielectric layer is a double gate dielectric layer, and the double gate dielectric layer consists of an insulating layer deposited above a gate electrode and an oxide layer formed by in-situ oxidation; the oxide layer formed by in-situ oxidation is positioned between the gate electrode and the metal oxide channel layer; the in-situ oxidation is an oxidation reaction occurring between the materials of the gate electrode and the metal oxide channel layer; the thickness of an oxide layer formed by in-situ oxidation of the gate electrode is less than 10 nm;

the metal oxide channel layerIs indium oxide In₂O₃Indium zinc oxide IZO, indium gallium zinc oxide IGZO, indium hafnium zinc oxide HIZO, or indium gallium oxide IGO.

2. The metal oxide thin film transistor of claim 1, wherein In is In said metal oxide channel layer composition₂O₃Is more than 50 percent.

3. The metal oxide thin film transistor of claim 1, wherein the gate electrode is one of Al, Hf, Ti, Zr, Mg, Mn, Cr, Zn or an alloy thereof.

4. A metal oxide thin film transistor according to claim 1, wherein the gate electrode is not less than 2 metal electrodes spaced apart from each other formed using a patterned mask.

5. The metal oxide thin film transistor of claim 1, wherein the source and drain electrodes are Indium Tin Oxide (ITO), high conductivity IZO, Mo, Cu, or Ag.

6. A method for preparing a metal oxide thin film transistor, the method comprising: forming a source electrode on a substrate; forming a first metal oxide channel layer on the source electrode; using a certain pattern mask on the first metal oxide channel layer, and then depositing metal to form not less than 2 gate electrodes which are mutually separated; depositing an insulating layer on the gate electrode; continuously growing the same metal oxide as the first metal oxide channel layer on the first metal oxide channel layer, the gate electrode and the insulating layer to form a complete metal oxide channel layer, and embedding the gate electrode in the middle of the metal oxide channel layer; forming a drain electrode on the metal oxide channel layer; the whole structure is annealed for 10 hours at 200 ℃ in an atmospheric environment, so that in-situ oxidation reaction is generated between the gate electrode and the metal oxide channel layer, a gate dielectric layer with the thickness of less than 10nm grows around the gate electrode, and the gate dielectric layer are mutually separated to form a multi-conductive channel with current carriers from bottom to top.

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