CN107403800A - 具有叉指状背对背mosfet的器件结构 - Google Patents
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Abstract
一个双向开关器件,包括两个叉指状背对背垂直金属氧化物半导体场效应晶体管(MOSFET),形成在衬底上,它们的漏极连接在一起,但相互隔离。
Description
技术领域
本发明主要涉及集成电路,更确切地说是具有背对背金属氧化物半导体场效应晶体管(MOSFET)的集成电路器件。
背景技术
金属氧化物半导体场效应晶体管(MOSFET)是一种半导体晶体管器件,其中电绝缘栅极所加电压控制源极和漏极之间的电流。MOSFET应用于多种功率开关器件。在一种电池保护电路模块(PCM)所使用的具体结构中,两个MOSFET呈背对背结构,它们的漏极以浮动结构连接在一起。图1A表示这种结构的示意图。图1B表示这种器件100与电池保护电路模块PCM 102、电池104和一个负载或充电器106结合使用。在本例中,充电和放电MOSFET 120和130的栅极,分别由控制器集成电路(IC)110单独驱动。这种结构允许在两个方向上控制电流:充电器到电池以及电池到负载。在正常充电和放电操作下,MOSFET 120和130都接通(即导电)。在电池104的过充电或充电过电流状态下,控制器IC 110断开充电MOSFET 120,接通放电MOSFET 130。在过放电或放电过电流状态下,控制器IC 110接通充电MOSFET 120,断开放电MOSFET 130。
发明内容
本发明的目的在于提供一个具有叉指状背对背MOSFET的器件结构,包括两个叉指状背对背垂直金属氧化物半导体场效应晶体管(MOSFET),形成在衬底上,它们的漏极连接在一起,但相互隔离。通过将MOSFET分成窄的叉指状组件,器件结构实现了邻近隔离垂直MOSFET之间紧凑的水平间距,它们的漏极连接在一起,并实现电浮动。
为了达到上述目的,本发明通过以下技术方案实现:
一种双向半导体开关器件,其特征是,包括:
一个半导体衬底;
两个叉指状背对背垂直金属氧化物半导体场效应晶体管(MOSFET)形成在衬底上,它们的漏极连接在一起,但是源极和栅极相互隔离。
上述的器件,其中两个叉指状背对背垂直MOSFET包括一个具有多个组件的第一垂直MOSFET,以及一个具有一个或多个组件的第二垂直MOSFET,其中第二垂直MOSFET的一个或多个组件包括沉积在第一垂直MOSFET多个组件中两个组件之间的一个组件。
上述的器件,其中第一垂直MOSFET多个组件的间距在10微米至100微米之间。
上述的器件,其中半导体衬底的厚度大于75微米。
上述的器件,其中半导体衬底的厚度为3mil至6mil。
上述的器件,其中第一和第二MOSFET中多个组件中每个组件的宽度为500微米至5毫米。
上述的器件,其中第一和第二MOSFET中多个组件中有源晶胞的数量为10至200。
上述的器件,其中选择多个组件的间距,使两个叉指状背对背MOSFET之间的源极至源极电流通路,以两个MOSFET的漂流区中的横向电流为主。
上述的器件,其中,还包括一个形成在衬底上的电隔离金属层,其中两个叉指状背对背MOSFET的栅极和源极区电连接到金属层相应的隔离部分。
上述的器件,其中,还包括一个形成在衬底上的电隔离金属层,其中两个叉指状背对背MOSFET的源极区电连接到金属层相应的隔离且交叉的指状部分。
上述的器件,其中两个叉指状背对背MOSFET的栅极区电连接到金属层相应的隔离栅极垫部分。
上述的器件,其中,还包括一个形成在衬底上的第一电隔离金属层,以及一个形成在一层绝缘材料上的第二电隔离金属层,绝缘材料夹在第一金属层和第二金属层之间,其中两个叉指状背对背MOSFET的源极区电连接到第一金属层相应的隔离且交叉的指状部分上,第一金属层相应的隔离且交叉的指状部分,通过形成在第一金属层和第二金属层之间的隔离材料层中的导电通孔电连接到第二金属层相应的电隔离部分上。
上述的器件,其中两个叉指状背对背MOSFET的栅极区电连接到第一金属层相应的隔离栅极部分,第一金属层相应的隔离栅极部分,通过形成在第一金属层和第二金属层之间的隔离材料层中的导电通孔电连接到第二金属层相应的电隔离栅极垫部分。
上述的器件,其中,还包括一个端接结构,形成在第一和第二叉指状背对背MOSFET之间。
上述的器件,其中端接结构包括一个或多个沟槽,内衬绝缘物材料,并用导电材料填充。
上述的器件,其中端接结构包括一个单独的沟槽,内衬绝缘物材料,并用导电材料填充。
上述的器件,其中端接结构包括一个用绝缘物材料填充的单独沟槽。
上述的器件,其中,还包括一个通道终点,形成在第一和第二叉指状MOSFET周围。
上述的器件,其中衬底的背部没有金属层形成在上面。
一种双向开关器件,其特征是,包括:
一个半导体衬底;
一个第一垂直金属氧化物半导体场效应晶体管(MOSFET),形成在衬底上,第一垂直金属氧化物半导体场效应晶体管具有一个第一源极区,第一源极区位于衬底的第一个顶部,第一漏极位于衬底的第一个底部,第一源极金属电连接到第一源极区;
一个第二垂直MOSFET形成在衬底上,第二垂直金属氧化物半导体场效应晶体管包括一个第二源极区、一个位于衬底第二个顶部上的第二栅极区以及一个位于衬底第二个底部上的第二漏极,第二源极金属电连接到第二源极区;以及
一个隔离结构,包括在第一和第二MOSFET之间的至少一个沟槽,其中第一和第二漏极相互电连接起来,第一源极和第一栅极分别与第二源极和第二栅极电隔离,从而构成两个背对背MOSFET。
上述的器件,其中两个背对背MOSFET之间的源极至源极电流通路,以两个MOSFET的漂流区中的横向电流为主。
上述的器件,其中两个MOSFET之间的距离为5微米或更小。
本发明与现有技术相比具有以下优点:通过将MOSFET分成窄的叉指状组件,器件结构实现了邻近隔离垂直MOSFET之间紧凑的水平间距,它们的漏极连接在一起,并实现电浮动。
附图说明
图1A表示具有两个背对背MOSFET的传统开关电路的示意图。
图1B表示传统的电池保护电路模块(PCM)的示意图。
图2A表示具有两个背对背呈MOSFET并排结构的传统开关器件的平面示意图。
图2B表示图2A所示的传统开关电路沿图2A中的A-A’线的剖面示意图。
图3表示依据本发明的一个方面,具有两个叉指状背对背MOSFET开关器件的剖面示意图。
图3B表示依据本发明的一个方面,图3所示的开关器件沿图3中的A-A’线的剖面示意图。
图3C表示依据本发明的一个方面,具有两个叉指状背对背MOSFET的一种可选开关器件的剖面示意图。
图3D表示依据本发明的一个方面,具有两个叉指状背对背MOSFET的另一种可选开关器件的剖面示意图。
图4A表示依据本发明的一个方面,具有一个金属层的两个叉指状背对背MOSFET的一种开关器件的平面示意图。
图4B-4C表示依据本发明的一个方面,具有两个金属层的两个叉指状背对背MOSFET的一种开关器件的平面示意图。
具体实施方式
以下结合附图,通过详细说明一个较佳的具体实施例,对本发明做进一步阐述。
引言
图2A表示具有两个完全隔离的垂直MOSFET 220和230的器件200的传统结构,对于每个MOSFET都有单独的端子和通道终点。MOSFET 1和MOSFET 2之间要求存在相当大的死区空间,以提供单独的端接区和通道终点,确保集成在同一个半导体衬底上的两个MOSFET完全隔离。隔离和通道终点占用很大的芯片面积,很难实现紧密的叉指状结构,以提高总的源极至源极导通电阻RSS。
图2B表示图2A所示的器件200的剖面图。每个垂直MOSFET 220/230包括多个有源器件晶胞,形成在轻掺杂的外延层246中,轻掺杂外延层246生长在较重掺杂的衬底244上。在本例中,重掺杂(例如N+)衬底244用作漏极,通过形成在衬底244背面的背部金属242,两个MOSFET 220和230的漏极电连接。有源器件形成在具有相同 导电类型(例如N-型)次掺杂的外延漂流层246中,外延漂流层246生长在衬底244的正面。本体区250的导电类型与衬底244和外延区246(例如P-型)的导电类型相反,本体区250形成在一部分外延层246中。栅极沟槽252形成在外延层246中,然后内衬绝缘物254(例如氧化层)。电绝缘栅极电极256(例如由多晶硅制成)沉积在沟槽252中。导电类型与衬底244相同的重掺杂(例如N+)源极区260,形成在沟槽252附近。通过源极金属层265和垂直源极接头267,形成到源极区的外部电接头。利用与栅极电极类似的绝缘电极,通过外延区中的源极-型导电区,短接至外延漂流区,形成通道终点280、282。端接区还包括由本体-型导电区制成的保护环284、286。
该器件的重要指标在于两个MOSFET 220和230都接通时的源极对源极电阻。必须使该电阻尽可能地小。总的源极对源极电阻Rss如下:
其中Rch为当栅极接通时,通过源极265和本体区250的导电通道电阻,Rdrift为外延层246的电阻,Rbackmetal为背部金属242的电阻,以及Rsubstrate为衬底244的电阻。如果MOSFET220和230之间的间距足够大,那么从MOSFET 220的源极金属到MOSFET 230的电流通路,基本垂直穿过通道252、漂流区246以及衬底244,水平穿过背部金属242。为了降低Rss,必须使衬底244很薄,使背部金属242很厚。在正面制成器件之后,通常将衬底244尽可能地磨薄,以减小衬底244的厚度。为了减小Rsubstrate和Rdrift,衬底244不能超过2mil(大约50微米)厚,为了减小Rbackmetal,背部金属至少8微米厚。鉴于衬底244的厚度,图2A和图2B所示的器件200非常脆弱,易于损坏。为了增加机械强度,通常采用至少2mil的保护带或塑封材料。即使带有这些保护,可用器件的产量也十分有限。
另一个问题是,如图2B所示,图2A-2B所示类型的传统器件在两个MOSFET的周围使用通道终点280/282。通道终点280/282占据了有源器件晶胞不应使用的额外空间。对于12-30伏的低压器件,两个MOSFET器件220,230的有源区的间隔应大于5微米,通常为10微米或更大。这样减小了通道区的面积,增大了Rss。
叉指状MOSFET,以减小Rss
本发明的各个方面利用图1A和图1B所示电路的特殊属性。对于图1A和图1B所用的双向开关来说,漏极是浮动的。没有漏极端接让电流流向器件,或从器件到漏极。基于上述原因,可以优化Rss,减小两个MOSFET之间的水平间距,使大部分电流在它们之间流动,水平穿过漂流区。如果电流必须从器件外部流经漏极的话,那么减小水平间距并没有任何好处。在如图2A所示的双向开关器件中,减小MOSFET之间的水平间距,同时保持器件的特性,是有些问题的,因为这必须要求在一个非常长并且很窄的芯片上制备器件。对于大多数有效的应用来说,这种制备参数是不现实的。
依据本发明的各个方面,通过将MOSFET分成窄的叉指状组件,器件结构实现了邻近隔离垂直MOSFET之间紧凑的水平间距,它们的漏极连接在一起,并实现电浮动。叉指状的MOSFET减小了间距,同时允许在传统尺寸的芯片上制备器件。叉指状本来并不是为垂直MOSFET制备,而是为水平MOSFET制备的。然而,水平MOSFET的源极-漏极电阻(Rds-on)高于垂直MOSFET,因此人们不会将水平MOSFET用于背对背结构,就像图1A所示的那样。
图3表示依据本发明的一个方面,具有两个叉指状背对背MOSFET的开关器件300的一个示例。在所示示例中,第一和第二MOSFET 320和330分别由叉指状隔离组件制成,各隔离组件相互隔开一个很短的距离。如果组件之间的间隔足够小的话,那么大多数的电流会通过漂流区,流过这个很短的水平距离,而不是很长的垂直距离。作为示例,但不作为局限,漂流区(例如对应外延层246)约为0.5微米至5微米厚。此外,将组件之间的间距做得非常小,可以消除通过衬底和背部金属的垂直电流。大部分电流水平穿过漂流区,可以使流经衬底的垂直电流和流经背部金属的水平电流可以忽略不计。因此,无需背部研磨衬底,或者将背部金属做得过厚。利用图3、3B所示的叉指状双向开关设计,衬底244可以3至6mil(约为75至150微米)厚,并且几乎没有背部金属242。取消背部研磨和背部金属,避免了过多的处理,改善了芯片的稳定性,从而提高了产量,降低了成本。
在图3、图3B所示的示例中,制备MOSFET 320、330的芯片为矩形。在可选实施例中,芯片可以是其他任意合适的形状。对于矩形芯片来说,最长边的尺寸范围为500微米至5毫米左右,纵横比(长度与宽度之比)的范围为1至3。
实际情况是,叉指状组件连接到电隔离源极金属区,源极金属区也是叉指状。例如通过一次刻蚀过程,例如通过对金属层形成图案,制成两个源极金属区。利用两个MOSFET320、330之间的新型隔离设计,如图3B-3D所示,可以轻松实现两个MOSFET 320、330之间的间距为5微米或更小,对于两个源极金属区来说,这也是由金属至金属间距所决定的。形成金属层图案的刻蚀过程,限制了金属至金属间距。例如,现有的金属刻蚀过程,将金属至金属间距限制到1微米以下。
每个组件可以容纳的有源器件晶胞的数量,取决于组件间距、每个组件内晶胞的间距以及第一和第二MOSFET的组件之间金属间的间距。金属间的间距范围约为1微米至5微米。组件间距范围为10微米至100微米。作为示例,但不作为局限,对于25微米的组件间距和5微米的金属间间距来说,组件宽度为22.5微米(μm)。对于1微米的晶胞间距来说,每个组件中大约可容纳22个晶胞。组件的数量取决于制备双向开关的芯片长度。晶胞间距范围为0.5微米至2微米。
本发明的各个方面还可以消除通道终点沟槽和接头,以及图2B所示的MOSFET220/230之间的多个保护环。在这些结构的空间中,叉指状结构可以利用邻近MOSFET组件之间的浅沟槽隔离物和端接310。通道终点380仅用于芯片边缘处的隔离。
图3B表示一个示例,其中消除了图2B所示的保护环284/286,两个MOSFET 320和330被较深的沟槽390/392隔开,沟槽390/392消除在外延层246中,内衬相对较厚的绝缘物394(例如氧化物),并用导电材料396(例如多晶硅)填充。绝缘物394比内衬栅极沟槽352的绝缘物354更厚。在MOSFET 1 320周围,绝缘沟槽392中的导电材料396与有源栅极沟槽中的栅极电极电隔离。在一个实施例中, MOSFET 1 320周围的隔离沟槽392中导电材料396,连接到MOSFET 1的源极金属360。与之类似,MOSFET 2 330周围的隔离沟槽390中的导电材料与有源栅极沟槽中栅极电极电隔离。在一个实施例中, MOSFET 2 330周围隔离沟槽390中导电材料396,连接到MOSFET 2的源极金属362。对于12-30V的器件,隔离沟槽390/392的深度约为0.5至2微米。虽然本体掺杂区可以触及隔离沟槽390/392的外部侧壁,但是没有源极区位于隔离沟槽390/392附近。如同有源器件边缘处测得的那样,两个MOSFET 320/330之间的间距可以减小到5微米或更小。
在图3C中的一个可选实施例中,MOSFET 1 320’和MOSFET 2 330’被单独的隔离沟槽390’隔开,隔离沟槽390’内衬绝缘材料,绝缘材料使电浮动的导电材料396隔离。在所述的示例中,沟槽390’内衬相对较厚的绝缘物394,并用多晶硅等导电材料396填充。两个MOSFET 320’/330’之间的间隔可以减小至5微米以下。在图3D所述的另一个可选实施例中,MOSFET 1 320”和MOSFET 2 330”被单独的浅沟槽398隔开,浅沟槽398用氧化物等绝缘物399填充。这种结构完全省去了多晶硅,取而代之使用氧化物填充沟槽。两个MOSFET 320’/330’之间的间隔可以减小至5微米以下。图3D所示结构的制备工艺需要一个额外的步骤,就是用绝缘物399填充单独的浅沟槽398。
图4A表示一种具有两个叉指状MOSFET的双向开关器件400的布局示意图,该叉指状MOSFET利用一个单独的金属层,提供到两个MOSFET 420和430源极的单独的电接头,两个MOSFET 420和430源极由本发明所述的紧凑隔离物450隔开。单独的金属层被分成两个独立部分432和433,分别覆盖两个MOSFET 420和430的叉指状组件,以及一个或多个栅极垫436和438。接触开口在金属部分和相应组件的有源晶胞之间提供垂直电接触。额外的接触开口将栅极垫436和438垂直连接到栅极滑道442和444,栅极滑道442和444分别位于源极金属432和433下方的隔离物内衬的栅极滑道沟槽中。栅极滑道442和444分别连接到有源晶胞的栅极电极上,栅极电极在有源晶胞栅极沟槽中,栅极沟槽分别平行延伸于两个MOSFET 420和430的有源区中。
图4A所示的单独的金属层结构可以导致一个相当的器件芯片区域,不能用于有源晶胞。为了更高效地利用有源晶胞的可用芯片面积,可以使用两个金属层。图4B-4C表示具有这种两个金属层结构的双向开关布局的示例。图4B表示开关的平面布局,用于表示第一个金属层结构,以及第一和第二MOSFET 520和530的特定特征,例如栅极滑道542和544分别连接到栅极沟槽中每个绝缘栅极电极上,栅极沟槽平行位于每个第一和第二MOSFET 520和530区域中,芯片501边缘的一个通道终点580,其中开关500就制备在芯片501上。第一金属层分成隔离部分560和562,隔离部分560和562位于含有第一和第二MOSFET 520和530的有源晶胞的叉指状组件上。这些隔离部分560和562中的每个金属组件都分别连接到相应的源极区,通过导电插头,例如如图所示和如上所述的方式。第一金属层还分成额外的隔离栅极滑道金属部分552和554,金属部分552和554分别位于第一和第二MOSFET 520和530的栅极滑道542和544上方。第一金属层的另一个部分在通道终点580上方。
图4C表示图4B上方第二金属层的平面。第一和第二金属层通过夹在它们之间的一层电介质材料(图中没有表示出),相互隔离。第二金属层分成四个隔离部分(611、613、615和615’),允许外部接头,用于第一和第二MOSFET 520和530的栅极和源极。这些部分中的每个部分都连接到第一金属层的相应部分,通过形成在电介质层中的导电通孔。两个栅极垫615和615’也类似地连接到相应的由第一金属层形成的栅极垫或栅极滑道金属部分,通过形成在电介质层中的导电通孔。焊锡球形成在第二金属层的各自隔离部分中,用于倒装芯片,连接到电路板上。双金属结构使得栅极垫和源极金属区更加紧凑,从而更加高效地利用有源器件晶胞上的芯片可用面积。
本发明的各个方面用于紧凑、高效的双向开关设计,无需背部研磨或背部金属就能制备。
尽管以上是本发明的较佳实施例的完整说明,但是也有可能使用各种可选、修正和等效方案。因此,本发明的范围不应局限于以上说明,而应由所附的权利要求书及其全部等效内容决定。任何可选件(无论首选与否),都可与其他任何可选件(无论首选与否)组合。在以下权利要求中,除非特别声明,否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非在指定的权利要求中用“意思是”特别指出,否则所附的权利要求书应认为是包括意义及功能的限制。
Claims (22)
1.一种双向半导体开关器件,其特征在于,包括:
一个半导体衬底;
两个叉指状背对背垂直金属氧化物半导体场效应晶体管(MOSFET)形成在衬底上,它们的漏极连接在一起,但是源极和栅极相互隔离。
2.如权利要求1所述的器件,其特征在于,其中两个叉指状背对背垂直MOSFET包括一个具有多个组件的第一垂直MOSFET,以及一个具有一个或多个组件的第二垂直MOSFET,其中第二垂直MOSFET的一个或多个组件包括沉积在第一垂直MOSFET多个组件中两个组件之间的一个组件。
3.如权利要求2所述的器件,其特征在于,其中第一垂直MOSFET多个组件的间距在10微米至100微米之间。
4.如权利要求2所述的器件,其特征在于,其中半导体衬底的厚度大于75微米。
5.如权利要求2所述的器件,其特征在于,其中半导体衬底的厚度为3mil至6mil。
6.如权利要求2所述的器件,其特征在于,其中第一和第二MOSFET中多个组件中每个组件的宽度为500微米至5毫米。
7.如权利要求2所述的器件,其特征在于,其中第一和第二MOSFET中多个组件中有源晶胞的数量为10至200。
8.如权利要求1所述的器件,其特征在于,其中选择多个组件的间距,使两个叉指状背对背MOSFET之间的源极至源极电流通路,以两个MOSFET的漂流区中的横向电流为主。
9.如权利要求1所述的器件,其特征在于,还包括一个形成在衬底上的电隔离金属层,其中两个叉指状背对背MOSFET的栅极和源极区电连接到金属层相应的隔离部分。
10.如权利要求1所述的器件,其特征在于,还包括一个形成在衬底上的电隔离金属层,其中两个叉指状背对背MOSFET的源极区电连接到金属层相应的隔离且交叉的指状部分。
11.如权利要求10所述的器件,其特征在于,其中两个叉指状背对背MOSFET的栅极区电连接到金属层相应的隔离栅极垫部分。
12.如权利要求1所述的器件,其特征在于,还包括一个形成在衬底上的第一电隔离金属层,以及一个形成在一层绝缘材料上的第二电隔离金属层,绝缘材料夹在第一金属层和第二金属层之间,其中两个叉指状背对背MOSFET的源极区电连接到第一金属层相应的隔离且交叉的指状部分上,第一金属层相应的隔离且交叉的指状部分,通过形成在第一金属层和第二金属层之间的隔离材料层中的导电通孔电连接到第二金属层相应的电隔离部分上。
13.如权利要求12所述的器件,其特征在于,其中两个叉指状背对背MOSFET的栅极区电连接到第一金属层相应的隔离栅极部分,第一金属层相应的隔离栅极部分,通过形成在第一金属层和第二金属层之间的隔离材料层中的导电通孔电连接到第二金属层相应的电隔离栅极垫部分。
14.如权利要求1所述的器件,其特征在于,还包括一个端接结构,形成在第一和第二叉指状背对背MOSFET之间。
15.如权利要求14所述的器件,其特征在于,其中端接结构包括一个或多个沟槽,内衬绝缘物材料,并用导电材料填充。
16.如权利要求14所述的器件,其特征在于,其中端接结构包括一个单独的沟槽,内衬绝缘物材料,并用导电材料填充。
17.如权利要求14所述的器件,其特征在于,其中端接结构包括一个用绝缘物材料填充的单独沟槽。
18.如权利要求1所述的器件,其特征在于,还包括一个通道终点,形成在第一和第二叉指状MOSFET周围。
19.如权利要求1所述的器件,其特征在于,其中衬底的背部没有金属层形成在上面。
20.一种双向开关器件,其特征在于,包括:
一个半导体衬底;
一个第一垂直金属氧化物半导体场效应晶体管(MOSFET),形成在衬底上,第一垂直金属氧化物半导体场效应晶体管具有一个第一源极区,第一源极区位于衬底的第一个顶部,第一漏极位于衬底的第一个底部,第一源极金属电连接到第一源极区;
一个第二垂直MOSFET形成在衬底上,第二垂直金属氧化物半导体场效应晶体管包括一个第二源极区、一个位于衬底第二个顶部上的第二栅极区以及一个位于衬底第二个底部上的第二漏极,第二源极金属电连接到第二源极区;以及
一个隔离结构,包括在第一和第二MOSFET之间的至少一个沟槽,其中第一和第二漏极相互电连接起来,第一源极和第一栅极分别与第二源极和第二栅极电隔离,从而构成两个背对背MOSFET。
21.如权利要求20所述的器件,其特征在于,其中两个背对背MOSFET之间的源极至源极电流通路,以两个MOSFET的漂流区中的横向电流为主。
22.如权利要求20所述的器件,其特征在于,其中两个MOSFET之间的距离为5微米或更小。
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| US15/161,054 US10388781B2 (en) | 2016-05-20 | 2016-05-20 | Device structure having inter-digitated back to back MOSFETs |
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| CN107403800A true CN107403800A (zh) | 2017-11-28 |
| CN107403800B CN107403800B (zh) | 2020-10-20 |
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| US9425304B2 (en) | 2014-08-21 | 2016-08-23 | Vishay-Siliconix | Transistor structure with improved unclamped inductive switching immunity |
| US9171949B1 (en) | 2014-09-24 | 2015-10-27 | Alpha And Omega Semiconductor Incorporated | Semiconductor device including superjunction structure formed using angled implant process |
| US9281368B1 (en) | 2014-12-12 | 2016-03-08 | Alpha And Omega Semiconductor Incorporated | Split-gate trench power MOSFET with protected shield oxide |
| US9312381B1 (en) | 2015-06-23 | 2016-04-12 | Alpha And Omega Semiconductor Incorporated | Lateral super-junction MOSFET device and termination structure |
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- 2016-05-20 US US15/161,054 patent/US10388781B2/en active Active
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- 2017-05-10 TW TW106115514A patent/TW201807806A/zh unknown
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109216440A (zh) * | 2018-09-17 | 2019-01-15 | 电子科技大学 | 具有双向电平传输的凹槽型漏极结构的mosfet器件 |
| CN109244135A (zh) * | 2018-09-17 | 2019-01-18 | 电子科技大学 | 基于Trench工艺的超结型双向阻断MOS器件及制备方法 |
| CN109244135B (zh) * | 2018-09-17 | 2021-03-30 | 电子科技大学 | 基于沟槽工艺的超结型双向阻断mos器件及制备方法 |
| CN109216440B (zh) * | 2018-09-17 | 2021-08-17 | 电子科技大学 | 具有双向电平传输的凹槽型漏极结构的mosfet器件 |
| CN115088081A (zh) * | 2020-12-29 | 2022-09-20 | 伏达半导体(合肥)有限公司 | 感应超结晶体管 |
| CN115088081B (zh) * | 2020-12-29 | 2025-01-28 | 伏达半导体(合肥)股份有限公司 | 感应超结晶体管 |
| WO2023123363A1 (en) * | 2021-12-31 | 2023-07-06 | Innoscience (suzhou) Semiconductor Co., Ltd. | Nitride-based bidirectional switching device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201807806A (zh) | 2018-03-01 |
| US20170338337A1 (en) | 2017-11-23 |
| US10388781B2 (en) | 2019-08-20 |
| CN107403800B (zh) | 2020-10-20 |
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