CN107346803A - The manufacture method of silicon substrate backboard light-emitting diode display - Google Patents

Abstract

The invention provides a method for manufacturing an LED display with a silicon-based backplane, comprising the steps of: providing a silicon-based backplane; forming a substrate optical alignment mark on the silicon-based backplane; providing a first mask; The first mask plate optical alignment mark is formed on the mask plate, and a plurality of first through holes form a first through hole array; the first mask plate is temporarily bonded to the silicon-based backplane; from the first mask plate Depositing the first LED emission layer on the upper surface of the upper surface through the first through hole in the first sub-pixel region array formed by the plurality of first sub-pixel regions exposed on the upper surface of the silicon substrate backplane; releasing the first mask The lower surface of the board is temporarily bonded to the upper surface of the silicon-based backplane, and the first mask is removed; a transparent sealing cover is formed on the upper surface of the silicon-based backplane. The method helps to further reduce the pixel size of the silicon-based backplane multi-primary-color LED light-emitting array pixel matrix display, making it possible for the silicon-based backplane active matrix OLED microdisplay to develop towards the direction of high pixel density and multi-color mixing.

Description

Manufacturing method of silicon-based backplane LED display

technical field

The invention relates to the field of display technology, in particular to a method for manufacturing a silicon-based backplane LED display.

Background technique

Compared with the traditional display represented by TFT-LCD, the active matrix LED display with organic light-emitting diode (OLED) as the core has fast response speed, large color gamut, high contrast ratio, wide viewing angle, high photoelectric efficiency, and thin device thickness. And many other advantages, not only become the best display technology choice for terminal application systems such as mobile terminals, portable electronics, and even digital TVs, but also become the best display technology solution for emerging application terminal systems such as virtual reality (Virtual Reality). Among them, the VR helmet-mounted display system with microdisplay as the core has restrictions on the size and area of the imaging area of the microdisplay, and within the limited area and size, the resolution of the microdisplay is getting higher and higher, that is, the resolution of the pixel Density (that is, the number of pixels per unit area) requirements will continue to increase.

Specifically, the core of the OLED unit on each pixel in an OLED display is the organic emission layer between the anode and the cathode, and the holes provided from the anode and the electrons provided from the cathode will recombine in the organic emission layer To generate an exciton, which is an electron-hole pair, and the exciton returns to the ground state, releasing energy in the form of light emission.

The active matrix OLED display manufactured based on the glass substrate TFT process, due to the large size of its own substrate and the limitations of process equipment, greatly restricts the lithography accuracy of the processing technology, the reduction of pixel size and the improvement of pixel density. The improvement of display resolution is constrained. For example, to achieve a pixel density of 1,500PPI (that is, 1,500 pixels per inch), it means that the pixel size needs to be reduced to about 17 microns, and the required photolithography process almost enters the sub-micron scale. For the traditional TFT process manufacturing of the substrate, it is a considerable technical challenge. At the same time, according to the needs of VR display and its system applications, the frame frequency should be further increased while increasing the resolution, which poses considerable technical challenges to the performance of TFT (thin film transistor) response speed and so on. Therefore, the silicon-based backplane active matrix OLED microdisplay technology based on large-scale integrated circuit technology and CMOS transistors naturally becomes a better choice to solve the two thresholds of high frame frequency and high resolution technology.

Compared with the matrix display with red, green and blue transparent color filter array (Color filter array) configured with pure white OLED emission layer, the multi-primary-color OLED array pixel matrix display has a larger The color gamut and higher photoelectric efficiency make it a better choice for various end application systems, but the processing is more difficult.

At the same time, because the performance and reliability of the OLED emissive layer are extremely sensitive to water molecules and other solutions and ion contamination and chemical reactions, the traditional silicon-based wafer etching method is no longer suitable for OLED emissive layer sub-pixels composed of multi-primary colors. The micromachining of light-emitting pixel arrays has become a more feasible technical path by referring to the mainstream method used in the processing of multi-primary-color OLED array displays on TFT substrates. Certain vertical metal mesh screens (masks) are placed on the corresponding lower electrode surfaces on the TFT substrate in turn, and organic emission layers of different colors are locally deposited (such as evaporated). Unfortunately, this method not only requires a large-scale, somewhat curved metal mask to maximize the proximity to the TFT panel surface, but also must prevent it from any contact with the TFT panel surface (to cause surface damage or residue) In order to improve the optical alignment accuracy between the metal mask and the lower electrode on the TFT panel, and to further reduce the size of the metal mesh screen hole, it will encounter huge technical challenges, thus constraining the further reduction of the pixel size, and it has become a silicon-based backplane. A fundamental technological bottleneck in the development of source-matrix multi-primary-color OLED microdisplays to high-pixel-density multi-color mixing.

Contents of the invention

The object of the present invention is to provide a method for manufacturing a silicon-based backplane LED display, comprising steps:

Provide a silicon-based backplane, including the upper surface of the silicon-based backplane and the lower surface of the silicon-based backplane opposite thereto;

Form substrate optical alignment marks on the silicon-based backplane;

providing a first mask, including an upper surface of the first mask and an opposite lower surface of the first mask;

forming a first mask optical alignment mark on the first mask, and a plurality of first through holes forming a first through hole array;

placing the first mask in parallel on the silicon-based backplane to form a vertical optical alignment between the optical alignment mark of the first mask and the optical alignment mark of the substrate;

Based on the vertical optical alignment between the optical alignment mark of the first mask plate and the optical alignment mark of the substrate, the temporary bonding of the first mask plate and the silicon-based backplane is formed, wherein the lower surface of the first mask plate opposite to the upper surface of the silicon-based backplane;

Depositing the first LED emission layer from above the upper surface of the first mask plate through the first through hole in the first sub-pixel region array formed by the plurality of first sub-pixel regions exposed on the upper surface of the silicon substrate backplane ;

Release the temporary bonding between the first mask plate and the silicon-based backplane, and remove the first mask plate;

A transparent sealing cover is formed on the surface of the silicon-based backplane.

Compared with the prior art, the manufacturing method of the present invention adopts a set of specially prepared hard mask plates each containing a corresponding through-hole array, through the optical alignment marks of the hard mask plate and the silicon-based backplane, and the silicon-based backplane respectively. The substrate and the backplane take turns to form high-precision alignment and temporary bonding in the vertical direction, so that the through hole array on the hard mask and the corresponding lower electrode array on the silicon substrate form an accurate optical alignment in the vertical direction, and then through Deposit the OLED emission layer of the corresponding color on the electrode through the through hole, and then release the temporary bonding of the group of hard mask templates and the silicon-based backplane respectively; repeat the temporary bonding of all hard mask templates and silicon-based backplanes After the process of bonding, deposition of OLED emission layer of corresponding color and release of bonding between hard mask and silicon backplane, a transparent upper electrode covering OLED emission layer and a capping layer for surface sealing are formed by thin film deposition. In this method, through the high-precision alignment bonding between the hard mask and the silicon-based backplane, the OLED emission layer is accurately deposited on the corresponding lower electrode by means of the through-hole array on the hard mask, thereby further reducing the pixel size, making Silicon-based backplane active-matrix OLED microdisplays are likely to develop in the direction of high pixel density and multi-color mixing.

Description of drawings

Fig. 1 is the flow chart of the manufacturing method of the silicon-based backplane OLED microdisplay of the first embodiment of the present invention;

2 to 10 are schematic diagrams of a method for manufacturing a silicon-based backplane OLED microdisplay according to a first embodiment of the present invention;

11 is a flowchart of a method for manufacturing a silicon-based backplane OLED microdisplay according to a second embodiment of the present invention;

12 to 14 are schematic diagrams of a method for manufacturing a silicon-based backplane OLED microdisplay according to a second embodiment of the present invention;

15 is a flowchart of a method for manufacturing a silicon-based backplane OLED microdisplay according to a third embodiment of the present invention;

16 to 19 are schematic diagrams of a method for manufacturing an OLED microdisplay with a silicon-based backplane according to a third embodiment of the present invention.

detailed description

The active visual display and its drive circuit of the present invention will be described in more detail below with reference to schematic diagrams. It should be understood that those skilled in the art can modify the present invention described here while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

first embodiment

Fig. 1 is the flow chart of the manufacturing method of the silicon-based backplane OLED microdisplay of the first embodiment of the present invention, with reference to Fig. 1, the manufacturing method of the silicon-based backplane LED display of the present invention, comprises steps:

S10, providing a silicon-based backplane;

S20, forming an optical alignment mark of the substrate on the silicon-based backplane close to the lower surface of the silicon-based backplane or the lower surface of the silicon-based backplane;

S30, providing a first mask, including an upper surface of the first mask and an opposite lower surface of the first mask;

S40, forming a first mask optical alignment mark on the first mask, and a plurality of first through holes forming a first through hole array;

S50, placing the first mask on the silicon-based backplane in parallel, forming a vertical optical alignment between the optical alignment mark of the first mask and the optical alignment mark of the substrate;

S60, based on the vertical optical alignment between the first mask optical alignment mark and the substrate optical alignment mark, forming a temporary bond between the first mask plate and the silicon-based backplane;

S70, depositing the first LED emission layer on the first sub-pixel region formed by the plurality of first sub-pixel regions exposed on the upper surface of the silicon substrate backplane through the first through hole from above the upper surface of the first mask plate inside the array;

S80, releasing the temporary bonding between the first mask plate and the silicon-based backplane, and removing the first mask plate;

S90, forming a transparent sealing cover on the surface of the silicon-based backplane.

2 to 10 are schematic diagrams of a method for manufacturing a silicon-based backplane OLED microdisplay according to a first embodiment of the present invention. Referring to FIGS. 2 to 10 , the first embodiment will be described in detail.

Execute step S10 , referring to FIG. 2 , providing a silicon-based backplane 100 , including an upper surface 101 of the silicon-based backplane and a lower surface 102 of the silicon-based backplane opposite thereto. The silicon-based backplane 100 is made of a single crystal silicon material. Silicon-based backplane OLED microdisplays are different from conventional AMOLED devices that use amorphous silicon, microcrystalline silicon or low-temperature polysilicon thin-film transistors as backplanes. It is based on a single-crystal silicon chip, and the pixel size is about 1/10 of traditional display devices. The left and right are even smaller, and the fineness is much higher than that of traditional devices. Monocrystalline silicon can be used as the base of the existing mature integrated circuit CMOS process, which has a higher integration level, greatly reduces the external wiring of the device, increases reliability, and realizes light weight.

Execute step S20, continue to refer to FIG. 2 , and form a substrate optical alignment mark 105 on the silicon-based backplane 100 close to the lower surface 102 of the silicon-based backplane or the lower surface 102 of the silicon-based backplane, for performing post-processing between the substrate and the mask. The alignment improves the accuracy of the process.

In this embodiment, preferably, referring to FIG. 3 , it further includes the step of: forming a first lower electrode 111 in each first sub-pixel region on the upper surface of the silicon-based backplane, and the first sub-pixel region Multiple first lower electrodes 111 in the array form a first lower electrode array.

In this embodiment, preferably, the first lower electrode is an LED cathode with a relatively low work function, and is composed of any one or more of metals Mg, Ca, Al, Ag and their alloy materials . Preferably, the distance between two adjacent first lower electrodes in the first lower electrode array is less than 25 microns, which is based on the existing bonding technology between silicon-based wafers, and its horizontal alignment accuracy has been able to Reach 0.5 microns or even below 0.25 microns. This step is located after the step S10 of providing a silicon-based backplane and before the step S20 of forming the vertical optical alignment mark of the first mask plate and the optical alignment mark of the substrate.

In this embodiment, preferably, further comprising steps:

S203 , referring to FIG. 4 , providing an electrostatic adsorption bottom plate 500 , and bonding the electrostatic adsorption bottom plate 500 to the bottom of the silicon-based backplane 100 . The electrostatic adsorption bottom plate absorbs the bottom of the silicon-based backplane by means of electrostatic action, thereby reducing damage to the silicon-based backplane while effectively holding the silicon-based backplane, and making the operation convenient. This step is before the step S50 of placing the first mask in parallel on the silicon-based backplane, so that the silicon-based backplane can be temporarily bonded to the first mask. Of course, other methods can also be used, which are not limited here.

In this embodiment, preferably, a step is further included: forming an active matrix drive circuit 160 on the silicon-based backplane, and the source matrix drive circuit 160 includes a first electrode electrically connected to each first lower electrode 111. A pixel sub-circuit and peripheral driving circuit; form the input and output pins of the active matrix driving circuit.

Step S30 is executed, and referring to FIG. 5 , a first mask 200 is provided, including an upper surface 201 of the first mask and an opposite lower surface 202 of the first mask. In this embodiment, preferably, the material of the first mask plate 200 is also silicon, so that there will be no difference in horizontal thermal expansion between the first through hole 211 and the silicon-based backplane in the subsequent process. The vertical dislocation of the first electrode 111 affects the vertical alignment between the first LED emitting layer 151 and the first electrode 111 . In addition, other materials can also be used, as long as the thermal expansion coefficient of the mask can be configured to be the same or close to that of the silicon base.

Step S40 is executed, and referring to FIG. 5 , a first mask optical alignment mark 205 is formed on the first mask 200 , and a plurality of first through holes 211 form a first through hole array. The spacing and arrangement sequence between the first through holes 211 are in one-to-one correspondence with the positions of the first lower electrodes 111 on the silicon substrate backplate, so as to ensure that the positions can be corresponding in the subsequent bonding process, and the first The through holes can be formed by etching methods known to those skilled in the art, and details will not be repeated here. In this embodiment, preferably, the surface passivation layer of the first through hole is made of metal, including but not limited to aluminum, titanium, cobalt, tungsten, tantalum, nickel, gold, silver and any alloy thereof. It is possible to protect the surface of the first through hole during the cleaning step, and also make cleaning easier to remove impurities.

Execute step S50, continue to refer to FIG. 5, place the first mask 200 in parallel on the silicon-based backplane 100, and form the optical alignment mark 205 of the first mask and the optical alignment mark 105 of the substrate. Vertical optical alignment.

Execute step S60, referring to FIG. 6 , based on the vertical optical alignment between the first mask optical alignment mark 205 and the substrate optical alignment mark 105, the first mask plate 200 and the silicon-based backplane 100 are formed. Temporary bonding, so that the first through hole 211 just exposes the first lower electrode 111 . In this embodiment, the bonding of the first mask plate and the silicon-based backplane is preferably achieved through the bottom pad 220 , other methods may also be used, such as direct thermal fusion bonding.

In this embodiment, referring to FIG. 7 , preferably, the temporary bonding between the lower surface of the first mask plate and the upper surface of the silicon-based backplane is by means of a plurality of edge clamps 610 that are individually mechanically bonded to the silicon-based backplane 100 . Clamp to achieve.

Execute step S70, referring to FIG. 8 , depositing the first LED emission layer 151 on the plurality of first sub-layers exposed by the upper surface 101 of the silicon-based backplane through the first through hole 211 from above the upper surface 201 of the first mask plate. The first sub-pixel area array formed by the pixel area covers the first lower electrode 111 . The first LED emitting layer is preferably composed of an inorganic semiconductor, and may also be composed of an organic compound semiconductor. The deposition of the first LED emitting layer is realized by any one method among evaporation, vapor deposition and inkjet printing, such as evaporation.

Step S80 is executed, referring to FIG. 9 , releasing the temporary bonding between the first mask plate 200 and the silicon-based backplane 100 , and removing the first mask plate 200 .

Execute step S90, referring to FIG. 10, a transparent sealing cover 190 is formed on the upper surface 101 of the silicon-based backplane. The sealing cover can be a semiconductor material such as silicon dioxide, which can be formed by vapor deposition, or can be formed by using The packaging method is directly bonded to the surface of the silicon-based backplane. .

second embodiment

The second embodiment also includes the steps of:

S10, providing a silicon-based backplane 100;

S20, forming a substrate optical alignment mark 105 on the silicon-based backplane 100 close to the lower surface of the silicon-based backplane or the lower surface of the silicon-based backplane;

A first lower electrode 111 is formed in each first sub-pixel region on the upper surface of the silicon-based backplane, and a plurality of first lower electrodes 111 in the first sub-pixel region array constitute a first lower electrode array .

S30, providing a first mask 200, including an upper surface of the first mask and an opposite lower surface of the first mask;

S40, forming a first mask optical alignment mark 205 on the first mask, and a plurality of first through holes 211 to form a first through hole array;

S50, placing the first mask plate 200 in parallel on the silicon-based backplane 100, forming a vertical optical alignment between the optical alignment mark of the first mask plate and the optical alignment mark of the substrate;

S60, based on the vertical optical alignment between the first mask optical alignment mark and the substrate optical alignment mark, forming a temporary bond between the first mask 200 and the silicon-based backplane 100;

S70, depositing the first LED emission layer 151 on the first sub-pixel formed by the plurality of first sub-pixel regions exposed on the upper surface of the silicon substrate backplane through the first through hole from above the upper surface of the first mask plate inside the area array;

S80, releasing the temporary bonding between the first mask plate and the silicon-based backplane, and removing the first mask plate;

The same steps as the first embodiment will not be repeated, the difference is:

Referring to FIG. 11 , after forming the array of the first lower electrodes 111, before the step S90 of forming a transparent sealing cover on the silicon-based backplane 100, the steps include:

A second lower electrode 121 is formed in each second sub-pixel region on the upper surface 101 of the silicon-based backplane, and a plurality of second lower electrodes 121 in the second sub-pixel region array form a second lower electrode array.

Preferably, an active matrix driving circuit is formed on the silicon-based backplane 100, and the source matrix driving circuit includes first pixels electrically connected to each of the first lower electrode 111 and the second lower electrode 121 respectively. sub-circuit, second pixel sub-circuit and peripheral driving circuit.

After releasing the temporary bonding between the first mask 200 and the silicon-based backplane 100 and removing the first mask 200 in step S80, and before forming a transparent sealing cover on the silicon-based backplane 100 S90, the following sub-steps are included :

Sub-step S821, referring to FIG. 12 , provides a second mask 300, including the upper surface 301 of the second mask and the lower surface 302 of the second mask opposite; in this embodiment, for the above reasons, the The material of the second mask 300 is also the same silicon as that of the first mask.

Sub-step S822, referring to FIG. 12 , forming a second mask optical alignment mark 305 on the second mask, and a second through-hole array composed of a plurality of second through-holes 311; the second through-holes 311 The spacing between them and the arrangement sequence correspond to the positions of the second lower electrodes 121 on the silicon-based backplate one by one to ensure that the positions can be corresponding in the subsequent bonding process. The etching method well-known to personnel is formed, and will not be repeated here. In this embodiment, preferably, the surface passivation layer of the second through hole is made of metal, including but not limited to aluminum, titanium, cobalt, tungsten, tantalum, nickel, gold, silver and any alloy thereof. The surface of the second through hole can be protected during the cleaning step, which also makes cleaning easier to remove impurities.

Sub-step S823, referring to FIG. 12 , placing the second mask 300 in parallel on the silicon-based backplane 100 to form a vertical line between the optical alignment mark 305 of the second mask and the optical alignment mark 105 of the substrate. Optical alignment.

Based on the vertical optical alignment between the second mask optical alignment mark 305 and the substrate optical alignment mark 105, the temporary bonding between the second mask plate 300 and the silicon-based backplane 100 is formed, so that the The second through hole 311 just exposes the second lower electrode 121 . In this embodiment, it is worth noting that since the first LED emitting layer 151 covering the first lower electrode 111 has been formed on the upper surface 102 of the silicon-based backplane, in this embodiment, the second mask 300 and the silicon The bonding between the base and backplanes 100 is achieved by adhering the bottom gasket, so that the first LED emission layer 151 is raised above the height of the top layer of the first LED emission layer 151 relative to the surface of the silicon base, so that It is not damaged, and it is also prevented from sticking to the bottom of the second through hole 212 when the second LED emitting layer 152 is deposited. If the temporary bonding between the lower surface 302 of the second mask 300 and the upper surface 101 of the silicon-based backplane 100 is achieved by electrostatic adsorption, in order to achieve electrostatic isolation, the bottom gasket 220 is made of a dielectric material Poses as well.

In addition, other bonding methods can also be used in other embodiments, for example, the second mask or the silicon-based backplane can include a dielectric layer with grooves, so as to perform bonding by thermal fusion, The first LED emission layer is located in the groove.

Sub-step S824, continue to refer to FIG. 12 , based on the vertical optical alignment between the optical alignment mark of the second mask plate and the optical alignment mark of the substrate, a temporary alignment between the second mask plate 300 and the silicon-based backplane 100 is formed. Bonding is achieved by means of a plurality of edge clamps 610 individually forming mechanical clamps with the silicon-based backplane 100 , of course, it is also possible to choose to only use electrostatic adsorption to the bottom plate.

Sub-step S825, continue to refer to FIG. 12 , deposit the second LED emitting layer 152 on the plurality of second LED emission layers exposed by the upper surface 101 of the silicon substrate backplane from above the upper surface 301 of the second mask plate through the second through hole 311. The second sub-pixel area array formed by the sub-pixel area covers the second lower electrode 121;

The first sub-pixel area and the second sub-pixel area do not intersect or overlap on the upper surface of the silicon substrate backplane.

The second LED emitting layer is preferably composed of an inorganic semiconductor, and may also be composed of an organic compound semiconductor. The deposition of the second LED emitting layer is realized by any one method among evaporation, vapor deposition and inkjet printing, such as evaporation.

Sub-step S826 , referring to FIG. 13 , releases the temporary bonding between the second mask 300 and the silicon-based backplane 100 , and removes the second mask 300 .

In this embodiment, referring to FIG. 14 , preferably, step S827 is further included, forming a shared upper electrode film 180 in physical contact with the first LED emission layer 151 and the second LED emission layer 152 on the upper surface of the silicon substrate backplane. .

Step S90 is executed, referring to FIG. 13 , forming a transparent sealing cover 190 on the upper surface 101 of the silicon substrate backplane.

third embodiment

The third embodiment also includes the steps of:

S10, providing a silicon-based backplane 100;

S20, forming a substrate optical alignment mark 105 on the silicon-based backplane 100 close to the lower surface of the silicon-based backplane or the lower surface of the silicon-based backplane;

A first lower electrode 111 is formed in each first sub-pixel region on the upper surface of the silicon-based backplane, and a plurality of first lower electrodes 111 in the first sub-pixel region array constitute a first lower electrode array .

A second lower electrode 121 is formed in each second sub-pixel region on the upper surface 101 of the silicon-based backplane, and a plurality of second lower electrodes 121 in the second sub-pixel region array form a second lower electrode array.

S30, providing a first mask 200, including an upper surface of the first mask and an opposite lower surface of the first mask;

S40, forming a first mask optical alignment mark 205 on the first mask, and a plurality of first through holes 211 to form a first through hole array;

S50, placing the first mask plate 200 in parallel on the silicon-based backplane 100, forming a vertical optical alignment between the optical alignment mark of the first mask plate and the optical alignment mark of the substrate;

S60, based on the vertical optical alignment between the first mask optical alignment mark and the substrate optical alignment mark, forming a temporary bond between the first mask 200 and the silicon-based backplane 100;

S70, depositing the first LED emission layer 151 on the first sub-pixel formed by the plurality of first sub-pixel regions exposed on the upper surface of the silicon substrate backplane through the first through hole from above the upper surface of the first mask plate inside the area array;

S80, releasing the temporary bonding between the first mask plate and the silicon-based backplane, and removing the first mask plate;

Sub-step S821, providing a second mask 300;

Sub-step S822, forming a second mask optical alignment mark 305 and a second through-hole array composed of a plurality of second through-holes 311 on the second mask;

Sub-step S823, placing the second mask 300 in parallel on the silicon-based backplane 100 to form a vertical optical alignment between the optical alignment mark 305 of the second mask and the optical alignment mark 105 of the substrate;

Sub-step S824, based on the vertical optical alignment between the second mask optical alignment mark and the substrate optical alignment mark, forming a temporary bond between the second mask 300 and the silicon-based backplane 100;

Sub-step S825, depositing the second LED emission layer 152 from above the upper surface 301 of the second mask plate through the second through hole 311 on the exposed second sub-pixel regions of the silicon substrate backplane upper surface 101 In the second sub-pixel area array, that is, covering the second lower electrode 121;

Sub-step S826 is executed to release the temporary bonding between the second mask plate 300 and the silicon-based backplane 100 , and remove the second mask plate 300 .

The same steps of the third embodiment and the second embodiment will not be repeated, the difference is:

Referring to FIG. 15 , after forming the first lower electrode 111 array and the second lower electrode 121 array step, before forming a transparent sealing cover on the silicon-based backplane 100, step S231 is included:

A third lower electrode 131 is formed in each third sub-pixel region on the upper surface 101 of the silicon-based backplane, and a plurality of third lower electrodes 131 in the third sub-pixel region array constitute a third lower electrode array; wherein each third lower electrode 131 is in one-to-one correspondence with the first lower electrode 111 and the second lower electrode 121 , and is arranged in an orderly manner.

Preferably, an active matrix driving circuit is formed on the silicon-based backplane 100, and the source matrix driving circuit includes electrical connections with each of the first lower electrode, the second lower electrode and the third lower electrode, respectively. The first pixel sub-circuit, the second pixel sub-circuit, the third pixel sub-circuit and the peripheral driving circuit form the input and output pins of the active matrix driving circuit.

After releasing the temporary bonding between the lower surface of the second mask 300 and the upper surface of the silicon-based backplane and removing the second mask 300, before the step of forming a transparent sealing cover on the silicon-based backplane, further Include the following sub-steps:

S8211, referring to FIG. 16 , providing a third mask 400, including the upper surface 401 of the third mask plate and the lower surface 402 of the third mask plate opposite; in this embodiment, the material of the third mask plate 400 It is made of the same silicon as the first mask plate and the second mask plate, so that the subsequent steps are more convenient to operate, with higher precision and better process compatibility. Besides, other materials are also possible.

S8212, referring to FIG. 16 , forming a third mask optical alignment mark 405 on the third mask 400, and a third through hole array composed of a plurality of third through holes 411; The spacing between them and the order of arrangement are in one-to-one correspondence with the positions of the first electrodes 111 or the second lower electrodes 121 on the silicon-based backplate, so as to ensure that the positions can be corresponding in the subsequent bonding process, and the third through holes 411 It can be formed by an etching method well known to those skilled in the art, and will not be repeated here. In this embodiment, preferably, the surface passivation layer of the third through hole is made of metal, including but not limited to aluminum, titanium, cobalt, tungsten, tantalum, nickel, gold, silver and any alloy thereof. The surface of the third through hole can be protected during the cleaning step, which also makes cleaning easier to remove impurities.

S8213, referring to FIG. 16 , placing a third mask in parallel on the silicon-based backplane to form a vertical optical alignment between the optical alignment mark of the third mask and the optical alignment mark of the substrate;

S8214, referring to FIG. 16 , based on the vertical optical alignment between the third mask optical alignment mark 405 and the substrate optical alignment mark 105, form the third mask lower surface 402 and the upper surface of the silicon substrate backplane. The temporary bonding of 101 makes the third through hole 411 just expose the third bottom electrode 131 . In this embodiment, it is also worth noting that since the first LED emitting layer 151 covering the first lower electrode 111 and the second LED emitting layer covering the second lower electrode 112 have been formed on the upper surface 102 of the silicon substrate backplane 152, so in this embodiment, the bonding between the third mask plate 400 and the silicon-based backplane 100 is realized by adhering the bottom pad, so that the first LED emission layer 151 and the second LED emission layer 152 Overhead, the height of the overhead will exceed the height of the top layer of the first LED emission layer 151 and the second LED emission layer relative to the surface of the silicon base, so that it will not be damaged, and it will also avoid contact with the third LED emission layer 153 when depositing the third LED emission layer 153. Via bottom sticking. If the temporary bonding between the lower surface 402 of the third mask 400 and the upper surface 101 of the silicon-based backplane 100 is achieved by electrostatic adsorption, in order to achieve electrostatic isolation, the bottom gasket 220 is made of a dielectric material. it is good.

In addition, other bonding methods can also be used in other embodiments, for example, the third mask or the silicon-based backplane can include a dielectric layer with grooves, so as to perform bonding by thermal fusion, The first LED emitting layer and the second LED emitting layer are located in the groove.

Wherein, the temporary bonding of the first mask, the third mask and the third mask to the silicon-based backplane respectively can be achieved through the electrostatic adsorption effect of the electrostatic adsorption base on the first mask. to fulfill. Of course, it can also be realized by means of a plurality of edge clamps 610 individually forming mechanical clamps with the silicon-based backplane 100 .

S8215, depositing the third LED emission layer 153 on the upper surface 101 of the silicon substrate backplane from above the upper surface 401 of the third mask plate through the third through hole 411 to form a third In the sub-pixel area array; any two of the first sub-pixel area, the second sub-pixel area and the third sub-pixel area do not intersect or overlap on the upper surface of the silicon substrate backplane.

The third LED emitting layer is preferably composed of an inorganic semiconductor, and may also be composed of an organic compound semiconductor. The deposition of the third LED emitting layer is realized by any one method among evaporation, vapor deposition and inkjet printing, such as evaporation.

S8217 , referring to FIG. 17 , releasing the temporary bonding between the third mask 400 and the silicon-based backplane 100 , and removing the third mask 400 .

Referring to FIG. 18, after the step of removing the third mask plate and before the step of forming a transparent sealing cover, further include:

On the upper surface of the silicon base backplane, a shared upper electrode film 180 is formed in physical contact with the first LED emitter 151 , the second LED emitter layer 152 and the third LED emitter layer 153 .

S90, referring to FIG. 19 , forming a transparent sealing cover 190 on the upper surface 101 of the silicon substrate backplane.

In the above embodiment, preferably, at least one of the first mask, the second mask and the third mask is made of silicon. The preferred solution includes that all masks are made of silicon wafers of the same size as the silicon-based backplane, so as to ensure that the mask and the silicon-based backplane have the same coefficient of thermal expansion, so as to reduce the temperature increase during processing. The mask plate and its through holes are dislocated in the horizontal direction with the silicon-based backplane.

Preferably, at least one of the surfaces of the first through hole, the second through hole and the third through hole is plated with a passivation layer on the surface of the through hole. The entire surface passivation layer is made of metals or alloys with good adhesion to the silicon base, including but not limited to metals such as aluminum, titanium, cobalt, tungsten, tantalum, nickel, gold, silver and any alloys thereof . This can not only reduce the corrosion of the LED luminescent material on the mask plate, especially the surface of the through hole, but also remove the temporary bonding between the mask plate and the silicon-based backplane, and the mask plate to be reused The cleaning process corrodes the surface of the mask plate, thereby improving the reusability of the mask plate and reducing costs.

Preferably, at least one of the first LED emitting layer, the third LED emitting layer and the third LED emitting layer is composed of an inorganic semiconductor or an organic compound semiconductor.

Preferably, the shared upper electrode film is the anode of the LED, has a relatively high work function, and is composed of relatively transparent indium tin oxide (ITO) or indium-doped zinc oxide (IZO); the first The lower electrode, the second lower electrode or the third lower electrode is an LED cathode with a relatively low work function, and is composed of metals such as Mg, Ca, Al, Ag and their alloy materials.

Preferably, the first lower electrode, the second lower electrode or the third lower electrode is an LED anode with a relatively high work function, which is composed of indium tin oxide (ITO) or indium-doped zinc oxide (IZO), so The shared upper electrode thin film is an LED cathode with low work function and high light transmittance, and is composed of metals Mg, Ca, Al, Ag and their alloy materials.

Preferably, the first LED emitting layer, the third LED emitting layer and the third LED emitting layer are different from each other, being luminescent materials corresponding to different spectral regions, so as to generate a desired color gamut through combination.

Preferably, the first LED emission layer, the third LED emission layer and the third LED emission layer are different from each other, and each is a primary color luminescent material corresponding to the three primary colors of red, blue, and green, that is, the most common display combination of the three primary colors.

Preferably, the first LED emission layer, the third LED emission layer and the third LED emission layer are different from each other, and each is a primary color luminescent material corresponding to one of the three primary colors of yellow, magenta, and cyan, that is, the other of the display The most common combination of the three primary colors.

Preferably, the deposition of the first LED emitting layer, the second LED emitting layer or the third LED emitting layer is achieved by any one method among evaporation, vapor deposition and inkjet printing.

Preferably, a plurality of first lower electrodes are formed on the upper surface of the silicon substrate to form a first lower electrode array, an equal number of second lower electrodes forms a second lower electrode array, and an equal number of third lower electrodes forms a third lower electrode array. The step of the lower electrode array can also be achieved by bonding the same mask plate containing the through hole array to the silicon backplane and depositing the electrode material through the through holes. The specific steps include:

providing a fourth mask plate, including the upper surface of the fourth mask plate and the opposite lower surface of the fourth mask plate;

Form the fourth mask plate optical alignment mark on the fourth mask plate, and a plurality of first electrode precipitation through holes form the first electrode precipitation through hole array, and the same number of second electrode precipitation through holes form the second electrode precipitation The through hole array and the same number of third electrode precipitation through holes form the third electrode precipitation through hole array;

placing the fourth mask in parallel on the silicon-based backplane to form a vertical optical alignment between the optical alignment mark of the substrate and the optical alignment mark of the fourth mask;

Based on the vertical optical alignment between the fourth mask optical alignment mark and the substrate optical alignment mark, forming a temporary bond between the lower surface of the fourth mask plate and the upper surface of the silicon substrate backplane;

Through the first electrode precipitation through hole, the second electrode precipitation through hole and the third electrode precipitation through hole from above the upper surface of the fourth mask plate, the shared LED lower electrode material is respectively deposited in the corresponding first sub-pixel area, the second In the second sub-pixel area and the third sub-pixel area;

The temporary bonding between the lower surface of the fourth mask plate and the upper surface of the silicon substrate backplane is released, and the fourth mask plate is removed.

The above-mentioned method for manufacturing OLED microdisplays on silicon-based backplanes is also applicable to the manufacture of microdisplays using inorganic semiconductor LEDs as self-luminous components on silicon-based backplanes. For example, the first LED emission layer can be gallium nitride, an inorganic semiconductor LED thin film material that produces blue light, and the method of depositing it on the first electrode array electrode of the silicon-based backplane through the first through hole array can be the most commonly used metal organic Chemical Vapor Deposition (MOCVD). In addition, the second LED emission layer and the third LED emission layer can be made of inorganic semiconductor materials gallium arsenide and gallium phosphide that produce red and green primary colors, or gallium nitride that produces blue primary colors can be placed on them. Red and green fluorescent materials are used to realize three-color display.

In addition, the above-mentioned manufacturing method for silicon-based backplane OLED microdisplays is also applicable to the manufacture of silicon-based backplane OLED microdisplays with more than three primary color combinations; for example, five primary color combinations can be used to further broaden the more common red, green and blue three primary colors The range of color gamuts that can be represented by the combination. Similarly, the method disclosed above is also applicable to the high-precision alignment temporary bonding of a single mask plate (such as the first mask plate) containing a single through-hole array (such as the first through-hole array) and a silicon-based backplane. It is used in the manufacture of displays with red, green and blue transparent color filter arrays configured with pure white OLED emission layers.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (24)

1. A method for manufacturing a silicon-based backplane LED display, characterized in that it comprises the steps: Provide a silicon-based backplane, including the upper surface of the silicon-based backplane and the lower surface of the silicon-based backplane opposite thereto; Form substrate optical alignment marks on the silicon-based backplane; providing a first mask, including an upper surface of the first mask and an opposite lower surface of the first mask; forming a first mask optical alignment mark on the first mask, and a plurality of first through holes forming a first through hole array; placing the first mask in parallel on the silicon backplane to form a vertical optical alignment between the optical alignment mark of the first mask and the optical alignment mark of the substrate; Based on the vertical optical alignment between the optical alignment mark of the first mask and the optical alignment mark of the substrate, the temporary bonding between the first mask and the silicon-based backplane is formed, wherein the first mask The lower surface is opposite to the upper surface of the silicon-based backplane; Depositing the first LED emission layer from above the upper surface of the first mask plate through the first through hole in the first sub-pixel region array formed by the plurality of first sub-pixel regions exposed on the upper surface of the silicon substrate backplane ; Release the temporary bonding between the first mask plate and the silicon-based backplane, and remove the first mask plate; A transparent sealing cover is formed on the surface of the silicon-based backplane. 2. The method for manufacturing an LED display with a silicon-based backplane according to claim 1, wherein after the step of providing a silicon-based backplane, the optical alignment mark of the first mask plate and the optical alignment of the substrate are formed. Prior to the vertical optical alignment step of the bit mark, include the steps of: A first lower electrode is formed in each first sub-pixel region on the upper surface of the silicon-based backplane, and a plurality of first lower electrodes in the first sub-pixel region array constitute a first lower electrode array. 3. The method for manufacturing a silicon-based backplane LED display according to claim 2, characterized in that, after the step of providing the silicon-based backplane, the step of placing the first mask in parallel on the silicon-based backplane Before, further include: An active matrix driving circuit is formed on the silicon-based backplane, and the source matrix driving circuit includes a first pixel sub-circuit electrically connected to each first lower electrode and a peripheral driving circuit; Forms the input and output pins of the active matrix drive circuit. 4. the manufacture method of silicon-based backplane LED display according to claim 2, is characterized in that, After forming the first lower electrode array, before forming a transparent sealing cover on the silicon-based backplane, the steps include: A second lower electrode is formed in each second sub-pixel region on the upper surface of the silicon-based backplane, and a plurality of second lower electrodes in the second sub-pixel region array form a second lower electrode array; After releasing the temporary bonding between the lower surface of the first mask and the upper surface of the silicon-based backplane and removing the first mask, and before forming a transparent sealing cover on the silicon-based backplane, the steps include: providing a second mask plate, including an upper surface of the second mask plate and an opposite lower surface of the second mask plate; forming a second mask optical alignment mark on the second mask, and a second through-hole array composed of a plurality of second through-holes; placing the second mask in parallel on the silicon-based backplane to form a vertical optical alignment between the optical alignment mark of the second mask and the optical alignment mark of the substrate; Based on the vertical optical alignment between the optical alignment mark of the second mask plate and the optical alignment mark of the substrate, a temporary bond between the second mask plate and the silicon-based backplane is formed, wherein the lower surface of the second mask plate opposite to the upper surface of the silicon-based backplane; Depositing the second LED emission layer on the second sub-pixel area array formed by the plurality of second sub-pixel areas exposed on the upper surface of the silicon substrate back plate through the second through hole from above the upper surface of the second mask plate; The temporary bonding between the second mask plate and the silicon-based backplane is released, and the second mask plate is removed. 5. The manufacturing method of the silicon-based backplane LED display according to claim 4, characterized in that, after the step of providing the silicon-based backplane, the step of placing the first mask in parallel on the silicon-based backplane Before, further include: An active matrix drive circuit is formed on the silicon-based backplane, and the source matrix drive circuit includes a first pixel sub-circuit and a second pixel sub-circuit respectively electrically connected to each first lower electrode and second lower electrode and peripheral drive circuits; Forms the input and output pins of the active matrix drive circuit. 6. The method for manufacturing a silicon-based backplane LED display according to claim 4, further comprising: On the upper surface of the silicon base backplane, a shared upper electrode film is formed that is in physical contact with the first LED emission layer and the second LED emission layer. 7. The method for manufacturing a silicon-based backplane LED display according to claim 4, characterized in that, after forming the first lower electrode array and the second lower electrode array step, a transparent sealing seal is formed on the silicon-based backplane Before covering, include steps: forming a plurality of third lower electrodes to form a third lower electrode array, wherein each third lower electrode is in one-to-one correspondence with the first lower electrode and the second lower electrode, and is arranged in an orderly manner; After the step of releasing the temporary bonding between the lower surface of the second mask and the upper surface of the silicon-based backplane and removing the second mask, before the step of forming a transparent sealing cover on the silicon-based backplane, further comprising: providing a third mask plate, including the upper surface of the third mask plate and the opposite lower surface of the third mask plate; forming a third mask optical alignment mark on the third mask, and a third through hole array composed of a plurality of third through holes; placing the third mask in parallel on the silicon-based backplane to form a vertical optical alignment between the optical alignment mark of the third mask and the optical alignment mark of the substrate; Based on the vertical optical alignment between the optical alignment mark of the third mask and the optical alignment mark of the substrate, the temporary bonding between the third mask and the silicon-based backplane is formed, wherein the lower surface of the third mask opposite to the upper surface of the silicon-based backplane; Depositing the third LED emitting layer on the upper surface of the third mask plate through the third through hole in the third sub-pixel area array formed by a plurality of third sub-pixel areas exposed on the upper surface of the silicon substrate back plate; Release the temporary bonding between the third mask and the silicon-based backplane, and remove the third mask. 8. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein any two of the first sub-pixel region, the second sub-pixel region and the third sub-pixel region are formed on silicon The upper and upper surfaces of the substrate do not intersect or overlap. 9. The method for manufacturing a silicon-based backplane LED display according to claim 7, further comprising: On the upper surface of the silicon base backplane, a shared upper electrode thin film is formed that is in physical contact with the first LED emitting layer, the second LED emitting layer and the third LED emitting layer. 10. The method for manufacturing a silicon-based backplane LED display according to claim 9, wherein the shared upper electrode film is an anode of an LED, has a relatively high work function, and is made of relatively transparent indium tin oxide (ITO) or indium-doped zinc oxide (IZO); the first lower electrode, the second lower electrode or the third lower electrode is an LED cathode with a lower work function, and is made of metals Mg, Ca, Any one or more of Al, Ag and their alloy materials. 11. The method for manufacturing a silicon-based backplane LED display according to claim 9, wherein the first lower electrode, the second lower electrode or the third lower electrode is an LED anode with a relatively high work function , consisting of indium tin oxide (ITO) or indium-doped zinc oxide (IZO), the shared upper electrode film is an LED cathode with low work function and high light transmittance, made of metals Mg, Ca, Al , Ag and their alloy materials. 12. The method for manufacturing an LED display with a silicon-based backplane according to claim 7, further comprising: Provide an electrostatic adsorption bottom plate, and combine the electrostatic adsorption bottom plate to the bottom of the silicon-based backplane; Wherein, the temporary bonding between the lower surface of the first mask plate, the lower surface of the third mask plate and the lower surface of the third mask plate and the upper surface of the silicon substrate backplane is through the electrostatic adsorption base plate to the first mask plate. It is realized by electrostatic adsorption of a mask plate. 13. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein at least one of the first mask, the second mask and the third mask is made of silicon. 14. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein at least one of the surfaces of the first through hole, the second through hole and the third through hole is coated with a passivation layer on the surface of the through hole . 15. The method for manufacturing a silicon-based backplane LED display according to claim 14, wherein the passivation layer on the surface of the through hole is made of metal, including but not limited to aluminum, titanium, cobalt, tungsten, tantalum , nickel, gold, silver and any alloy thereof. 16. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein at least one of the first LED emission layer, the third LED emission layer and the third LED emission layer is an inorganic semiconductor or Organic compound semiconductor composition. 17. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein the first LED emission layer, the third LED emission layer, and the third LED emission layer are different from each other and are respectively corresponding to Luminescent materials in different spectral regions. 18. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein the first LED emission layer, the third LED emission layer and the third LED emission layer are different from each other, each It is a primary color luminescent material corresponding to the three primary colors of red, blue and green. 19. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein the first LED emitting layer, the third LED emitting layer and the third LED emitting layer are different from each other, each It is a primary color luminescent material corresponding to the three primary colors of yellow, magenta and cyan. 20. The method for manufacturing an LED display with a silicon-based backplane according to claim 7, characterized in that, after the step of providing the silicon-based backplane, the step of placing the first mask in parallel on the silicon-based backplane Before, further include: An active matrix driving circuit is formed on the silicon-based backplane, and the source matrix driving circuit includes a first pixel sub-circuit electrically connected to each of the first lower electrode, the second lower electrode and the third lower electrode, respectively, The second pixel sub-circuit and the third pixel sub-circuit and a peripheral driving circuit; Forms the input and output pins of the active matrix drive circuit. 21. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein the lower surface of the first mask, the lower surface of the second mask, or the lower surface of the third mask is in contact with the silicon The temporary bonding of the upper surface of the substrate is achieved by means of a plurality of edge clamps to form mechanical clamps with the silicon-based backplane respectively. 22. The method for manufacturing a silicon-based backplane LED display according to any one of claims 1, 4 or 7, wherein the two adjacent first lower electrodes in the first lower electrode array The distance between them is less than 25 microns. 23. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein the deposition of the first LED emission layer, the second LED emission layer or the third LED emission layer is by evaporation, Either method of vapor deposition and inkjet printing. 24. The method for manufacturing a silicon-based backplane LED display according to claim 7, wherein a plurality of first lower electrodes are formed on the upper surface of the silicon-based backplane to form a first lower electrode array, and an equal number of first lower electrodes are formed. The step of forming a second lower electrode array with two lower electrodes and forming a third lower electrode array with an equal number of third lower electrodes includes: providing a fourth mask plate, including the upper surface of the fourth mask plate and the opposite lower surface of the fourth mask plate; Form the fourth mask plate optical alignment mark on the fourth mask plate, and a plurality of first electrode precipitation through holes form the first electrode precipitation through hole array, and the same number of second electrode precipitation through holes form the second electrode precipitation The through hole array and the same number of third electrode precipitation through holes form the third electrode precipitation through hole array; placing the fourth mask in parallel on the silicon-based backplane to form a vertical optical alignment between the optical alignment mark of the substrate and the optical alignment mark of the fourth mask; Based on the vertical optical alignment between the optical alignment mark of the fourth mask and the optical alignment mark of the substrate, the temporary bonding between the fourth mask and the silicon-based backplane is formed, wherein the lower surface of the fourth mask opposite to the upper surface of the silicon-based backplane; Through the first electrode precipitation through hole, the second electrode precipitation through hole and the third electrode precipitation through hole from above the upper surface of the fourth mask plate, the shared LED lower electrode material is respectively deposited in the corresponding first sub-pixel area, the second In the second sub-pixel area and the third sub-pixel area; Release the temporary bonding between the fourth mask plate and the silicon-based backplane, and remove the fourth mask plate.