CN107330203B - Method for automatically exporting length of PCB (printed Circuit Board) line and generating relation report - Google Patents

Abstract

The invention discloses a method for automatically exporting the length of a PCB wire and generating a relation report in the field of PCB design, which comprises the steps of establishing a BUS with the same signal time sequence of the whole project, confirming the conditions of all connected devices of signals and setting the XNET of the branch of the device; generating an XLS table through linkage, carrying out symbol conversion, and generating a length report of a signal; different lists are built for all BUSs in the XLS, and judgment values with equal time sequence and the like are filled. The invention solves the problems of rapid signal extraction, accuracy, rapid signal correction, delayed signal use and the like, reduces errors of manual input, and quickens the time of input of rechecking personnel, thereby improving the working efficiency.

Description

Method for automatically exporting length of PCB (printed Circuit Board) line and generating relation report

Technical Field

The invention relates to the field of PCB design, in particular to a method for automatically exporting the length of a PCB wire and generating a relation report.

Background

In the PCB design process, whether the signal exceeds the required length value always influences the designer. If the length value is too long, it is considered that distortion occurs when the sound is out of range, and therefore, this problem is evaluated and confirmed as early as possible in the initial stage of wiring. However, in order to increase the initial wiring speed, the PCB is designed to perform cooperative work, and thus, the content evaluated by one person may change in the middle. This change may cause a large area of rework if the problem is not discovered until later.

In the conventional design, all time-series equal-length signals are manually extracted into EXCEL, then signal values are extracted, branch signal values are added to obtain the total length, and finally, the relational expression needs to be manually set. These works are less in manual examination under the condition of less data, but as the data increase, how to confirm whether the signal name input is correct, whether the numerical value addition is correct, whether the setting of relationship judgment is correct, etc., these all provide greater examination for the assessment worker, and the inaccurate judgment can cause that other manpower is required to be input again to carry out repeated examination and test at the later stage, thereby affecting the whole design work.

The above-mentioned drawbacks are worth solving.

Disclosure of Invention

In order to overcome the defects of the prior art, the invention provides a method for automatically exporting the length of a PCB (printed Circuit Board) line and generating a relation report.

The technical scheme of the invention is as follows:

a method for automatically exporting the length of a PCB wire and generating a relation report is characterized in that a BUS with the same time sequence of a signal of the whole project is established, the conditions of all connected devices are confirmed, and XNET of the branch of the device is set; generating an XLS table through linkage, carrying out symbol conversion, and generating a length report of a signal; different lists are built for all BUSs in the XLS, and judgment values with equal time sequence and the like are filled.

The invention according to the above scheme is characterized by specifically comprising the following steps:

step 1, establishing BUS processing needing to be equal in signal time sequence of the whole project, and recording the signal time sequences into ALLEGRO software;

step 2, sorting out the relation of all signals connected with resistance signals in series, removing pull-up and pull-down resistors, reserving butt-joint resistors, and setting XNET for resistor branches;

step 3, extracting the relevant information of the ALLEGRO, outputting the XLS file according to the corresponding format, outputting the lengths of all signals to the REPORT of the ALLEGRO, sticking the signals to the EXCEL, and replacing the symbols to enable the derived signal names to obtain the corresponding length information;

step 4, classifying the information of the signals and the lengths, and placing the information into each worksheet of the EXCEL;

and 5, filling the MAX and MIN lengths of the signal branches and the total NET and the ERROR values of the branches and the total NET, and then generating ERROR and PASS to determine whether the project time sequence length meets the requirement or not.

Further, in the step 1, a signal of the BUS is extracted in the PIN of the BGA, or the signal of the BUS is extracted through an input connector and an output connector; the required signal is framed by EDIT- > Property under ALLEGRO, and BUS name is set by selecting ASSIGN _ ROUTE _ LAYER parameter.

Further, in step 2, XNET is set for the signal resistance in which NET is generated in a branch in the middle of the signal, instead of generating NET length in two points.

Further, XNET setting is performed by using the analysis- > SI/EMI Sim- > Model Assignment program under ALLEGRO and selecting the corresponding resistance.

Further, in the step 3, the data in the alloroller is extracted by using the programming function of the skip, the obtained data is input into the EXCEL, and the numerical values in the XLS level are added, so that the relation judgment is directly programmed.

Further, in the step 5, after the EXCEL report is generated, the report is typeset, and the relational expression is filled.

Further, the process of typesetting and filling specifically includes:

(1) the plug-in worksheet Sheet1 runs out all length reports by using ALLEGRO and pastes the reports into the worksheet;

(2) classifying different worksheets of each BUS to form a uniform format;

(3) filling in the judging values of the corresponding MAX and MIN lengths and length errors;

(4) filling out the BUS name, the signal and the corresponding length;

(5) typesetting a BUS classification column, and setting all signals and length columns of the project;

(6) the total length of the fill signal, the MAX value, the GROUP ERROR, the DIFF ERROR, the relationship ERROR, and the PASS field.

The invention according to the scheme has the advantages that the SKILL program is used for combining the ALLEGRO software and the EXECL software to generate seamless link; the invention uses the program to process the signals according to the formatting, solves the problems of quick extraction, accuracy, quick correction, delay and the like of the signals, reduces errors of manual input, and quickens the time of input of reexamination personnel, thereby improving the working efficiency.

Drawings

FIG. 1 is a flow chart of the present invention.

FIG. 2 is a flow chart of the operating portion of the ALLEGRO software of the present invention.

Fig. 3 is a flow chart of the SKILL program portion of the present invention.

FIG. 4 is a flow chart of the EXCEL software operating portion of the present invention.

FIG. 5 is an interface diagram of the present invention for filling in BUS name, signal, length, etc.

FIG. 6 is an interface diagram of the BUS classification bar, all signals of the items and the length bar of the layout of the present invention.

FIG. 7 is an interface diagram of the fill-in total length MAX value, ERROR, relationship ERROR, PASS fields, etc. of the present invention.

Detailed Description

The invention is further described with reference to the following figures and embodiments:

as shown in fig. 1, a method for automatically exporting the length of a PCB line and generating a relation report includes establishing a BUS with equal signal time sequence of the whole project, confirming the condition of all connected devices, and setting XNET of device branches; generating an XLS table through linkage, carrying out symbol conversion, and generating a length report of a signal; different lists are built for all BUSs in the XLS, and judgment values with equal time sequence and the like are filled.

The method specifically comprises the following steps:

1. and (3) establishing BUS processing needing to be equal in signal time sequence of the whole project, and recording the signal time sequences into ALLEGRO software.

As shown in fig. 2, the signal of the BUS is extracted in the PIN of the BGA, or through the input and output connectors; the required signal is framed by EDIT- > Property under ALLEGRO, and BUS name is set by selecting ASSIGN _ ROUTE _ LAYER parameter.

2. The relation of all signals connected with the resistor signals in series is sorted out, pull-up and pull-down resistors are eliminated, butt-joint resistors are reserved, and XNET setting is carried out on resistor branches.

The method is characterized in that XNET is set for the signal resistance of a signal which is not two points generating NET length but has a branch generating NET in the middle, and XNET is set by selecting the corresponding resistance through the analysis- > SI/EMI Sim- > Model Assignment program under ALLEGRO.

3. Extracting the related information of ALLEGRO, outputting XLS files according to the corresponding format, outputting the lengths of all signals to the REPORT of ALLEGRO, sticking the signals to EXCEL, and replacing symbols to obtain the corresponding length information of the derived signal names.

As shown in fig. 3, data in alloroller is extracted by using the programming function of skip, the obtained data is input to EXCEL, and the numerical values in XLS class are added to directly perform the relation determination. The specific operation code employed in this embodiment is given below, the code being divided into 6 large blocks:

(1) defun netlengthlist () window sets and displays blocks;

(2) netlenghlist _ format () creates blocks such as window characters, buttons, and the like;

(3) netlenghlist _ key _ action (form) in-window button execution block;

(4) netlengthlist1() main program block,

data generated for ALLEGRO is imported into the program. A distinction is made whether XNET is present. A distinction is made between DIFF and non-DIFF. When the signal has branches, analyzing the sequence of the front-end signal and the back-end signal;

(5) a netlenghlist _ net () single-line signal addition, a relational decision format processing block;

(6) the netlength hlist _ DIFF () DIFF signals are added, and the format processing block is determined by the relational expression.

The specific codes are as follows:

4. and classifying the information of the signals and the lengths, and placing the information into each worksheet of the EXCEL.

5. The lengths of MAX and MIN of the signal branch and the total NET and the ERROR values of the branch and the total NET are filled, and then two judgments of ERROR and PASS are generated to confirm whether the project time sequence length is in accordance with the requirement or not.

As shown in fig. 4, the operations of generating the EXCEL report, then typesetting the report, and filling the relational expression specifically include:

(1) the plug-in worksheet Sheet1 runs out all length reports by using ALLEGRO and pastes the reports into the worksheet;

(2) classifying different worksheets of each BUS to form a uniform format;

(3) filling in the judging values of the corresponding MAX and MIN lengths and length errors;

(4) as shown in fig. 5, fill in the BUS name, signal and corresponding length;

(5) as shown in fig. 6, the BUS classification bar, all signal and length bars of the item are laid out;

(6) as shown in FIG. 7, the total length of the fill signal, the MAX value, the GROUP ERROR, the DIFF ERROR, the relationship ERROR, and the PASS field.

It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

The invention is described above with reference to the accompanying drawings, which are illustrative, and it is obvious that the implementation of the invention is not limited in the above manner, and it is within the scope of the invention to adopt various modifications of the inventive method concept and technical solution, or to apply the inventive concept and technical solution to other fields without modification.

Claims (6)

1. A method for automatically exporting the length of a PCB wire and generating a relation report is characterized in that a BUS with the same time sequence of a signal of the whole project is established, the conditions of all connected devices are confirmed, and XNET of the branch of the device is set; generating an XLS table through linkage, carrying out symbol conversion, and generating a length report of a signal; establishing different lists for all BUSs in the XLS, and filling time sequence equal length judgment values; the method specifically comprises the following steps:

step 1, establishing BUS processing needing to be equal in signal time sequence of the whole project, and recording the signal time sequences into ALLEGRO software;

step 2, the relation that all signals are connected with resistance signals in series is cleared, pull-up and pull-down resistors are eliminated, butt-joint resistors are reserved, XNET setting is carried out on resistor branches, and XNET setting is carried out on signal resistors which have branches to generate NET in midway instead of generating NET lengths at two points;

step 3, extracting the relevant information of the ALLEGRO, outputting the XLS file according to the corresponding format, outputting the lengths of all signals to the REPORT of the ALLEGRO, sticking the signals to the EXCEL, and replacing the symbols to enable the derived signal names to obtain the corresponding length information;

step 4, classifying the information of the signals and the lengths, and placing the information into each worksheet of the EXCEL;

and 5, filling the MAX and MIN lengths of the signal branches and the total NET and the ERROR values of the branches and the total NET, and then generating ERROR and PASS to determine whether the project time sequence length meets the requirement or not.

2. The method for automatically exporting the length of the PCB wire and generating the relational report according to claim 1, wherein in the step 1, the BUS signal is extracted in the PIN of BGA or through the input and output connectors;

the required signal is framed by EDIT- > Property under ALLEGRO, and BUS name is set by selecting ASSIGN _ ROUTE _ LAYER parameter.

3. The method of claim 1, wherein XNET is set by analyzing- > SI/EMI Sim- > Model Assignment under alloguro and selecting the corresponding resistor.

4. The method as claimed in claim 1, wherein in step 3, data in ALLEGRO is extracted by using SKILL programming function, the obtained data is inputted into EXCEL, and the values in XLS files are added, so that the relation determination is directly programmed.

5. The method for automatically exporting the length of the PCB line and generating the relational report as claimed in claim 1, wherein in the step 5, the report is typeset after the EXCEL report is generated, and the relational filling is performed.

6. The method for automatically exporting the length of the PCB line and generating the relational report as claimed in claim 5, wherein the process of typesetting and filling comprises:

(1) the plug-in worksheet Sheet1 runs out all length reports by using ALLEGRO and pastes the reports into the worksheet;

(2) classifying different worksheets of each BUS to form a uniform format;

(3) filling in the judging values of the corresponding MAX and MIN lengths and length errors;

(4) filling out the BUS name, the signal and the corresponding length;

(5) typesetting a BUS classification column, and setting all signals and length columns of the project;

(6) the total length of the fill signal, the MAX value, the GROUP ERROR, the DIFF ERROR, the relationship ERROR, and the PASS field.

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