CN107301975A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention provides a semiconductor device and a method for manufacturing the same, the semiconductor device includes: a first conductive type substrate; a second conductive type body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; a first conductive type first well disposed in the second conductive type body region; a gate structure disposed on an upper surface of the first conductive type substrate; a source region including a heavily doped source region of a first conductivity type and disposed in the body region of a second conductivity type; and the drain region is provided with a heavily doped first conduction type and is arranged in the first conduction type first well. The invention has simple process steps, and can simultaneously arrange the N-type metal oxide semiconductor and the P-type metal oxide semiconductor in the P-type substrate under the condition of not increasing the number of masks and excessive process cost, even not increasing the cost.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to semiconductor technology, and more particularly to semiconductor devices and methods of manufacturing the same.

Background technique

High-voltage semiconductor device technology is suitable for high-voltage and high-power integrated circuits. Conventional high-voltage semiconductor devices, such as horizontally diffused metal oxide semiconductor (LDMOS) devices, are mainly used in the field of device applications above 18V. The advantage of high-voltage device technology is that it is cost-effective and easily compatible with other processes. It has been widely used in the fields of display driver IC components, power supplies, power management, communications, automotive electronics, or industrial control.

Generally, high-voltage semiconductor devices use N-type metal oxide semiconductor (NMOS) instead of P-type metal-oxide semiconductor (PMOS), and the N-type metal oxide semiconductor is usually disposed on a P-type substrate. However, current semiconductor devices such as high voltage semiconductor devices are not satisfactory in every respect. For example, if an N-type MOS and a P-type MOS are to be formed on a P-type substrate at the same time, traditionally one or more epitaxial processes are required to form the P-type MOS on the P-type substrate. However, this process step is difficult and the process cost is high.

Therefore, the industry still needs a manufacturing method with simple process, low process cost and the ability to form a P-type metal oxide semiconductor on a P-type substrate, so that those skilled in the art of this invention can simultaneously set the P-type substrate on the P-type substrate. N-type metal oxide semiconductors and P-type metal oxide semiconductors without increasing excessive process costs.

Contents of the invention

The present invention provides a semiconductor device, comprising: a first conductive type substrate; a second conductive type main body region disposed in the first conductive type substrate, wherein the first conductive type is different from the second conductive type; the first conductive type first The well is arranged in the body region of the second conductivity type; the gate structure is arranged on the upper surface of the substrate of the first conductivity type; the source region, wherein the source region includes a heavily doped source region of the first conductivity type, and is provided in the body region of the second conductivity type; and the drain region, wherein the drain region has the heavily doped first conductivity type and is arranged in the first well of the first conductivity type.

The present invention further provides a method for manufacturing a semiconductor device, including: providing a substrate of a first conductivity type; forming a body region of a second conductivity type in the substrate of the first conductivity type, wherein the first conductivity type is different from the second conductivity type; forming the second conductivity type A first conductivity type well is in the second conductivity type body region; a gate structure is formed on the upper surface of the first conductivity type substrate; a source region is formed, wherein the source region includes a first conductivity type heavily doped source region , and disposed in the second conductivity type body region; and forming a drain region, wherein the drain region has heavily doped first conductivity type, and is disposed in the first conductivity type first well.

The beneficial effect of the embodiment of the present invention is that the process steps of the embodiment of the present invention are simple, and the N-type substrate can be provided in the P-type substrate at the same time without increasing the number of masks and excessive process costs, or even without increasing the cost. Metal oxide semiconductors and P-type metal oxide semiconductors.

In order to make the features and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

Description of drawings

1 shows a cross-sectional view of a semiconductor device in one step of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

2 shows a cross-sectional view of a semiconductor device in one step of a method for manufacturing a semiconductor device according to some embodiments of the present invention;

3 shows a cross-sectional view of a semiconductor device in one step of the method for manufacturing a semiconductor device according to some embodiments of the present invention;

FIG. 4 shows a cross-sectional view of a semiconductor device in a step of the method for manufacturing a semiconductor device according to some embodiments of the present invention.

reference sign

100 first conductive type substrate;

100S1 upper surface;

100S2 lower surface;

102 the second conductive type body region;

104A the first well of the first conductivity type;

104B the second well of the first conductivity type;

104C the third well of the first conductivity type;

106A the first doped region of the first conductivity type;

106B the second doped region of the first conductivity type;

108 field oxide layer;

108A opening;

110 grid structure;

110A gate dielectric layer;

110B gate electrode;

112 source region;

112A The heavily doped source region of the first conductivity type;

112B second conductivity type heavily doped source region;

114 drain region;

116 first conductive type channel area;

118 second conductivity type heavily doped region;

120 first conductivity type heavily doped region;

122 interlayer dielectric layer;

124D drain contact plug;

124S1 first source contact plug;

124S2 second source contact plug;

124A contact plug;

124B BODY CONTACT PLUG;

126D wire;

126S wire;

126B wire;

128 protective layers;

130D conductive pad;

130S conductive pad;

200 Semiconductor device.

detailed description

The semiconductor device and its manufacturing method of the present invention will be described in detail below. It should be appreciated that the following description provides many different embodiments or examples for implementing different aspects of the invention. The specific elements and arrangements described below are only for the purpose of simply and clearly describing the present invention. Of course, these are only examples rather than limitations of the present invention. Furthermore, repeated reference numerals or designations may be used in different embodiments. These repetitions are only for the purpose of simply and clearly describing the present invention, and do not represent any relationship between the different embodiments and/or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation that the first material layer is in direct contact with the second material layer. Alternatively, one or more layers of other material may be interspersed, in which case there may be no direct contact between the first material layer and the second material layer.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element to another element in the drawings. It will be understood that if the illustrated device is turned over so that it is upside down, elements described as being on the "lower" side would then be described as being on the "higher" side.

Here, the terms "about", "approximately" and "approximately" usually mean within 20%, preferably within 10%, and more preferably within 5%, or within 3% of a given value or range. Within %, or within 2%, or within 1%, or within 0.5%, or within 0.3%. The given quantity here is an approximate quantity, that is, the meanings of "about", "about" and "approximately" can still be implied if "about", "approximately" and "approximately" are not specified.

It can be understood that although the terms "first", "second", "third" and the like may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, Regions, layers, and/or sections should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or sections. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, and/or section without departing from the teachings of the present invention. part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It can be understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the background or context of the related art and the present invention, and should not be interpreted in an idealized or overly formal manner. Interpretation, unless otherwise defined in the present invention.

The embodiments of the present invention can be understood together with the drawings, and the drawings of the present invention are also regarded as a part of the disclosure. It should be understood that the drawings of the present invention are not shown in scale of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings in order to clearly represent the features of the present invention. In addition, the structures and devices in the drawings are shown schematically in order to clearly show the features of the present invention.

In the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom" etc. should be understood as the Orientation shown in paragraph and related drawings. This relative term is for convenience of description only, and it does not mean that the described device must be manufactured or operated in a specific orientation. The terms about jointing and connection, such as "connection", "interconnection", etc., unless otherwise specified, may refer to two structures that are in direct contact, or may also refer to two structures that are not in direct contact, and other structures are provided here. between the two structures. And the terms about joining and connecting may also include the situation that both structures are movable, or both structures are fixed.

It should be noted that the term "substrate" hereinafter may include elements already formed on a semiconductor wafer and various film layers covering the wafer, on which any desired semiconductor elements may have been formed, but here for the sake of simplification In the drawing, only the flat substrate is shown. In addition, "substrate surface" includes the uppermost and exposed film layer on the semiconductor wafer, such as a silicon surface, an insulating layer and/or metal lines.

The embodiment of the present invention utilizes the novel configuration of the doped region in the P-type substrate to form a P-type metal oxide semiconductor in a P-type substrate, and cooperates with the known formation of an N-type metal oxide semiconductor in a P-type substrate. The technology can simultaneously arrange N-type metal oxide semiconductors and P-type metal oxide semiconductors in a P-type substrate.

In addition, since the embodiment of the present invention is to form the P-type metal oxide semiconductor in the P-type substrate by changing the configuration of the doped region of the semiconductor device, the process steps of the embodiment of the present invention are simple and can be achieved without adding a mask. The number and the excessive process cost, even without increasing the cost, the N-type metal oxide semiconductor and the P-type metal oxide semiconductor are arranged on the P-type substrate at the same time.

FIG. 1 shows a cross-sectional view of a semiconductor device in a step of a method for manufacturing a semiconductor device according to some embodiments of the present invention. As shown in FIG. 1 , firstly, a substrate 100 of a first conductivity type is provided. The first conductive type substrate 100 can be a semiconductor substrate, such as a silicon substrate. In addition, the above-mentioned semiconductor substrate can also be an elemental semiconductor, including germanium; a compound semiconductor, including gallium nitride (GaN), silicon carbide, gallium arsenide, gallium phosphide ( gallium phosphide), indium phosphide, indium arsenide and/or indium antimonide; alloy semiconductors, including silicon-germanium alloy (SiGe), gallium-arsenide-phosphorus alloy (GaAsP), arsenic AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP or combinations thereof. In addition, the first conductive type substrate 100 may also be a semiconductor on insulator. In some embodiments, the first conductive type substrate 100 may be a lightly doped P-type substrate.

In the embodiments, "lightly doped" means a doping concentration of about 10 ¹¹ -10 ¹³ /cm ³ , for example a doping concentration of about 10 ¹² /cm ³ . However, those skilled in the art can understand that the definition of "lightly doped" can also be determined according to a specific device type, technology generation, minimum device size, and the like. Therefore, the definition of "lightly doped" should be re-evaluated depending on the technical content, but not limited to the examples presented here.

Continuing to refer to FIG. 1 , the body region 102 of the second conductivity type is formed in the substrate 100 of the first conductivity type. This second conductivity type is different from the first conductivity type. For example, in some embodiments of the present invention, the second conductivity type is N type, and the first conductivity type is P type.

The body region 102 of the second conductivity type can be formed by ion implantation. For example, when the second conductivity type is N type, phosphorous ions or arsenic ions can be implanted into the region where the second conductivity type body region 102 is to be formed to form the second conductivity type body region 102 . In addition, the second conductive type body region 102 may directly contact the upper surface 100S1 of the first conductive type substrate 100 .

It should be noted that, in the above-described embodiments, unless "lightly doped" or "heavily doped" is not specified, "doped" means a doping concentration of about 10 ¹⁴ -10 ¹⁶ /cm ³ , for example The doping concentration is about 10 ¹⁵ /cm ³ . In other words, in some embodiments, the doping concentration of the body region 102 of the second conductivity type may be about 10 ¹⁴ -10 ¹⁶ /cm ³ , for example, about 10 ¹⁵ /cm ³ . However, those skilled in the art can understand that the definition of "doping" can also be determined according to a specific device type, technology generation, minimum device size, and the like. Therefore, the definition of "doping" should be re-evaluated depending on the technical content, and is not limited to the examples presented here.

FIG. 2 is a cross-sectional view of a semiconductor device showing a step of a method for manufacturing a semiconductor device according to some embodiments of the present invention. As shown in FIG. 2 , a first well 104A of the first conductivity type and a second well 104B of the first conductivity type are formed in the body region 102 of the second conductivity type, and no second conductivity type is formed in the substrate 100 of the first conductivity type. A third well 104C of the first conductivity type is formed in the region of the body region 102 . In some embodiments of the present invention, the first well 104A of the first conductivity type and the third well 104C of the first conductivity type are disposed on two opposite sides of the second well 104B of the first conductivity type, respectively.

In some embodiments of the present invention, the first well 104A of the first conductivity type, the second well 104B of the first conductivity type and the third well 104C of the first conductivity type may directly contact the upper surface 100S1 of the substrate 100 of the first conductivity type. In addition, the third well 104C of the first conductivity type can directly contact the body region 102 of the second conductivity type, as shown in FIG. 2 .

In some embodiments of the present invention, the first well 104A of the first conductivity type, the second well 104B of the first conductivity type and the third well 104C of the first conductivity type can be formed by ion implantation. For example, when the first conductivity type is P-type, boron ions, indium ions, and ions or boron difluoride ions (BF ₂ ⁺ ) to form the first well 104A of the first conductivity type, the second well 104B of the first conductivity type and the third well 104C of the first conductivity type.

In addition, in some embodiments of the present invention, the doping concentrations of the first well 104A of the first conductivity type, the second well 104B of the first conductivity type, and the third well 104C of the first conductivity type may be about 10 ¹⁴ -10 ¹⁶ / The doping concentration in cm ³ is, for example, about 10 ¹⁵ /cm ³ . And the doping concentration of the first conductive type first well 104A, the first conductive type second well 104B and the first conductive type third well 104C is greater than the doping concentration of the second conductive type body region 102 .

Continuing to refer to FIG. 2 , a first doped region 106A of the first conductivity type and a second doped region 106B of the first conductivity type are formed in the body region 102 of the second conductivity type. In some embodiments of the present invention, as shown in FIG. 2 , the first doped region 106A of the first conductivity type is located between the first well 104A of the first conductivity type and the second well 104B of the first conductivity type, and directly contacts The first well 104A of the first conductivity type and the second well 104B of the first conductivity type. The first well 104A of the first conductivity type is electrically connected to the second well 104B of the first conductivity type through the first doped region 106A of the first conductivity type, and the first doped region 106A of the first conductivity type does not contact the first doped region of the first conductivity type. The upper surface 100S1 of the substrate 100 and the subsequent field oxide layer.

In addition, in some embodiments of the present invention, the second doped region 106B of the first conductivity type is disposed between the second well 104B of the first conductivity type and the third well 104C of the first conductivity type, and the first conductivity type The second doped region 106B only contacts the body region 102 of the second conductivity type, but does not contact other doped regions shown in FIG. 2 and any subsequent doped regions. In other words, the second doped region 106B of the first conductivity type is not electrically connected to any other doped region, and forms a reduced surface field (RESURF) structure with the body region 102 of the second conductivity type. The embodiment of the present invention can further reduce the surface electric field in the device through the surface electric field reducing structure, thereby further increasing the breakdown voltage of the device.

In addition, in some embodiments of the present invention, the first conductive type second doped region 106B does not contact the upper surface 100S1 of the first conductive type substrate 100 and the subsequent field oxide layer.

In addition, in some embodiments of the present invention, the doping concentration of the first doped region 106A of the first conductivity type and the second doped region 106B of the first conductivity type may be about 10 ¹⁴ -10 ¹⁶ /cm ³ The concentration is, for example, about 10 ¹⁵ /cm ³ . In addition, the doping concentration of the first conductive type first well 104A, the first conductive type second well 104B and the first conductive type third well 104C is higher than that of the first conductive type first doped region 106A and the first conductive type first doped region 106A and the first conductive type The doping concentration of the second doped region 106B, and the doping concentration of the first doped region 106A of the first conductivity type and the second doped region 106B of the first conductivity type is greater than the doping concentration of the body region 102 of the second conductivity type concentration.

Next, referring to FIG. 3 , a field oxide layer 108 is formed on the upper surface 100S1 of the first conductive type substrate 100 . The material of the field oxide layer 108 may include silicon oxide. In some embodiments of the present invention, the field oxide layer 108 may be formed on the upper surface 100S1 of the first conductive type substrate 100 by a thermal oxidation method. However, in some other embodiments of the present invention, the field oxide layer 108 can also be formed by chemical vapor deposition (CVD) or spin coating and patterning steps.

Next, a gate structure 110 is formed on the upper surface 100S1 of the first conductive type substrate 100 . The gate structure 110 includes a gate dielectric layer 110A and a gate electrode 110B formed on the gate dielectric layer 110A. In detail, the gate structure 110 is formed on the second well 104B of the first conductivity type and the field oxide layer 108 in contact with the second well 104B of the first conductivity type. Since there is a height difference between the field oxide layer 108 and the upper surface 100S1 of the substrate 100 of the first conductivity type, and there is also a height difference between the field oxide layer 108 and the gate dielectric layer 110A, the gate structure 110 (or gate The electrode 110B) has a stepped shape. In addition, the second well 104B of the first conductivity type is located under the gate structure 110 .

The material of the gate dielectric layer 110A can be silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or any other suitable dielectric material, or a combination thereof. The material of this high dielectric constant (high-k) dielectric material can be metal oxide, metal nitride, metal silicide, transition metal oxide, transition metal nitride, transition metal silicide, metal oxynitride, Metal aluminates, zirconosilicates, zircoaluminates. For example, the high-k dielectric material can be LaO, AlO, ZrO, TiO, Ta ₂ O ₅ , Y ₂ O ₃ , SrTiO ₃ (STO), BaTiO ₃ (BTO), BaZrO, HfO _2. HfO ₃ , HfZrO, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, HfTaTiO, HfAlON, (Ba, Sr)TiO ₃ (BST), Al ₂ O ₃ , other high dielectric constants of other appropriate materials Dielectric material, or a combination of the above. The gate dielectric layer 110A can be formed by thermal oxidation, chemical vapor deposition (CVD) or spin coating. The chemical vapor deposition method can be, for example, low pressure chemical vapor deposition (LPCVD), low temperature chemical vapor deposition (LTCVD), rapid temperature chemical vapor deposition (rapid thermal chemical vapor deposition) , RTCVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (atomic layer deposition, ALD) of atomic layer chemical vapor deposition, or other commonly used methods.

The material of the aforementioned gate electrode 110B may be amorphous silicon, polysilicon, one or more metals, metal nitrides, conductive metal oxides, or a combination thereof. The aforementioned metals may include, but are not limited to, molybdenum (molybdenum), tungsten (tungsten), titanium (titanium), tantalum (tantalum), platinum (platinum) or hafnium (hafnium). The aforementioned metal nitrides may include but not limited to molybdenum nitride, tungsten nitride, titanium nitride and tantalum nitride. The above-mentioned conductive metal oxide may include but not limited to ruthenium oxide and indium tin oxide. The material of the gate electrode 110B can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition method, for example, in an embodiment Among them, an amorphous silicon conductive material layer or a polysilicon conductive material layer can be deposited by low-pressure chemical vapor deposition (LPCVD) at 525-650°C, and its thickness range can be about to about

Next, referring to FIG. 3 , the source region 112 is formed in the body region 102 of the second conductivity type, and the drain region 114 is formed in the first well 104A of the first conductivity type. The source region 112 and the drain region 114 are respectively disposed on two opposite sides of the gate structure 110 . And in some embodiments of the present invention, the source region 112 is disposed between the gate structure 110 and the second doped region 106B of the first conductivity type or the third well 104C of the first conductivity type.

The drain region 114 has a heavily doped first conductivity type, and the source region 112 includes a heavily doped source region 112A of the first conductivity type and a second conductive region directly contacting the heavily doped source region 112A of the first conductivity type. Type heavily doped source region 112B. The heavily doped source region 112A of the first conductivity type is closer to the gate structure 110 , and the heavily doped source region 112B of the second conductivity type is farther away from the gate structure 110 .

In some embodiments of the present invention, the drain region 114 and the first conductivity type heavily doped source region 112A can be formed by ion implantation. For example, when the first conductivity type is P-type, boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) to form the drain region 114 and the first conductivity type heavily doped source region 112A.

In addition, in some embodiments of the present invention, the heavily doped source region 112B of the second conductivity type can be formed by ion implantation. For example, when the second conductivity type is N type, phosphorous ions or arsenic ions can be implanted into the region where the second conductivity type heavily doped source region 112B is to be formed to form the second conductivity type heavily doped source region 112B.

In the described embodiments, "heavily doped" means a doping concentration exceeding about 10 ¹⁹ /cm ³ , such as a doping concentration of about 10 ¹⁹ /cm ³ to about 10 ²¹ /cm ³ . However, those skilled in the art can understand that the definition of "heavily doped" can also be determined according to a specific device type, technology generation, minimum device size, and the like. Therefore, the definition of "heavily doped" should be re-evaluated depending on the technical content, and is not limited to the examples mentioned here.

In addition, there is a channel region 116 of the first conductivity type under the gate structure 110 . The first conductivity type channel region 116 is located in the first conductivity type substrate 100 (or the second conductivity type body region 102 ) between the first conductivity type heavily doped source region 112A and the first conductivity type second well 104B. middle). In some embodiments of the present invention, when the first conductivity type is P-type and the second conductivity type is N-type, the channel region 116 of the first conductivity type is a P-type channel, and at this time the gate structure 110, the source The electrode region 112 and the drain region 114 jointly form a P-type metal oxide semiconductor, and the above-mentioned first conductive type substrate 100 is a P-type substrate.

It can be seen that the embodiments of the present invention can form a P-type metal oxide semiconductor in a P-type substrate by using the novel doped region configuration provided in the P-type substrate, and cooperate with the known N-type metal oxide semiconductor in the P-type substrate. Oxide semiconductor technology can simultaneously arrange N-type metal oxide semiconductors and P-type metal oxide semiconductors on a P-type substrate.

In addition, since the embodiment of the present invention is to form the P-type metal oxide semiconductor in the P-type substrate by changing the configuration of the doped region of the semiconductor device, the process steps of the embodiment of the present invention are simple and can be achieved without adding a mask. The number and the excessive process cost, even without increasing the cost, the N-type metal oxide semiconductor and the P-type metal oxide semiconductor are arranged on the P-type substrate at the same time.

In some embodiments of the present invention, using the novel configuration of the doped region, the breakdown voltage of the semiconductor device of the embodiment of the present invention can be greater than or equal to 710V, and the on-resistance can be less than or equal to 570mohm-cm ² . In addition, in some embodiments of the present invention, the thickness of the substrate 100 of the first conductivity type of the semiconductor device according to the embodiment of the present invention may be greater than 100 μm. Therefore, the above-mentioned first conductivity type second doped region 106B and the second conductivity type body region The depletion region of the surface electric field reduction structure formed by 102 will not contact the lower surface 100S2 of the substrate 100 of the first conductivity type and affect the performance of the device.

Next, continue to refer to FIG. 3 , the heavily doped region 118 of the second conductivity type can be further formed in the body region 102 of the second conductivity type. The heavily doped region 118 of the second conductivity type is formed in the opening 108A of the field oxide layer 108, and the heavily doped region 118 of the second conductivity type is located between the second doped region 106B of the first conductivity type and the second doped region 106B of the second conductivity type. between heavily doped source regions 112B. In addition, in some embodiments of the present invention, the above-mentioned second doped region 106B of the first conductivity type and the heavily doped source region 112A of the first conductivity type are respectively disposed on two opposite sides of the heavily doped region 118 of the second conductivity type. .

In some embodiments of the present invention, the heavily doped region 118 of the second conductivity type can be formed by ion implantation. For example, when the second conductivity type is N-type, phosphorous ions or arsenic ions can be implanted into the region where the second conductivity type heavily doped region 118 is scheduled to be formed to form the second conductivity type heavily doped region 118 .

Next, referring to FIG. 3 , the heavily doped region 120 of the first conductivity type can be formed in the third well 104C of the first conductivity type. In some embodiments of the present invention, the heavily doped region 120 of the first conductivity type may directly contact the body region 102 of the second conductivity type.

In some embodiments of the present invention, the heavily doped region 120 of the first conductivity type can be formed by ion implantation. For example, when the first conductivity type is P-type, boron ions, indium ions or boron difluoride ions (BF ₂ ⁺ ) can be implanted in the region where the first conductivity type heavily doped region 120 is scheduled to be formed to form the first conductivity type. type heavily doped region 120 .

In addition, in some embodiments of the present invention, the doping concentrations of the above-mentioned heavily doped region 118 of the second conductivity type and the heavily doped region 120 of the first conductivity type are similar or identical to those of the source region 112 and the drain region 114 concentration.

Next, refer to FIG. 4 , which is a cross-sectional view of the semiconductor device 200 showing a step of the manufacturing method of the semiconductor device 200 according to some embodiments of the present invention. As shown in FIG. 4 , an interlayer dielectric (ILD) 122 is formed on the upper surface 100S1 of the first conductive type substrate 100 . The interlayer dielectric layer 122 can be silicon oxide, silicon nitride, silicon oxynitride, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin-on glass (SOG), high density plasma (high density) plasma, HDP) deposited dielectric material or any other suitable dielectric material, or a combination of the above. The interlayer dielectric (ILD) 122 may be formed by the aforementioned chemical vapor deposition (CVD) or spin coating and patterning steps.

Next, continuing to refer to FIG. 4 , a drain contact plug 124D, a first source contact plug 124S1 , a second source contact plug 124S2 , a contact plug 124A and a body contact plug are formed in the interlayer dielectric layer 122 124B. The drain contact plug 124D is electrically connected to the drain region 114, the first source contact plug 124S1 is electrically connected to the first conductivity type heavily doped source region 112A, and the second source contact plug 124S2 is electrically connected to To the heavily doped source region 112B of the second conductivity type, the contact plug 124A is electrically connected to the heavily doped region 118 of the second conductivity type, and the body contact plug 124B is electrically connected to the heavily doped region 120 of the first conductivity type.

In addition, a wire 126D electrically connected to the drain contact plug 124D, electrically connected to the first source contact plug 124S1 , the second source contact plug 124S2 and the contact plug 124A are further formed on the interlayer dielectric layer 122 . The wire 126S of the main body contact plug 124B is electrically connected to the wire 126B.

In some embodiments of the present invention, the drain contact plug 124D, the first source contact plug 124S1 , the second source contact plug 124S2 , the contact plug 124A, the body contact plug 124B and the wires 126D and 126S are connected to The material of 126B may include copper, aluminum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys of the above, combinations of the above, or other metal materials with good electrical conductivity. In other embodiments, the drain contact plug 124D, the first source contact plug 124S1, the second source contact plug 124S2, the contact plug 124A, the body contact plug 124B and the wires 126D, 126S and 126B The material can be a non-metallic material as long as the material used is conductive. The materials of the drain contact plug 124D, the first source contact plug 124S1, the second source contact plug 124S2, the contact plug 124A, the body contact plug 124B, and the wires 126D, 126S and 126B can be obtained through the aforementioned chemistry. Vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition methods.

In addition, in some embodiments of the present invention, the body contact plug 124B and the wire 126B are electrically connected to the substrate 100 of the first conductivity type through the heavily doped region 120 of the first conductivity type and the third well 104C of the first conductivity type. A conductive substrate 100 is grounded.

In addition, a protective layer 128 can be further formed on the interlayer dielectric layer 122, and the protective layer 128 can be silicon nitride, silicon oxide, silicon oxynitride, borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), spin Dielectric material formed by coated glass (SOG), high density plasma (HDP) deposition or any other suitable dielectric material, or a combination thereof, and can be formed by the aforementioned methods.

The protection layer 128 covers the wires 126D, 126S and 126B, and has an opening to expose the wire 126D and the wire 126S. In addition, a conductive pad 130D electrically connected to the wire 126D and a conductive pad 130S electrically connected to the wire 126S may be formed in the opening of the protection layer 128 . The conductive pad 130D is disposed on the wire 126D, and the conductive pad 130S is disposed on the wire 126S.

The material of the conductive pads 130D and 130S may include copper, aluminum, molybdenum, tungsten, gold, chromium, nickel, platinum, titanium, iridium, rhodium, alloys of the above, combinations of the above, or other metal materials with good conductivity. In other embodiments, the material of the above-mentioned conductive pads 130D and 130S can be a non-metallic material, as long as the used material has conductivity. The material of the conductive pads 130D and 130S can be formed by the aforementioned chemical vapor deposition (CVD), sputtering, resistance heating evaporation, electron beam evaporation, or any other suitable deposition methods. In some embodiments, the conductive pads 130D and 130S may be made of the same material, and may be formed through the same deposition process. However, in other embodiments, the conductive pads 130D and 130S may also be formed through different deposition steps, and their materials may be different from each other.

Continuing to refer to FIG. 4 , the semiconductor device 200 includes a substrate 100 of the first conductivity type and a body region 102 of the second conductivity type disposed in the substrate 100 of the first conductivity type. The semiconductor device 200 further includes a first well 104A of the first conductivity type and a second well 104B of the first conductivity type disposed in the body region 102 of the second conductivity type. The third well 104C of the first conductivity type in the region of the body region 102 of the conductivity type. The above-mentioned first well 104A of the first conductivity type and the third well 104C of the first conductivity type are respectively disposed on two opposite sides of the second well 104B of the first conductivity type.

The semiconductor device 200 further includes a first doped region 106A of the first conductivity type and a second doped region 106B of the first conductivity type disposed in the body region 102 of the second conductivity type. The first doped region 106A of the first conductivity type is located between the first well 104A of the first conductivity type and the second well 104B of the first conductivity type, and directly contacts the first well 104A of the first conductivity type and the first well 104A of the first conductivity type. The second well 104B, and the first well 104A of the first conductivity type is electrically connected to the second well 104B of the first conductivity type through the first doped region 106A of the first conductivity type.

The second doped region 106B of the first conductivity type is located between the second well 104B of the first conductivity type and the third well 104C of the first conductivity type, and the second doped region 106B of the first conductivity type only contacts the second well 104C of the first conductivity type. The body region 102 of the second conductivity type does not contact other doped regions, such as the second well 104B of the first conductivity type and the third well 104C of the first conductivity type.

The semiconductor device 200 further includes a gate structure 110 disposed on the upper surface 100S1 of the substrate 100 of the first conductivity type, and the gate structure 110 is disposed on the second well 104B of the first conductivity type. Next, the semiconductor device 200 further includes a source region 112 and a drain region 114 . The source region 112 and the drain region 114 are respectively disposed on two opposite sides of the gate structure 110 . Specifically, the source region 112 is disposed in the body region 102 of the second conductivity type, and is located between the gate structure 110 and the second doped region 106B of the first conductivity type or the third well 104C of the first conductivity type. . The drain region 114 is located in the first well 104A of the first conductivity type.

In addition, the source region 112 includes a heavily doped source region 112A of the first conductivity type and a heavily doped source region 112B of the second conductivity type directly contacting the heavily doped source region 112A of the first conductivity type. The heavily doped source region 112A of the first conductivity type is closer to the gate structure 110 , and the heavily doped source region 112B of the second conductivity type is farther away from the gate structure 110 .

The semiconductor device 200 may further include a channel region 116 of the first conductivity type located under the gate structure 110 and between the heavily doped source region 112A of the first conductivity type and the second well 104B of the first conductivity type. In some embodiments of the present invention, when the first conductivity type is P-type, the channel region 116 of the first conductivity type is a P-type channel, and the gate structure 110, the source region 112 and the drain region 114 are jointly formed. A P-type metal oxide semiconductor, and the first conductive type substrate 100 is a P-type substrate.

The semiconductor device 200 may further include a second conductivity type heavily doped region 118 disposed in the second conductivity type body region 102, and the second conductivity type heavily doped region 118 is located in the first conductivity type second doped region 106B and the second conductivity type heavily doped source region 112B. The semiconductor device 200 may further include a heavily doped region 120 of the first conductivity type disposed in the third well 104C of the first conductivity type.

Furthermore, in some embodiments of the present invention, the semiconductor device 200 may be a high voltage semiconductor device, such as a horizontally diffused metal oxide semiconductor (LDMOS). In some embodiments of the present invention, the semiconductor device 200 uses the P-type substrate 100 , and besides the above-mentioned P-type MOS, the semiconductor device 200 may further include another N-type MOS (not shown).

To sum up, the embodiment of the present invention utilizes the novel configuration of the doped region in the P-type substrate to form a P-type metal oxide semiconductor in the P-type substrate, and cooperates with the known N-type substrate in the P-type substrate. The N-type metal oxide semiconductor technology can simultaneously arrange the N-type metal oxide semiconductor and the P-type metal oxide semiconductor on the P-type substrate.

In addition, since the embodiment of the present invention is to form the P-type metal oxide semiconductor in the P-type substrate by changing the configuration of the doped region of the semiconductor device, the process steps of the embodiment of the present invention are simple and can be achieved without adding a mask. The number and the excessive process cost, even without increasing the cost, the N-type metal oxide semiconductor and the P-type metal oxide semiconductor are arranged on the P-type substrate at the same time.

In addition, it should be noted that those skilled in the art are well aware that the drain and the source in the present invention are interchangeable, because the definition is related to the voltage level to which it is connected.

It should be noted that the above-mentioned device dimensions, device parameters, and device shapes are not limitations of the present invention. Those skilled in this technical field can adjust these setting values according to different needs. In addition, the semiconductor device and its manufacturing method of the present invention are not limited to the states shown in FIGS. 1-4 . The present invention may comprise only any one or more features of any one or more of the embodiments of FIGS. 1-4 . In other words, not all the illustrated features must be implemented in the semiconductor device and its manufacturing method of the present invention at the same time.

In addition, although the foregoing lists the doping concentration of each doped region in some embodiments. However, those skilled in the art can understand that the doping concentration of each doping region can be determined according to a specific device type, technology generation, minimum device size, and the like. Therefore, the doping concentration of each doping region can be re-evaluated according to the technical content, and is not limited to the embodiments herein.

In addition, it should be noted that although in the above embodiments, the first conductivity type is P-type and the second conductivity type is N-type, however, those skilled in the art should understand that the first conductivity type is also It can be N type, and at this time the second conductivity type is P type.

Although the embodiments of the present invention and their advantages have been disclosed above, it should be understood that those skilled in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the protection scope of the present invention is not limited to the process, machine, manufacture, material composition, device, method and steps in the specific embodiments described in the specification, and anyone skilled in the art can understand from the disclosure of the present invention Processes, machines, manufactures, compositions of matter, devices, methods and steps developed at present or in the future can be used in accordance with the present invention as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein. Therefore, the protection scope of the present invention includes the above-mentioned process, machine, manufacture, composition of matter, device, method and steps. In addition, each claim constitutes an individual embodiment, and the protection scope of the present invention also includes combinations of the individual claims and the embodiments.

Claims (20)

1. a kind of semiconductor device, it is characterised in that the semiconductor device includes：

One first conduction type substrate；

One second conductivity type body region, in first conduction type substrate, wherein first conductivity type and described second Conductivity type is different；

One first the first trap of conductivity type, in the second conductivity type body region；

One grid structure, on the upper surface of first conduction type substrate；

Source region, wherein the source area includes one first conductivity type heavy-doped source polar region, and located at second conductivity type In body region；And

One drain region, wherein the drain region has the conductivity type of heavy doping first, and in the trap of the first conductivity type first.

2. semiconductor device according to claim 1, it is characterised in that first conductivity type is p-type, and described second leads Electric type is N-type, and the semiconductor device further includes a p-type passage and is located between the source area and the drain region, and sets Under the grid structure.

3. semiconductor device according to claim 1, it is characterised in that the semiconductor device is further included：

One first the second trap of conductivity type, in the second conductivity type body region, and the trap of the first conductivity type second is located at Under the grid structure；And

One first the first doped region of conductivity type, in the second conductivity type body region, wherein first conductivity type first Trap is electrically connected with the trap of the first conductivity type second by the doped region of the first conductivity type first.

4. semiconductor device according to claim 3, it is characterised in that the doped region of the first conductivity type first is not contacted The upper surface of first conduction type substrate.

5. semiconductor device according to claim 1, it is characterised in that the semiconductor device is further included：

One first the second doped region of conductivity type, in the second conductivity type body region, wherein first conductivity type second Doped region only contacts the second conductivity type body region, without contacting other doped regions.

6. semiconductor device according to claim 5, it is characterised in that the doped region of the first conductivity type second is not contacted The upper surface of first conduction type substrate.

7. semiconductor device according to claim 1, it is characterised in that the source area is further included：

One second conductivity type heavy-doped source polar region, directly contacts the first conductivity type heavy-doped source polar region.

8. semiconductor device according to claim 5, it is characterised in that the semiconductor device is further included：

One second conductivity type heavily doped region, located at the second conductivity type body region, wherein first conductivity type second adulterates The two-phase that area is respectively arranged on the second conductivity type heavily doped region with the first conductivity type heavy-doped source polar region is tossed about.

9. semiconductor device according to claim 1, it is characterised in that the semiconductor device is further included：

The trap of one first conductivity type the 3rd, is formed without the second conductivity type body region in first conduction type substrate Region.

10. semiconductor device according to claim 9, it is characterised in that the semiconductor device is further included：

One first conductivity type heavily doped region, in the trap of the first conductivity type the 3rd.

11. a kind of manufacture method of semiconductor device, it is characterised in that the manufacture method includes：

One first conduction type substrate is provided；

One second conductivity type body region is formed in first conduction type substrate, wherein first conductivity type and described second Conductivity type is different；

One first the first trap of conductivity type is formed in the second conductivity type body region；

A grid structure is formed on the upper surface of first conduction type substrate；

Source region is formed, wherein the source area includes one first conductivity type heavy-doped source polar region, and is led located at described second In electric type body region；And

A drain region is formed, wherein the drain region has the conductivity type of heavy doping first, and located at first conductivity type first In trap.

12. the manufacture method of semiconductor device according to claim 11, it is characterised in that first conductivity type is P Type, second conductivity type is N-type, and the semiconductor device further includes a p-type passage located at the source area and the leakage Between polar region, and under the grid structure.

13. the manufacture method of semiconductor device according to claim 11, it is characterised in that the manufacture method is more wrapped Include：

One first the second trap of conductivity type is formed in the second conductivity type body region, and the trap of the first conductivity type second is located at Under the grid structure；And

One first the first doped region of conductivity type is formed in the second conductivity type body region, wherein first conductivity type first Trap is electrically connected with the trap of the first conductivity type second by the doped region of the first conductivity type first.

14. the manufacture method of semiconductor device according to claim 13, it is characterised in that first conductivity type first Doped region does not contact the upper surface of first conduction type substrate.

15. the manufacture method of semiconductor device according to claim 11, it is characterised in that the manufacture method is more wrapped Include：

One first the second doped region of conductivity type is formed in the second conductivity type body region, wherein first conductivity type second Doped region only contacts the second conductivity type body region, without contacting other doped regions.

16. the manufacture method of semiconductor device according to claim 15, it is characterised in that first conductivity type second Doped region does not contact the upper surface of first conduction type substrate.

17. the manufacture method of semiconductor device according to claim 11, it is characterised in that the source area is further included：

One second conductivity type heavy-doped source polar region, directly contacts the first conductivity type heavy-doped source polar region.

18. the manufacture method of semiconductor device according to claim 15, it is characterised in that the manufacture method is more wrapped Include：

One second conductivity type heavily doped region is formed in the second conductivity type body region, wherein first conductivity type second adulterates The two-phase that area is respectively arranged on the second conductivity type heavily doped region with the first conductivity type heavy-doped source polar region is tossed about.

19. the manufacture method of semiconductor device according to claim 11, it is characterised in that the manufacture method is more wrapped Include：

Form the trap of one first conductivity type the 3rd and the second conductivity type body region is formed without in first conduction type substrate Region.

20. the manufacture method of semiconductor device according to claim 19, it is characterised in that the manufacture method is more wrapped Include：

One first conductivity type heavily doped region is formed in the trap of the first conductivity type the 3rd.