CN107301873A - Decoding method, memory storage device and memory control circuit unit - Google Patents

Abstract

The invention provides a decoding method, a memory storage device and a memory control circuit unit. The decoding method comprises the following steps: reading data from a plurality of first memory cells of the memory cells; evaluating an error bit occurrence rate of the data prior to performing a first coding operation on the data; and performing the first coding operation on the data using a first coding parameter according to the evaluated error bit occurrence rate, wherein the first coding parameter corresponds to a stringency of locating erroneous bits in the first coding operation. The invention can improve the decoding efficiency of the memory storage device.

Description

Decoding method, memory storage device and memory control circuit unit

technical field

The invention relates to a decoding technology, in particular to a decoding method, a memory storage device and a memory control circuit unit.

Background technique

Digital cameras, mobile phones, and MP3 players have grown rapidly in recent years, making consumers' demand for storage media also increase rapidly. Since the rewritable non-volatile memory module (for example, flash memory) has the characteristics of data non-volatility, power saving, small size, and no mechanical structure, it is very suitable for being built in various portable memory modules listed above. in the multimedia device.

Generally, a memory device has one or more built-in decoding mechanisms for correcting possible errors in data read from the memory device. For example, these decoding mechanisms may include decoding algorithms such as Bit-Flipping algorithm, Min-Sum algorithm and Sum-Product algorithm. When the memory device leaves the factory, the built-in decoding algorithm of the memory device will be configured to use optimized operating parameters. However, as the use time and/or frequency of use of the memory device increase, the channel status of the memory device will also change. If the channel state of the memory device changes too much, even with optimized operating parameters, the decoding efficiency of the memory device will often be low.

Contents of the invention

In view of this, the present invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve the decoding efficiency of the memory storage device.

An exemplary embodiment of the present invention provides a decoding method for a rewritable non-volatile memory module including a plurality of memory cells, the decoding method comprising: extracting from the plurality of memory cells A memory cell reads data; before performing a first decoding operation on the data, evaluating an error bit occurrence rate of the data; and using a first decoding parameter to process the data according to the estimated error bit occurrence rate The first decoding operation is performed, wherein the first decoding parameter corresponds to a strict level for locating erroneous bits in the first decoding operation.

In an exemplary embodiment of the present invention, the step of evaluating the bit error rate of the data includes: obtaining a threshold voltage distribution of the first memory cell, wherein the threshold voltage distribution includes a first state and a second state state, wherein the first state corresponds to a first bit value, wherein the second state corresponds to a second bit value, wherein the first bit value is different from the second bit value; and according to the first The total number of memory cells corresponding to the overlapping area between the state and the second state is used to evaluate the error bit occurrence rate of the data.

In an exemplary embodiment of the present invention, the step of evaluating the error bit occurrence rate of the data includes: performing a parity check operation on the data to obtain a plurality of syndromes; accumulating the syndromes to obtain a parity a syndrome sum; and evaluating the error bit occurrence rate of the data based on the syndrome sum, wherein the estimated error bit incidence is positively correlated with the syndrome sum.

In an exemplary embodiment of the present invention, the first decoding parameter is an inversion threshold, and the first decoding operation includes: obtaining a check weight corresponding to each bit in the data; and inverting the At least one bit whose verification weight is greater than the flipping threshold in the data.

In an exemplary embodiment of the present invention, the decoding method further includes: judging whether the first decoding operation fails; if the first decoding operation fails, according to the execution result of the first decoding operation re-evaluating the bit error rate of the data; and performing a second decoding operation on the data using second decoding parameters according to the re-evaluated bit error rate, wherein the second decoding parameters correspond to The degree of precision with which erroneous bits are located in the second decoding operation.

Another exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for connecting to a host system. The rewritable non-volatile memory module includes a plurality of memory cells. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used to send a read command sequence to instruct the Reading data from a plurality of first memory cells, wherein before performing a first decoding operation on the data, the memory control circuit unit is further used to evaluate an error bit occurrence rate of the data, wherein the memory control circuit unit further for performing the first decoding operation on the data according to the estimated erroneous bit occurrence rate using first decoding parameters, wherein the first decoding parameters correspond to The degree of rigor with which the error bits are located.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit evaluating the error bit occurrence rate of the data includes: obtaining a threshold voltage distribution of the first memory cell, wherein the threshold voltage distribution includes a first state and a second state, wherein the first state corresponds to a first bit value, wherein the second state corresponds to a second bit value, wherein the first bit value is different from the second bit value; and evaluating the error bit occurrence rate of the data according to the total number of memory cells corresponding to the overlapping area between the first state and the second state.

In an exemplary embodiment of the present invention, the operation of the memory control circuit unit evaluating the error bit occurrence rate of the data includes: performing a parity check operation on the data to obtain a plurality of syndromes; accumulating the obtaining a syndrome sum; and estimating the bit error rate of the data based on the syndrome sum, wherein the estimated bit error rate is positively correlated with the syndrome sum .

In an exemplary embodiment of the present invention, the first decoding parameter is an inversion threshold, wherein the first decoding operation includes: obtaining a check weight corresponding to each bit in the data; and inverting At least one bit whose verification weight is greater than the flipping threshold in the data.

In an exemplary embodiment of the present invention, the memory control circuit unit is further used for judging whether the first decoding operation fails, wherein if the first decoding operation fails, the memory control circuit unit is further used for Re-evaluate the error bit occurrence rate of the data according to the execution result of the first decoding operation, wherein the memory control circuit unit is further configured to use a second decoding parameter according to the re-evaluated error bit occurrence rate A second decoding operation is performed on the data, wherein the second decoding parameter corresponds to a degree of precision with which erroneous bits are located in the second decoding operation.

Another exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory cells, the The memory control circuit unit includes a host interface, a memory interface, an error checking and correction circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface, the memory interface and the error checking and correction circuit, wherein the memory management circuit is used to send a read command sequence to instruct multiple The first memory cell reads data, wherein before performing a first decoding operation on the data, the memory management circuit is further used to evaluate an error bit occurrence rate of the data, wherein the error checking and correction circuit is used for performing the first decoding operation on the data using first decoding parameters based on the estimated occurrence of erroneous bits, wherein the first decoding parameters correspond to locating erroneous bits in the first decoding operation rigor.

In an exemplary embodiment of the present invention, the operation of the memory management circuit for evaluating the error bit occurrence rate of the data includes: obtaining a threshold voltage distribution of the first memory cell, wherein the threshold voltage distribution includes a first memory cell distribution. a state and a second state, wherein the first state corresponds to a first bit value, wherein the second state corresponds to a second bit value, wherein the first bit value is different from the second bit value; and The error bit occurrence rate of the data is estimated according to the total number of memory cells corresponding to the overlapping area between the first state and the second state.

In an exemplary embodiment of the present invention, the operation of the memory management circuit to evaluate the error bit occurrence rate of the data includes: performing a parity check operation on the data to obtain a plurality of syndromes; accumulating the parity obtaining a syndrome sum; and evaluating the error bit occurrence rate of the data according to the syndrome sum, wherein the estimated error bit occurrence rate is positively correlated with the syndrome sum.

In an exemplary embodiment of the invention, the stringency is positively related to the estimated bit error rate.

In an exemplary embodiment of the present invention, the strictness is positively correlated with the first decoding parameter.

In an exemplary embodiment of the present invention, the first decoding parameter is positively correlated with the estimated bit error rate.

In an exemplary embodiment of the present invention, the first decoding parameter is an inversion threshold, wherein the first decoding operation includes: obtaining a check weight corresponding to each bit in the data; and inverting At least one bit whose verification weight is greater than the flipping threshold in the data.

In an exemplary embodiment of the present invention, the memory management circuit is further configured to determine whether the first decoding operation fails, wherein if the first decoding operation fails, the memory management circuit is further configured to re-evaluating the bit error rate of the data as a result of the first decoding operation, wherein the error checking and correction circuit is further configured to use a second decoding parameter according to the re-evaluated bit error rate performing a second decoding operation on the data, wherein the second decoding parameter corresponds to a degree of precision with which erroneous bits are located in the second decoding operation.

Based on the above, according to the bit error occurrence rate of the data to be decoded, the error checking and correction circuit can flexibly perform a corresponding decoding operation based on a specific decoding parameter. Wherein, the decoding parameter corresponds to the precision of locating error bits in the corresponding decoding operation. Thereby, a balance can be achieved between improving the decoding success rate of each decoding operation and increasing the overall decoding speed, thereby improving the decoding efficiency of the memory storage device.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention;

2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention;

3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

5 is a schematic block diagram of a memory control circuit unit shown according to an exemplary embodiment of the present invention;

FIG. 6 is a schematic diagram of a parity check matrix displayed according to an exemplary embodiment of the present invention;

FIG. 7 is a schematic diagram showing a threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention;

FIG. 8 is a schematic diagram showing a parity check operation according to an exemplary embodiment of the present invention;

FIG. 9 is a flowchart of a decoding method according to an exemplary embodiment of the present invention;

FIG. 10 is a flowchart of a decoding method according to another exemplary embodiment of the present invention;

FIG. 11 is a flowchart of a decoding method according to another exemplary embodiment of the present invention.

Reference signs:

10, 30: memory storage device

11, 31: host system

110: System bus

111: Processor

112: random access memory

113: ROM

114: data transmission interface

12: Input/Output (I/O) device

20: Motherboard

201: Pen drive

202: memory card

203: SSD

204: Wireless memory storage device

205: Global Positioning System Module

206: Network Adapter

207: Wireless transmission device

208: Keyboard

209: screen

210: Horn

32: SD card

33: CF card

34: Embedded storage device

341: Embedded multimedia card

342: Embedded multi-chip package storage device

402: Connect the interface unit

404: memory control circuit unit

406: Rewritable non-volatile memory module

502: memory management circuit

504: host interface

506: memory interface

508: Error checking and correction circuit

510: buffer memory

512: Power management circuit

600, 800: parity check matrix

710, 720: status

701: Read voltage

730: Overlapping area

801: Codeword

802: check vector

S901: step (reading data from the first memory cell of the rewritable non-volatile memory module)

S902: Step (evaluating the error bit occurrence rate of the data)

S903: Step (using a decoding parameter to perform a decoding operation on the data according to the estimated error bit occurrence rate, wherein the decoding parameter corresponds to the precision of locating error bits in the decoding operation)

S1001: step (reading data from the first memory cell of the rewritable non-volatile memory module)

S1002: Step (evaluating the error bit occurrence rate of the data)

S1003: Step (using a decoding parameter to perform a decoding operation on the data according to the estimated error bit occurrence rate, wherein the decoding parameter corresponds to the precision of locating error bits in the decoding operation)

S1004: Step (whether the decoding is successful)

S1005: Step (output the data)

S1101: step (reading data from the first memory cell of the rewritable non-volatile memory module)

S1102: Step (perform a parity check operation on the data to obtain multiple syndromes)

S1103: Step (whether the decoding is successful)

S1104: Step (output the data)

S1105: Step (accumulate the syndromes to obtain the sum of syndromes)

S1106: step (evaluating the error bit occurrence rate of the data according to the syndrome sum total)

S1107: Step (using a decoding parameter to perform a decoding operation on the data according to the estimated error bit occurrence rate, wherein the decoding parameter corresponds to the precision of locating error bits in the decoding operation)

detailed description

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also called a control circuit). Generally, a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIG. 1 and FIG. 2 , the host system 11 generally includes a processor 111 , a random access memory (random access memory, RAM) 112 , a read only memory (read only memory, ROM) 113 and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 and the data transmission interface 114 are all connected to a system bus 110 .

In this exemplary embodiment, the host system 11 is connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 can store data into the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114 . In addition, the host system 11 is connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O devices 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 can be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114 , the motherboard 20 can be connected to the memory storage device 10 via a wired or wireless manner. The memory storage device 10 can be, for example, a flash drive 201 , a memory card 202 , a solid state drive (Solid State Drive, SSD) 203 or a wireless memory storage device 204 . The wireless memory storage device 204 can be, for example, a near field communication (Near Field Communication, NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device or a Bluetooth low energy memory storage device (for example, iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be connected to various I/O devices such as a Global Positioning System (GPS) module 205 , a network adapter 206 , a wireless transmission device 207 , a keyboard 208 , a screen 209 , and a speaker 210 through the system bus 110 . For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an exemplary embodiment, reference to a host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, however, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to FIG. 3 , in another exemplary embodiment, the host system 31 may also be a system such as a digital camera, video camera, communication device, audio player, video player or tablet computer, and the memory storage device 30 may be used for it. Various non-volatile memory storage devices such as a secure digital (Secure Digital, SD) card 32 , a compact flash (Compact Flash, CF) card 33 or an embedded storage device 34 . The embedded storage device 34 includes various types such as an embedded multimedia card (embedded MMC, eMMC) 341 and/or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device 342. The memory module is directly connected to the substrate of the host system. embedded storage device.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

In this exemplary embodiment, the connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 402 may also be a device conforming to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 Standard, Peripheral Component Interconnect Express (PCI Express) standard, Universal Serial Bus (Universal Serial Bus, USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard , Ultra High Speed-II (UHS-II) interface standard, Memory Stick (Memory Stick, MS) interface standard, Multi-Chip Package (Multi-Chip Package) interface standard, Multi Media Card (Multi Media Card, MMC) interface standard, eMMC interface standard, Universal Flash Storage (UFS) interface standard, eMCP interface standard, CF interface standard, Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 can be arranged outside a chip including the memory control circuit unit 404 .

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11. Fetch and erase operations.

The rewritable non-volatile memory module 406 is connected to the memory control circuit unit 404 and used for storing data written by the host system 11 . The rewritable non-volatile memory module 406 can be a single-level memory cell (Single Level Cell, SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in a memory cell), a multi-level memory cell (Multiple Level Cell) LevelCell, MLC) NAND flash memory module (that is, a flash memory module that can store 2 bits in a memory cell), and a triple-level memory cell (TripleLevel Cell, TLC) NAND flash memory module (that is, a memory cell that can store 3 bits) bit flash modules), other flash modules, or other memory modules with the same characteristics.

In this exemplary embodiment, the memory cells of the rewritable non-volatile memory module 406 constitute a plurality of physical programming units, and these physical programming units constitute a plurality of physical erasing units. Specifically, the memory cells on the same character line will form one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same character line can be at least classified into lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit is greater than that of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. unit reliability.

In this exemplary embodiment, the entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page (page) or an entity sector (sector). If the physical programming units are physical pages, these physical programming units usually include a data bit field and a redundancy (redundancy) bit field. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area is used for storing system data (eg, error correction code). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (byte, B). However, in other exemplary embodiments, the data bit area may also include 8, 16 or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains a minimum number of memory cells that are erased. For example, the physical erasing unit is a physical block.

In this exemplary embodiment, each memory cell in the rewritable non-volatile memory module 406 stores one or more bits by changing a voltage (also referred to as a threshold voltage hereinafter). Specifically, there is a charge trapping layer between the control gate of each memory cell and the channel. By applying a writing voltage to the control gate, the electron quantity of the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. The operation of changing the threshold voltage is also called "writing data into the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple storage states. Which storage state a memory cell belongs to can be determined by applying a read voltage, thereby obtaining one or more bits stored in the memory cell.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 , a memory interface 506 and an error checking and correction circuit 508 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404 . Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions will be executed to perform operations such as writing, reading, and erasing data. When describing the operation of the memory management circuit 502 below, it is equivalent to describing the operation of the memory control circuit unit 404 .

In this exemplary embodiment, the control commands of the memory management circuit 502 are implemented in the form of firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a ROM (not shown), and these control instructions are recorded into the ROM. When the memory storage device 10 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program code (for example, a system area in the memory module dedicated to storing system data) middle. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store in the rewritable non-volatile memory module The control instruction in 406 is loaded into the random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The memory cell management circuit is used for managing memory cells or groups thereof of the rewritable non-volatile memory module 406 . The memory writing circuit is used for issuing a write command sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory reading circuit is used to issue a read command sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasing circuit is used for issuing an erase command sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used for processing data to be written into the rewritable non-volatile memory module 406 and data read from the rewritable non-volatile memory module 406 . The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or scripts and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding write, read and Erase etc. In an exemplary embodiment, the memory management circuit 502 may also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct to perform corresponding operations.

In this exemplary embodiment, the memory management circuit 502 configures a plurality of logical units to map the physical erasing units in the rewritable non-volatile memory module 406 . One logical unit may refer to a logical address, a logical programming unit, a logical erasing unit, or consist of multiple continuous or discontinuous logical addresses. In addition, a logical unit can be mapped to one or more physical erased units.

In this exemplary embodiment, the memory management circuit 502 records the mapping relationship (also referred to as the logical-physical mapping relationship) between the logical unit and the physical erasing unit in at least one logical-physical mapping table. When the host system 11 intends to read data from or write data to the memory storage device 10 , the memory management circuit 502 can perform data access to the memory storage device 10 according to the logical-physical mapping table.

The host interface 504 is connected to the memory management circuit 502 and is used for receiving and identifying commands and data transmitted by the host system 11 . That is to say, the commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504 . In this exemplary embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with PATA standard, IEEE 1394 standard, PCI Express standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is connected to the memory management circuit 502 and used for accessing the rewritable non-volatile memory module 406 . That is to say, the data to be written into the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 via the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding command sequence. For example, these command sequences may include a write command sequence to write data, a read command sequence to read data, an erase command sequence to erase data, and to sequence of instructions to read voltage levels or perform garbage collection operations, etc.). These command sequences are, for example, generated by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506 . These instruction sequences may include one or more signals, or data on the bus. These signals or data may include script or program code. For example, in the read instruction sequence, information such as read identification code and memory address will be included.

The error checking and correction circuit 508 is connected to the memory management circuit 502 and configured to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 will generate a corresponding error correcting code (error correcting code, ECC) and/or or error checking code (error detecting code, EDC), and the memory management circuit 502 will write the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable non-volatile memory module 406 in. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, the error correction code and/or error check code corresponding to the data will be read at the same time, and the error check and correction circuit 508 will be based on The error correcting code and/or error checking code performs error checking and correcting operations on the read data.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 510 and a power management circuit 512 .

The buffer memory 510 is connected to the memory management circuit 502 and used for temporarily storing data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 512 is connected to the memory management circuit 502 and used for controlling the power of the memory storage device 10 .

In this exemplary embodiment, the ECC circuit 508 supports low-density parity-check (LDPC) codes. For example, the error checking and correcting circuit 508 may utilize low density parity check codes for encoding and decoding. In low-density parity-check codes, a check matrix (also known as a parity check matrix) is used to define effective codewords. The parity check matrix is denoted matrix H and a codeword V below. According to the following equation (1), if the multiplication of the parity check matrix H and the codeword V is a zero vector, it means that the codeword V is a valid codeword. where operator Represents matrix multiplication modulo 2. In other words, the null space of the matrix H includes all valid codewords. However, the present invention does not limit the content of the codeword V. For example, the codeword V may also include error-correcting codes or error-checking codes generated by arbitrary algorithms.

The dimension of the matrix H is k-by-n (k-by-n), and the dimension of the codeword V is 1-by-n. k and n are positive integers. The codeword V includes information bits and parity bits, that is, the codeword V can be expressed as [UP], where the vector U is composed of information bits, and the vector P is composed of parity bits. The dimensions of the vector U are 1-by-(n-k), and the dimensions of the vector P are 1-by-k. In a codeword, the parity bits are used to protect the information bits and can be considered as error correction codes or error check codes generated corresponding to the information bits. Wherein, protecting the information bit refers to maintaining the correctness of the information bit, for example. For example, when a piece of data is read from the rewritable non-volatile memory module 406, the parity bit in the data can be used to correct possible errors in the corresponding data.

In an exemplary embodiment, information bits and parity bits in a codeword are collectively referred to as data bits. For example, there are n data bits in the code word V, wherein the length of the information bit is (n-k) bits, and the length of the parity bit is k bits. Therefore, the code rate (coderate) of the codeword V is (n-k)/n.

Generally, a generator matrix (marked as G below) is used during encoding, so that the following equation (2) can be satisfied for any vector U. The dimension of the generated matrix G is (n-k)-times-n.

The codeword V generated by equation (2) is an effective codeword. Equation (2) can therefore be substituted into equation (1), thereby obtaining the following equation (3).

Since the vector U can be any vector, the following equation (4) must be satisfied. That is to say, after the parity check matrix H is determined, the corresponding generation matrix G can also be determined.

When decoding a codeword V, a parity check operation is first performed on the data bits in the codeword V, for example, the parity check matrix H is multiplied by the codeword V to generate a vector (marked as S below, as in the following equation (5) shown). If the vector S is a zero vector (that is, each element in the vector S is zero), it means that the decoding is successful and the codeword V can be output directly. If vector S is not a zero vector (ie, at least one element in vector S is zero), it means that there is at least one error in codeword V and codeword V is not a valid codeword.

The dimension of the vector S is k-by-1. Each element in the vector S is also called a syndrome. If the codeword V is not a valid codeword, the ECC circuit 508 performs a decoding operation in an attempt to correct the errors in the codeword V.

FIG. 6 is a schematic diagram of a parity check matrix displayed according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the dimension of the parity check matrix 600 is k-by-n. For example, k is 8 and n is 9. However, the present invention does not limit the positive integers k and n. Each row of the parity check matrix 600 also represents a constraint. Taking the first column of the parity check matrix 600 as an example, if a certain codeword is an effective codeword, then the 3rd, 5th, 8th and 9th bits in the codeword are modulo 2 (modulo- After the addition of 2), the bit "0" is obtained. Those of ordinary skill in the art should be able to understand how to use the parity check matrix 600 for encoding, so details will not be repeated here. In addition, the parity check matrix 600 is just an example matrix and is not intended to limit the present invention.

When the memory management circuit 502 is to store multiple bits into the rewritable non-volatile memory module 406, the error checking and correction circuit 508 generates Corresponding k parity bits. Next, the memory management circuit 502 writes the n bits (ie, data bits) into the rewritable non-volatile memory module 406 as a code word.

FIG. 7 is a schematic diagram showing the threshold voltage distribution of a memory cell according to an exemplary embodiment of the present invention.

Please refer to FIG. 7 , the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells. For example, FIG. 7 shows the threshold voltage of each memory cell in a physical programming unit. Assuming that state 710 corresponds to bit "1" (hereinafter also referred to as the first bit value) and state 720 corresponds to bit "0" (hereinafter also referred to as the second bit value), when the threshold voltage of a certain memory cell belongs to state 710 , the memory cell stores a bit “1”; on the contrary, if the threshold voltage of a certain memory cell belongs to the state 720, the memory cell stores a bit “0”. It should be noted that, in this exemplary embodiment, a state in the threshold voltage distribution corresponds to a bit value, and the threshold voltage distribution of the memory cell has two possible states. However, in other exemplary embodiments, each state in the threshold voltage distribution may also correspond to a plurality of bit values and the distribution of the threshold voltages of the memory cells may also have four, eight or any other states. In addition, the present invention does not limit the bits represented by each state. For example, in another exemplary embodiment of FIG. 7, state 710 may also correspond to bit "0", while state 720 may correspond to bit "1".

In this exemplary embodiment, when data is to be read from the rewritable nonvolatile memory module 406 , the memory management circuit 202 sends a read command sequence to the rewritable nonvolatile memory module 106 . The read instruction sequence is used to instruct the rewritable non-volatile memory module 406 to read multiple memory cells (hereinafter also referred to as first memory cells) in a physical programming unit to obtain data stored in the first memory cell The data. For example, according to the read command sequence, the rewritable non-volatile memory module 406 can use the read voltage 701 in FIG. 7 to read the first memory cell. If the threshold voltage of one of the first memory cells is lower than the read voltage 701 , the memory cell will be turned on, and the memory management circuit 502 will read a bit “1”. Conversely, if the threshold voltage of one of the first memory cells is greater than the read voltage 701 , the memory cell will not be turned on, and the memory management circuit 502 will read a bit “0”. In addition, in another exemplary embodiment, a read operation may also be to read memory cells in multiple physical programming units or a part of memory cells in one physical programming unit, which is not limited by the present invention.

In this exemplary embodiment, an overlapping region 730 is included between the state 710 and the state 720 . The area of the overlapping region 730 is directly related to the total number of memory cells whose threshold voltage falls within the overlapping region 730 in the first memory cell. Overlap region 730 indicates that there are some memory cells in the first memory cell that should store a bit "1" (belonging to state 710), but whose threshold voltage is greater than the applied read voltage 701; or, in the first memory cell There are some memory cells that should store bit "0" (of state 720 ), but whose threshold voltage is less than the applied read voltage 701 . In other words, in the data read by applying the read voltage 701 , some bits have errors.

Generally speaking, if the usage time of the first memory cell is very short (for example, the data stored in the first memory cell is not long) and/or the usage frequency of the first memory cell is very low (for example, the read Fetch count, write count, and/or erase count are not high), the area of the overlap region 730 is usually small, and the overlap region 730 may not even exist (ie, states 710 and 720 do not overlap). Or, if the memory storage device 10 has just been shipped from the factory, the overlapping area 730 usually does not exist. If the area of the overlapping region 730 is small, the error bits in the data read from the first memory cell by applying the read voltage 701 tend to be less.

However, as the use time and/or the use frequency of the rewritable non-volatile memory module 406 (or the first memory cell) increases, the area of the overlapping region 730 will gradually increase. For example, if the first memory cell is used for a long time (e.g., data is stored in the first memory cell for a long time) and/or the first memory cell is used frequently (e.g., the read count of the first memory cell , write count and/or erase count are high), the area of overlapping region 730 becomes larger (eg, state 710 and state 720 become flatter and/or state 710 and state 720 are closer to each other). If the area of the overlapping region 730 is large, the data read from the first memory cell by applying the read voltage 701 tends to have more error bits. In other words, the area of the overlapping region 730 is positively related to the occurrence probability of bit errors in the data read from the first memory cell (hereinafter also referred to as the bit error occurrence rate).

In this exemplary embodiment, after receiving the read data from the rewritable non-volatile memory module 406, the ECC circuit 508 performs a parity check operation to verify whether there is an error in the data. If it is determined that there is an error in the data, the ECC circuit 508 performs a decoding operation to try to correct the error in the data.

In this exemplary embodiment, the ECC circuit 508 performs an iteration decoding operation. An iterative decoding operation is used to decode a piece of data from the rewritable non-volatile memory module 406 . For example, one decoding unit in data is one codeword. In an iterative decoding operation, the parity check operation for checking the correctness of the data and the decoding operation for correcting errors in the data are repeatedly performed until successful decoding or the number of iterations reaches a predetermined number of times . If the number of iterations reaches the predetermined number, it means that the decoding fails, and the error checking and correction circuit 508 stops decoding. In addition, if it is determined that there is no error in a certain data through the parity check operation, the ECC circuit 508 will output the data.

FIG. 8 is a schematic diagram showing a parity check operation according to an exemplary embodiment of the present invention.

Please refer to FIG. 8, assuming that the datagram read from the first memory cell contains a codeword 801, then in the parity check operation, according to equation (5), the parity check matrix 800 will be multiplied by the codeword 801 and obtain the check Vector 802 (ie, vector S). Wherein, each bit in the codeword 801 corresponds to at least one element (ie, a syndrome) in the check vector 802 . For example, bit V ₀ in codeword 801 (corresponding to the first row in parity check matrix 800) is corresponding to syndrome S ₁ , syndrome S ₄ and syndrome S ₇ ; bit V ₁ ( Corresponding to the second row in the parity check matrix 800 ) is corresponding to syndrome S ₂ , syndrome S ₃ and syndrome S ₆ , and so on. If the bit V ₀ is an error bit, at least one of the syndrome S ₁ , the syndrome S ₄ and the syndrome S ₇ may be “1”. If the bit V ₁ is an error bit, at least one of the syndrome S ₂ , syndrome S ₃ and syndrome S ₆ may be “1”, and so on.

In other words, if the syndromes S ₀ -S ₇ are all “0”, it means that there may be no error bits in the codeword 801 , so the error checking and correction circuit 508 can directly output the codeword 801 . However, if there is at least one erroneous bit in the codeword 801, at least one of the syndromes S ₀ -S ₇ may be “1”, and the ECC circuit 508 performs a decoding on the codeword 801 operate.

In the exemplary embodiment, the ECC circuit 508 supports one or more decoding algorithms. For example, the error checking and correcting circuit 508 may support at least one of decoding algorithms such as Bit-Flipping algorithm, Min-Sum algorithm and Sum-Product algorithm, and The types of decoding algorithms that can be employed are not limited to the above. After determining that there are errors in the data, the ECC circuit 508 performs a decoding operation based on a decoding algorithm. In addition, the two consecutive decoding operations may be performed based on the same or different decoding algorithms.

In this exemplary embodiment, before performing a decoding operation on a certain data, the memory management circuit 502 evaluates the bit error rate of the data. Wherein, if the estimated occurrence rate of error bits is higher, it means that the probability of including error bits in the data is higher and/or the total number of error bits in the data may also be larger. According to the estimated erroneous bit occurrence rate, the ECC circuit 508 uses a decoding parameter to perform a decoding operation on the data. Wherein, the decoding parameter is used to adjust the strict level of error detection and correction circuit 508 in locating error bits in the decoding operation.

In this exemplary embodiment, the strictness is related to the judgment standard of the error bit. For example, if the erroneous bits are located based on a higher degree of precision, the error checking and correction circuit 508 has stricter criteria for determining the erroneous bits in the data, so that the probability of any bit in the data being misjudged as an erroneous bit can be reduced. Correspondingly, however, the number of erroneous bits to be corrected in one decoding operation may also be reduced, so that the ECC circuit 508 may need to perform more decoding operations to correct all errors in the data. In other words, if the erroneous bits are located based on higher precision, the decoding operations to be performed may increase, but the advantage is that the probability of misjudging some bits in the data as erroneous bits can be reduced. In some cases (eg, when the estimated data has a high occurrence rate of erroneous bits), locating erroneous bits based on a higher degree of rigor in the decoding operation can improve the decoding efficiency of the data.

On the other hand, if the erroneous bits are located based on a lower degree of rigor, the error checking and correction circuit 508 has a looser criterion for judging the erroneous bits in the data, so that the bits that are identified as erroneous bits and corrected in one decoding operation The total number may be higher. Correspondingly, however, the misjudgment rate of erroneous bits may also increase, so that the error checking and correction circuit 508 may repeatedly change the bit value of the same bit in the data in multiple consecutive decoding operations. In other words, if erroneous bits are located based on a lower degree of rigor, some bits in the data may be repeatedly corrected in different decoding operations, but the advantage is that more errors can be corrected in the same decoding operation. In some cases (eg, when the estimated data has a low incidence of error bits), locating error bits based on a lower degree of rigor in the decoding operation can improve the decoding efficiency of the data.

Generally speaking, if there are many erroneous bits in the data to be decoded (for example, the total number of erroneous bits exceeds a preset value), the decoding success rate of each decoding operation is limited, and each bit in the data is within a Whether the decoding operation is correctly corrected depends on whether the decoding of the data was successful, the number of times the decoding operation was performed on the data, and/or the time required to complete the decoding. Therefore, in this exemplary embodiment, if the bit error occurrence rate of the evaluated data is relatively high, the error checking and correcting circuit 508 performs a decoding operation on the data using decoding parameters corresponding to a higher degree of precision.

On the other hand, if there are fewer error bits in the data to be decoded (for example, the total number of error bits is less than a preset value), each decoding operation has a higher decoding success rate, and any decoding Any code operation has the potential to correct all or most of the erroneous bits in the data. Therefore, in this exemplary embodiment, if the bit error occurrence rate of the evaluated data is low, the error checking and correction circuit 508 performs a decoding operation on the data using decoding parameters corresponding to a lower degree of precision. In other words, the degree of precision with which erroneous bits are located in a decoding operation performed on certain data is positively correlated with the estimated occurrence rate of erroneous bits for this data. Thereby, no matter whether there are many or few error bits in the data to be decoded, there is a higher probability to speed up the convergence of the error bits and improve the decoding efficiency.

In this exemplary embodiment, the ECC circuit 508 is preset to perform the iterative decoding operation according to the bit flipping algorithm. In this iterative decoding operation, each decoding operation attempts to correct (hereinafter also referred to as flipping) at least one bit in the data. For example, the error checking and correcting circuit 508 identifies bits in the data that need to be flipped (ie, erroneous bits) based on a flipping threshold. That is to say, in this exemplary embodiment, the decoding parameter used by the ECC circuit 508 refers to an inversion threshold corresponding to the bit inversion algorithm.

Referring to FIG. 8 , in a decoding operation, the ECC circuit 508 calculates the check weight of each bit in the codeword 801 according to the parity check matrix 800 and the check vector 802 . For example, the ECC circuit 508 will add the syndromes corresponding to the same bit in the codeword 801 to obtain the check weight of the bit. As shown in Figure 8, the verification weight of bit V ₀ is equal to the addition of syndrome S ₁ , syndrome S ₄ and syndrome S ₇ ; the verification weight of bit V ₁ is equal to syndrome S ₂ , syndrome S 2 The addition of syndrome S ₃ and syndrome S ₆ , and so on. It should be noted that the addition to the syndromes S ₀ -S ₇ here is a general addition, not a modulo 2 addition. For example, the error checking and correcting circuit 208 can obtain the check weight of each bit in the codeword 801 through the following equation (6). Wherein, each element in the vector f can be used to represent the verification weight of each bit in the codeword.

f=S ^T ×H...(6)

After selecting a decoding parameter (ie, the inversion threshold), the ECC circuit 508 corrects all or at least a part of the bits in the codeword 801 whose check weight is greater than the decoding parameter. For example, if the decoding parameter is “1” and the check weights of bit V ₁ , bit V ₃ and bit V ₅ in the codeword 801 are all greater than “1”, the error checking and correction circuit 508 will During the operation, the three bits V ₁ , V ₃ and V ₅ are flipped synchronously. Wherein, flipping a certain bit refers to flipping the bit value of this bit from "1" to "0", or from "0" to "1". Alternatively, if the decoding parameter is "2" and only the check weights of bit _V3 and bit _V5 in the codeword 801 are greater than "2", the error checking and correction circuit 508 reverses the 2 in this decoding operation. Ones bit V ₃ and bit V ₅ . For example, the values of bit _V3 and bit _V5 are respectively flipped from "1" to "0", or from "0" to "1".

In this exemplary embodiment, the decoding parameter (for example, the flipping threshold) used in a certain decoding operation is positively related to the degree of precision used to locate error bits in the decoding operation. From another point of view, the decoding parameter (for example, the flipping threshold) used in a certain decoding operation is positively related to the estimated bit error rate. If the estimated erroneous bit occurrence rate is higher, a larger decoding parameter will be used in subsequent decoding operations. For example, in an exemplary embodiment of FIG. 8, if the estimated error bit occurrence rate is high (eg, higher than a preset standard), the error checking and correction circuit 508 temporarily uses "2" as the toggle threshold. Conversely, if the estimated bit error rate is low, smaller decoding parameters will be used in subsequent decoding operations. For example, in an exemplary embodiment of FIG. 8 , if the estimated error bit occurrence rate is low (eg, lower than a preset standard), the error checking and correction circuit 508 temporarily uses "1" as the toggle threshold. Thus, in an exemplary embodiment, if the estimated error bit occurrence rate is high, the total number of flipped bits in the same decoding operation may be less; if the estimated error bit occurrence rate is low, the The total number of flipped bits in the same decoding operation may be larger. However, in fact, the total number of flipped bits in each decoding operation may also increase or decrease with the channel state of the first memory cell, which is not limited by the present invention.

In an exemplary embodiment, if the channel state of the first memory cell (or the physical programming unit or the physical erasing unit including the first memory cell) is better, the estimated value of the data read from the first memory cell is The lower the bit error rate will be. Conversely, if the channel state of the first memory cell (or the physical programming unit or the physical erasing unit including the first memory cell) is worse, the estimated error bit occurrence rate for the data read from the first memory cell will be higher.

In an exemplary embodiment, the memory management circuit 502 obtains the threshold voltage distribution of the first memory cell and evaluates the bit error occurrence rate of the data read from the first memory cell accordingly. Taking FIG. 7 as an example, the memory management circuit 502 can evaluate the bit error occurrence rate of the data read from the first memory cell according to the total number of memory cells corresponding to the overlapping region 730 between the state 710 and the state 720 . Wherein, the area of the overlapping region 730 is positively related to the threshold voltage of the total number of memory cells contained in the overlapping region 730 . For example, the memory management circuit 502 can query a look-up table to obtain the bit error rate of the data according to the area of the overlapping region 730 and/or the total number of memory cells whose threshold voltage is included in the overlapping region 730 . Alternatively, the memory management circuit 502 can also input the area of the overlapping region 730 and/or the threshold voltage of the total number of memory cells included in the overlapping region 730 into an algorithm and use the output of the algorithm as the bit error rate of the data.

In an exemplary embodiment, if a certain physical programming unit and another physical programming unit belong to the same physical erasing unit, there is a high probability that the data read from these two physical programming units will have the same or Similar bit error rates. Therefore, in an exemplary embodiment, assuming that the physical programming unit to which the first memory cell belongs belongs to a certain physical erasing unit in the rewritable non-volatile memory module 406, the memory management circuit 502 will store the The total number of erroneous bits obtained through successful decoding in data read by another physical programming unit in the division unit. According to the total number, the memory management circuit 502 can estimate the total number of possible error bits and/or the corresponding occurrence rate of error bits in the data read from the first memory cell.

In an exemplary embodiment, the memory management circuit 502 can also use any information related to the degree of wear of the first memory cell (for example, the storage time of data in the first memory cell, the read count of the first memory cell, the write count of the first memory cell) count and/or erase count, etc.) to evaluate the error bit occurrence rate of the data read from the first memory cell. For example, corresponding to different read counts, write counts and/or erase counts, the memory management circuit 502 can look up a table or use a specific algorithm to obtain the corresponding error bit occurrence rate.

In this exemplary embodiment, the memory management circuit 502 directly uses the execution result of the parity check operation to evaluate the bit error occurrence rate of the data to be decoded. For example, in an exemplary embodiment of FIG. 8 , the memory management circuit 502 accumulates the syndromes S ₀ -S ₇ in the check vector 802 to obtain a syndrome sum. Here, accumulation refers to general addition, not modulo-2 addition. The syndrome sum can be used to indicate how many "1"s (or how many "0s") there are in the syndromes S ₀ -S ₇ . For example, if there are 3 "1"s in the syndromes S ₀ -S ₇ , the sum of the syndromes will be "3". Or, if there are 7 "1"s among the syndromes S ₀ -S ₇ , the sum of the syndromes will be "7". Generally speaking, if there are more error bits in the codeword 801, there will be more "1"s in the syndromes S ₀ -S ₇ , and the larger the syndrome sum will be. If the number of error bits in the codeword 801 is less, the number of “1”s in the syndromes S ₀ -S ₇ will be less, and the sum of the syndromes will be smaller. Therefore, the estimated erroneous bit occurrence rate will be positively correlated with this syndrome sum.

It is worth mentioning that the present invention does not limit the form of the estimated error bit occurrence rate. For example, the error bit occurrence rate of a certain data can be the probability that at least one bit in the data is an error bit, the bit error rate of the data as a whole, the total number of error bits in the data, the loss degree of the first memory cell (for example, the first At least one of the memory cell read count, write count and/or erase count, etc.) and the sum of the syndromes or other numerical values related to the occurrence rate of the error bit is expressed or used as an evaluation basis.

In this exemplary embodiment, the memory management circuit 502 queries a look-up table to obtain decoding parameters used in subsequent decoding operations according to the syndrome sum and other values related to the bit error occurrence rate of the data. Alternatively, the memory management circuit 502 may also input values related to the error bit occurrence rate of the data, such as the syndrome sum, into an algorithm and use the output of the algorithm as a decoding parameter used in subsequent decoding operations. For example, the algorithm may include judging whether the sum of syndromes and other values related to the bit error rate of data is greater than or smaller than a threshold value, and judging the sum of syndromes and other values related to the bit error rate of data Which value range does it fall in? Or substitute the syndrome sum and other values related to the error bit occurrence rate of the data into a specific equation to output corresponding decoding parameters.

In an exemplary embodiment, the operation of obtaining the decoding parameters according to the syndrome sum and other values related to the error bit occurrence rate of the data can also be performed by the hardware circuit of the error checking and correcting circuit 508 itself, so as to speed up the overall decoding speed.

In an exemplary embodiment, if the same iterative decoding operation includes a plurality of consecutive decoding operations, the error rate of the data to be decoded may change during these decoding operations, and at least The decoding parameters used by some decoding operations are also adaptively changed. Thereby, even if the decoding algorithm is not changed, the precision for locating error bits in the decoding operation can be properly adjusted as the errors in the data are gradually corrected, thereby improving the decoding efficiency. For example, when a decoding operation is first performed on a certain data, the error rate corresponding to the data is relatively high (for example, there are many errors in the data), the error checking and correction circuit 508 will first use a higher stringency The decoding operation is performed at a high degree, so as to avoid errors in the data diverging due to one decoding operation containing too many misjudgments. However, as the errors in the data are gradually corrected, the total number of erroneous bits in the data will gradually decrease, and the occurrence rate of erroneous bits in the data will decrease. Therefore, in subsequent decoding operations, the error checking and correction circuit 508 will use a lower level of precision instead, so as to improve the overall decoding without greatly reducing the decoding success rate of each decoding operation. speed.

For example, assume that after evaluating the error bit occurrence rate of the data read from the first memory cell, the error checking and correction circuit 508 uses a certain decoding parameter (hereinafter also referred to as the first decoding parameter) to execute A decoding operation (hereinafter also referred to as a first decoding operation). Wherein, the first decoding parameter corresponds to the precision of locating error bits in the first decoding operation. Then, the memory management circuit 502 or the ECC circuit 508 determines whether the first decoding operation fails. If the first decoding operation fails (that is, there are still errors in the data), the memory management circuit 502 or the error checking and correction circuit 508 will re-evaluate the error rate of the data to be decoded according to the execution result of the first decoding operation. According to the re-evaluated error bit occurrence rate, the ECC circuit 508 uses another decoding parameter (hereinafter also referred to as the second decoding parameter) to perform another decoding operation (hereinafter also referred to as the second decoding parameter) on the data to be decoded. Two decoding operations). Wherein the second decoding parameter corresponds to the precision of locating error bits in the second decoding operation. Depending on the re-evaluated bit error rate, the second decoding parameter may be different or the same as the first decoding parameter. In particular, if the second decoding parameter is different from the first decoding parameter, the degree of precision for locating error bits in the first decoding operation and the second decoding operation will be different.

In an exemplary embodiment, the ECC circuit 508 can also change the used decoding algorithm. For example, if all the errors in the data cannot be corrected after performing a preset number of decoding operations on a certain data based on the bit-flip algorithm, the error checking and correction circuit 508 may switch to using the minimum sum algorithm, the sum product algorithm, etc. , to continue performing more decoding operations on this data. Alternatively, the error checking and correcting circuit 508 may also be preset to use decoding algorithms such as minimum sum algorithm and sum product algorithm to perform decoding operations, which is not limited by the present invention. In addition, although the above exemplary embodiment uses the flipping threshold corresponding to the bit flipping algorithm as an example of the decoding parameter, in another exemplary embodiment, if the error checking and correcting circuit 508 uses the minimum sum algorithm, sum product Algorithm and other decoding algorithms to perform the decoding operation, the error checking and correction circuit 508 may also use other types of decoding parameters to adjust the precision of locating error bits in the corresponding decoding operation. In other words, no matter what kind of decoding algorithm is used to perform the decoding operation, as long as a certain parameter can be used to adjust or control the precision of locating error bits in a certain decoding operation, this parameter can be regarded as the above-mentioned decoding parameter And can be selectively used according to the estimated error bit occurrence rate.

FIG. 9 is a flowchart of a decoding method according to an exemplary embodiment of the present invention.

Please refer to FIG. 9 , in step S901 , read data from the first memory cell of the rewritable non-volatile memory module. In step S902, the bit error occurrence rate of the data (ie, the data to be decoded) is evaluated. In step S903, a decoding operation is performed on the data (ie, the data to be decoded) using a decoding parameter according to the estimated error bit occurrence rate, wherein the decoding parameter corresponds to the decoding operation The rigor of locating error bits in .

FIG. 10 is a flowchart of a decoding method according to another exemplary embodiment of the present invention.

Please refer to FIG. 10 , in step S1001 , read data from the first memory cell of the rewritable non-volatile memory module. In step S1002, the bit error occurrence rate of the data (ie, the data to be decoded) is evaluated. In step S1003, a first decoding operation is performed on the data using a first decoding parameter according to the estimated error bit occurrence rate, wherein the first decoding parameter corresponds to the location error bit in the first decoding operation Rigor. In step S1004, it is judged whether the decoding is successful. If so, in step S1005, output the data that has been successfully decoded. If not (that is, the decoding fails), return to step S1002, and re-evaluate the bit error occurrence rate of the data to be decoded according to the execution result of the previous decoding operation. Then, in step S1003, a second decoding operation is performed on the data (that is, data to be decoded) using a second decoding parameter according to the re-evaluated bit error rate, wherein the second decoding parameter corresponds to the The degree of precision with which erroneous bits are located in the second decoding operation.

FIG. 11 is a flowchart of a decoding method according to another exemplary embodiment of the present invention.

Please refer to FIG. 11 , in step S1101 , read data from the first memory cell of the rewritable non-volatile memory module. In step S1102, a parity check operation is performed on the data (ie, the data to be decoded) to obtain a plurality of syndromes. In step S1103, it is judged whether the decoding is successful according to the acquired syndrome. If the decoding is successful, in step S1104, the data of successful decoding is output. If not (that is, the decoding has not been successful), in step S1105, the syndromes are accumulated to obtain a syndrome sum. In step S1106, the bit error occurrence rate of the data (ie, the data to be decoded) is evaluated according to the syndrome sum. In step S1107, a first decoding operation is performed on the data (that is, data to be decoded) using a first decoding parameter according to the estimated error bit occurrence rate, wherein the first decoding parameter corresponds to the The degree of rigor with which erroneous bits are located during the decode operation. After the first decoding operation is completed, return to step S1102, and perform a parity check operation on the data (ie, the data to be decoded) again to obtain a plurality of syndromes. In step S1103, it is judged whether the decoding is successful according to the retrieved syndrome. If yes, output the decoded data successfully. If not (that is, the decoding fails), in step S1105, the acquired syndromes are accumulated again to obtain a syndrome sum. In step S1106, the bit error occurrence rate of the data (that is, the data to be decoded) is evaluated according to the recalculated syndrome sum. In step S1107, a second decoding operation is performed on the data (that is, data to be decoded) using a second decoding parameter according to the estimated error bit occurrence rate, wherein the second decoding parameter corresponds to the second The degree of rigor with which erroneous bits are located during the decode operation. In an exemplary embodiment, step S1102, step S1103, and steps S1105-S1107 are repeatedly executed until successful decoding (that is, entering step S1104) or the total number of executed decoding operations (ie, the number of iterations) reaches a predetermined number of times. For example, if the number of iterations reaches the predetermined number, the decoding operation will be stopped.

However, each step in FIG. 9 to FIG. 11 has been described in detail above, and will not be repeated here. It should be noted that each step in FIG. 9 to FIG. 11 can be implemented as a plurality of program codes or circuits, which is not limited in the present invention. In addition, the methods in FIG. 9 to FIG. 11 can be used together with the above exemplary embodiments, or can be used alone, which is not limited by the present invention.

To sum up, according to the bit error occurrence rate of the data to be decoded, the error checking and correcting circuit can flexibly perform a corresponding decoding operation based on a specific decoding parameter. Wherein, the decoding parameter corresponds to the precision of locating error bits in the corresponding decoding operation. Thereby, a balance can be achieved between improving the decoding success rate of each decoding operation and increasing the overall decoding speed, thereby improving the decoding efficiency of the memory storage device.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (24)

1. A decoding method for a rewritable non-volatile memory module comprising a plurality of memory cells, wherein the decoding method comprises: reading data from a plurality of first memory cells in the plurality of memory cells; evaluating a bit error rate of the data before performing a first decoding operation on the data; and performing said first decoding operation on said data using first decoding parameters based on the estimated error bit occurrence rate, Wherein the first decoding parameter corresponds to the degree of precision in locating erroneous bits in the first decoding operation. 2. The decoding method according to claim 1, wherein the step of evaluating the error bit occurrence rate of the data comprises: obtaining a threshold voltage distribution of the plurality of first memory cells, wherein the threshold voltage distribution includes a first state and a second state, wherein the first state corresponds to a first bit value, wherein the second state corresponds to a second bit value, wherein said first bit value is different from said second bit value; and The error bit occurrence rate of the data is estimated according to the total number of memory cells corresponding to the overlapping area between the first state and the second state. 3. The decoding method according to claim 1, wherein the step of evaluating the error bit occurrence rate of the data comprises: performing a parity check operation on the data to obtain a plurality of syndromes; accumulating the plurality of syndromes to obtain a syndrome sum; and evaluating said error bit occurrence rate of said data based on said syndrome sum, Wherein the estimated error bit occurrence rate is positively correlated with the syndrome sum. 4. The decoding method according to claim 1, wherein the strictness is positively correlated with the estimated bit error rate. 5. The decoding method according to claim 1, characterized in that, the rigor is positively related to the first decoding parameter. 6. The decoding method according to claim 5, wherein the first decoding parameter is positively correlated with the estimated bit error rate. 7. The decoding method according to claim 6, wherein the first decoding parameter is a flipping threshold, wherein the first decoding operation comprises: obtaining a check weight corresponding to each bit in the data; and Inverting at least one bit in the data whose verification weight is greater than the inversion threshold. 8. The decoding method according to claim 1, further comprising: judging whether the first decoding operation fails; If the first decoding operation fails, re-evaluating the error bit occurrence rate of the data according to an execution result of the first decoding operation; and performing a second decoding operation on the data using a second decoding parameter according to the re-evaluated bit error rate, Wherein the second decoding parameter corresponds to the precision of locating error bits in the second decoding operation. 9. A memory storage device, comprising: connecting the interface unit for connecting to the host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of memory cells; and a memory control circuit unit connected to the connection interface unit and the rewritable non-volatile memory module, Wherein the memory control circuit unit is used to send a read instruction sequence to instruct to read data from a plurality of first memory cells in the plurality of memory cells, Wherein, before performing a first decoding operation on the data, the memory control circuit unit is further configured to evaluate an error bit occurrence rate of the data, wherein the memory control circuit unit is further configured to use a first decoding parameter to perform the first decoding operation on the data according to the estimated bit error rate, Wherein the first decoding parameter corresponds to the degree of precision in locating erroneous bits in the first decoding operation. 10. The memory storage device according to claim 9, wherein the operation of the memory control circuit unit evaluating the error bit occurrence rate of the data comprises: obtaining a threshold voltage distribution of the plurality of first memory cells, wherein the threshold voltage distribution includes a first state and a second state, wherein the first state corresponds to a first bit value, wherein the second state corresponds to a second bit value, wherein said first bit value is different from said second bit value; and The error bit occurrence rate of the data is estimated according to the total number of memory cells corresponding to the overlapping area between the first state and the second state. 11. The memory storage device according to claim 9, wherein the operation of the memory control circuit unit evaluating the error bit occurrence rate of the data comprises: performing a parity check operation on the data to obtain a plurality of syndromes; accumulating the plurality of syndromes to obtain a syndrome sum; and evaluating said error bit occurrence rate of said data based on said syndrome sum, Wherein the estimated error bit occurrence rate is positively correlated with the syndrome sum. 12. The memory storage device of claim 9, wherein the stringency is positively correlated with the estimated bit error rate. 13. The memory storage device according to claim 9, wherein the strictness is positively related to the first decoding parameter. 14. The memory storage device according to claim 13, wherein the first decoding parameter is positively correlated with the estimated bit error rate. 15. The memory storage device according to claim 14, wherein the first decoding parameter is an inversion threshold, wherein the first decoding operation comprises: obtaining a check weight corresponding to each bit in the data; and Inverting at least one bit in the data whose verification weight is greater than the inversion threshold. 16. The memory storage device according to claim 9, wherein the memory control circuit unit is further used to determine whether the first decoding operation fails, Wherein if the first decoding operation fails, the memory control circuit unit is further configured to re-evaluate the error bit occurrence rate of the data according to an execution result of the first decoding operation, wherein the memory control circuit unit is further configured to use a second decoding parameter to perform a second decoding operation on the data according to the re-evaluated error bit occurrence rate, Wherein the second decoding parameter corresponds to the precision of locating error bits in the second decoding operation. 17. A memory control circuit unit for controlling a rewritable non-volatile memory module, characterized in that the rewritable non-volatile memory module includes a plurality of memory cells, and the memory control circuit unit includes : a host interface for connecting to a host system; a memory interface for connecting to the rewritable non-volatile memory module; error checking and correction circuitry; and a memory management circuit connected to said host interface, said memory interface and said error checking and correction circuit, Wherein the memory management circuit is used to send a read command sequence to instruct to read data from a plurality of first memory cells in the plurality of memory cells, Wherein, before performing the first decoding operation on the data, the memory management circuit is further used to evaluate the bit error rate of the data, wherein the error checking and correction circuit is configured to perform the first decoding operation on the data using first decoding parameters according to the estimated error bit occurrence rate, Wherein the first decoding parameter corresponds to the degree of precision in locating erroneous bits in the first decoding operation. 18. The memory control circuit unit according to claim 17, wherein the operation of the memory management circuit evaluating the error bit occurrence rate of the data comprises: obtaining a threshold voltage distribution of the plurality of first memory cells, wherein the threshold voltage distribution includes a first state and a second state, wherein the first state corresponds to a first bit value, wherein the second state corresponds to a second bit value, wherein said first bit value is different from said second bit value; and The error bit occurrence rate of the data is estimated according to the total number of memory cells corresponding to the overlapping area between the first state and the second state. 19. The memory control circuit unit according to claim 17, wherein the operation of the memory management circuit evaluating the error bit occurrence rate of the data comprises: performing a parity check operation on the data to obtain a plurality of syndromes; accumulating the plurality of syndromes to obtain a syndrome sum; and evaluating said error bit occurrence rate of said data based on said syndrome sum, Wherein the estimated error bit occurrence rate is positively correlated with the syndrome sum. 20. The memory control circuit unit of claim 17, wherein the stringency is positively related to the estimated error bit occurrence rate. 21. The memory control circuit unit according to claim 17, wherein the strictness is positively related to the first decoding parameter. 22. The memory control circuit unit according to claim 21, wherein the first decoding parameter is positively correlated with the estimated bit error rate. 23. The memory control circuit unit according to claim 22, wherein the first decoding parameter is an inversion threshold, wherein the first decoding operation comprises: obtaining a check weight corresponding to each bit in the data; and Inverting at least one bit in the data whose verification weight is greater than the inversion threshold. 24. The memory control circuit unit according to claim 17, wherein the memory management circuit is further used to determine whether the first decoding operation fails, Wherein if the first decoding operation fails, the memory management circuit is further configured to re-evaluate the error bit occurrence rate of the data according to an execution result of the first decoding operation, wherein the error checking and correcting circuit is further configured to use a second decoding parameter to perform a second decoding operation on the data according to the re-evaluated error bit occurrence rate, Wherein the second decoding parameter corresponds to the precision of locating error bits in the second decoding operation.