CN107301444A - A kind of ultrahigh frequency RFID coding circuit - Google Patents

Abstract

The invention discloses a kind of ultrahigh frequency RFID coding circuit structure, the circuit structure includes asynchronous process circuit and synchronous coding circuit, wherein synchronous coding circuit is made up of asynchronous/synchronous interface, clock generation circuit and coding circuit, asynchronous/synchronous interface is used for position to be encoded and its request signal and coding-control and its request signal for receiving the generation of asynchronous process circuit, and feeds back the answer signal of these requests；Clock generation circuit is used to produce encoded clock；Coding circuit is made up of FM0 coding circuits and Miller coding circuits, according to the position to be encoded of asynchronous process circuit output and coding control signal, under the encoded clock control that clock generation circuit is generated, and is treated bits of coded and is carried out FM0 codings or Miller codings.The present invention treats bits of coded using asynchronous handshake mechanism and is controlled, and instead of the buffer and state machine in pure synchronous coding circuit, the area and power consumption that can effectively save needed for encoding.

Description

A UHF RFID Encoding Circuit

technical field

The invention relates to an ultra-high frequency RFID encoding circuit, which belongs to the technical field of communication.

Background technique

Due to the need for low power consumption in many fields, asynchronous circuits have received more attention. Asynchronous circuits use internal and external events to obtain system state, and use clockless handshaking as a communication mechanism.

RFID is a non-contact automatic identification technology, which uses radio frequency signals and their spatial coupling and transmission characteristics to realize automatic identification of stationary or moving items. RFID can be used to track and manage management objects in many fields. It has the characteristics of high accuracy, long reading distance, large amount of stored data, and strong durability. It is widely used in product production, logistics, sales and other links. The passive working characteristics of RFID make it more susceptible to external influences, and the energy derived from electromagnetic waves per unit space is limited, so low-power RFID can improve the working distance of a single chip and the group read response efficiency of multiple chips.

RFID digital logic has three obvious stages of decoding, processing and encoding, and the sequential execution of each stage is very suitable for event-driven asynchronous circuit implementation.

If the design of UHF RFID digital logic is completely implemented in an asynchronous manner, there will be the following problems: because the RFID encoding stage needs to divide the clock frequency, and the asynchronous circuit uses an event-driven handshake mechanism to eliminate the global clock with a constant period. , so asynchronous circuits are not suitable for clock frequency division.

Contents of the invention

The invention proposes a UHF RFID encoding circuit structure with an asynchronous/synchronous interface, and uses design methods such as an asynchronous handshake mechanism, a gating clock, and an asynchronous counter to reduce the area and power consumption of the UHF RFID encoding circuit.

The UHF RFID encoding circuit structure proposed by the present invention includes an asynchronous processing circuit and a synchronous encoding circuit, and an asynchronous processing circuit for outputting bits to be encoded and encoding control signals, and sending corresponding request signals; a synchronous encoding circuit for completing Return the response signal after encoding; the synchronous encoding circuit is composed of three parts: asynchronous/synchronous interface, clock generation circuit and encoding (FM0/Miller) circuit. Among them: the asynchronous/synchronous interface receives the bit to be encoded and its request signal and encoding control and its request signal generated by the asynchronous processing circuit, and feeds back the response signal of these requests. According to the frequency division coefficient output by the synchronous timing circuit, the clock generation circuit is 1.28 The MHz source clock is divided by 2 to 32 to generate a clock for encoding. The power consumption of the synchronous encoding circuit can be effectively reduced by adopting the asynchronous counter technology and using the enable signal output by the asynchronous processing circuit to gate the encoding clock. The encoding (FM0/Miller) circuit is composed of an FM0 encoding circuit and a Miller encoding circuit. According to the bit to be encoded and the encoding control signal output by the asynchronous processing circuit, under the control of the encoding clock generated by the clock generation circuit, FM0 encoding or Miller encoding is performed on the bit to be encoded. Both FM0 encoding and Miller encoding are realized by XOR operation of two signals triggered by rising edge and falling edge.

The invention provides a UHF RFID encoding circuit with an asynchronous/synchronous interface, the asynchronous/synchronous interface responds to the request of the bit to be encoded only after FM0 encoding or Miller encoding is performed on the bit to be encoded; Simple delay processing can respond to the request of the coded control signal. Compared with the general asynchronous/synchronous interface implementation, the present invention is based on the asynchronous handshake mechanism, and can realize the bit-by-bit output of the bit to be encoded through the asynchronous/synchronous interface, thereby replacing the buffer and state machine in the pure synchronous encoding circuit, without using Complex finite state machines or timing control components generate response signals, which can effectively reduce the area and power consumption of asynchronous/synchronous interface circuits. The invention has the characteristics of simple structure, small area and low power consumption.

Description of drawings

Fig. 1 UHF RFID encoding circuit structural block diagram of the present invention;

Figure 2last_dat_ack and tx_dat_ack generation circuit;

Figure 3fm0_v_ack, tx_m_ack, tx_trext_ack and tx_en_ack generation circuit;

Fig. 4 timing diagram of asynchronous/synchronous interface circuit;

Figure 5 clock generation circuit timing diagram;

Figure 6 Encoding (FM0/Miller) circuit timing diagram.

detailed description

Using the four-phase handshake protocol, taking FM0 encoding as an example, the following is a combination of the accompanying drawings for the realization of the structure of the proposed encoding circuit that conforms to the UHF RFID protocol, and the specific implementation steps are given.

UHF RFID digital logic is realized by combining asynchronous and synchronous design methods, and the structure of the encoding circuit with asynchronous/synchronous interface is shown in Figure 1. The asynchronous processing circuit outputs the bit to be encoded and the encoding control signal (indicated by dat in the figure), and sends a corresponding request signal (indicated by req in the figure), and the synchronous encoding circuit returns a response signal after completing the encoding (indicated by ack in the figure). Indicates), the corresponding interface timing is shown in Figure 4.

last_dat_req and last_dat_ack are a pair of synchronous handshake signals (only request and response, but no data transmission), which identify the last bit to be encoded decoded by the asynchronous processing circuit. last_dat_req changes from low to high after the to-be-encoded bit (tx_dat) before "DUMMY 1" is valid, and last_dat_ack is generated after the encoding completion signal (tx_dat_done) output by the encoding circuit is strobed and ANDed with its request signal (as shown in Figure 2 As shown), the change of last_dat_ack from low to high causes its request signal last_dat_req to change from high to low, and finally causes last_dat_ack to change from high to low, thus completing the four-phase handshake communication.

When the encoding enable signal (tx_en) is high, tx_dat sends a corresponding request after it is valid, and the encoding circuit responds to the request after completing FM0 encoding or Miller encoding, thereby controlling the bit-by-bit output of the bit to be encoded. Since tx_dat needs to be continuously output bit by bit, its response signal (tx_dat_ack) is generated by the encoding clock or counting completion signal. For FM0 encoding, directly use the encoding clock (clk_enc) to generate after gating and ANDing with its request signal (as shown in Figure 2).

fm0_v represents the indication signal of v in the FM0 code prefix, and its request signal (fm0_v_req) changes from low to high after fm0_v is valid, and the response signal (fm0_v_ack) of fm0_v only needs to be processed by a simple delay (caching) (as shown in the figure 3).

tx_m determines the encoding mode used, and tx_trext indicates the format of the encoding prefix. For the tx_m, tx_trext, and tx_en signals, the request and response only need to be changed once during initialization, and then the values of these coded control signals can be used directly, and the response signals only need to be processed by a simple delay (caching) (as shown in the figure 3). tx_m and tx_trext are valid only at the end of decoding (T1), and tx_en needs to be assigned in the initialization phase (initial value is 0).

The timing of the clock generation circuit is shown in Figure 5. The 1.28MHz source clock (clk_osc) is frequency-divided under the control of the external timing circuit (controlled by the frequency division factor div_fac, shown as 16 frequency division), using an asynchronous counter for frequency division, and the clk_enc generated by the frequency division is gated by tx_en control, thereby effectively reducing the power consumption of the synchronous encoding circuit.

The timing sequence of the encoding circuit is shown in Figure 6. Under the control of fm0_v, tx_m and tx_trext decoded by the asynchronous processing circuit, use clk_enc after frequency division by the clock generation circuit to perform FM0 encoding or Miller encoding (FM0 encoding in the figure) to be encoded bit tx_dat, and the encoded output is mo_dat. Both FM0 encoding and Miller encoding are realized by XOR operation of two signals triggered by rising edge and falling edge. Under the combined action of the last bit to be encoded and the counting completion signal, a coding completion signal (tx_dat_done) is generated. Because the synchronous encoding circuit uses the asynchronous handshake mechanism to control the bit to be encoded, it replaces the buffer and state machine in the pure synchronous encoding circuit, which can effectively reduce the area and power consumption of the synchronous encoding circuit.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (4)

1. A UHF RFID encoding circuit structure is characterized in that, comprises an asynchronous processing circuit and a synchronous encoding circuit, and an asynchronous processing circuit is used for outputting bits to be encoded and encoding control signals, and sends corresponding request signals; synchronous encoding circuit , used to return the response signal after the encoding is completed; the synchronous encoding circuit is composed of an asynchronous/synchronous interface, a clock generation circuit and an encoding circuit, wherein the asynchronous/synchronous interface receives the bit to be encoded and its request signal generated by the asynchronous processing circuit and the encoding control and Its request signal, and feed back the response signal of these requests; the clock generation circuit is used to generate the encoding clock; the encoding circuit is composed of the FM0 encoding circuit and the Miller encoding circuit, according to the bit to be encoded and the encoding control signal output by the asynchronous processing circuit, the clock is generated Under the control of the encoding clock generated by the circuit, FM0 encoding or Miller encoding is performed on the bit to be encoded. 2. UHF RFID coding circuit structure as claimed in claim 1, is characterized in that, according to the frequency division factor that synchronous timing circuit outputs, clock generation circuit carries out 2～32 frequency divisions to the source clock of 1.28MHz and is used for encoding clock. 3. The UHF RFID encoding circuit structure as claimed in claim 2, wherein the clock generation circuit uses an asynchronous counter to divide the frequency of the clock. 4. UHF RFID encoding circuit structure as claimed in claim 1, is characterized in that, FMO encoding and Miller encoding are all carried out XOR operation realization by two signals triggered by rising edge and falling edge.