CN1072393C - Ball Array Integrated Circuit Packaging Method - Google Patents
Ball Array Integrated Circuit Packaging Method Download PDFInfo
- Publication number
- CN1072393C CN1072393C CN97100004A CN97100004A CN1072393C CN 1072393 C CN1072393 C CN 1072393C CN 97100004 A CN97100004 A CN 97100004A CN 97100004 A CN97100004 A CN 97100004A CN 1072393 C CN1072393 C CN 1072393C
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- ball array
- packaging method
- array integrated
- electroplating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H10W72/0198—
-
- H10W90/754—
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
本发明涉及一种球阵式集成电路封装方法,是一种无需使用基板的球阵式(BGA)集成电路的封装方法,以使外包装更趋小巧。The invention relates to a packaging method of a ball array integrated circuit, which is a packaging method of a ball array (BGA) integrated circuit without using a substrate, so as to make the outer packaging more compact.
为达到符合不同场合的需要,现今集成电路的外包装有各式不同的外包装形式,诸如DIP、PGA、BGA、TAB……等型式,而以球阵式(BGA)(BALL GRID ARRAY)集成电路的外包装而论,其是在集成电路外包装的底面形成纵横排列的多数锡球接点,而供热熔焊接于电路板相应的接点上,但是在此种包装形式,由于制程期间需适当支撑以及供做为锡球与晶片的介质之下,一般均需以电路板做为「支撑基板」,在加入基板的封装中,即导致外包装尺寸厚度增加,此举,在包装尺寸要求较为严格的笔记型或次笔记型电脑上使用时,即有过于占用空间的问题存在,故有再予改进的必要。In order to meet the needs of different occasions, the outer packaging of integrated circuits today has a variety of different packaging forms, such as DIP, PGA, BGA, TAB... and other types, and BGA (BALL GRID ARRAY) integrated As far as the outer packaging of the circuit is concerned, it is formed on the bottom surface of the integrated circuit outer packaging with a large number of solder ball joints arranged vertically and horizontally, and is heated and welded to the corresponding contacts of the circuit board. Under the support and the medium used as the solder ball and the chip, the circuit board is generally required to be used as the "support substrate". In the package with the substrate, the thickness of the outer package will increase. When used on strict notebook or sub-notebook computers, there is a problem of taking up too much space, so it is necessary to improve it.
本发明的主要目的在于提供一种无基板的球阵式集成电路外包装方法,以省略基板而使得外包装更趋轻薄短小。The main purpose of the present invention is to provide a substrate-less ball array integrated circuit packaging method, so as to omit the substrate and make the packaging more light, thinner and shorter.
为达到上述目的,本发明采取如下技术方案:To achieve the above object, the present invention takes the following technical solutions:
本发明的球阵式集成电路封装方法,包括以下步骤:The ball array integrated circuit packaging method of the present invention comprises the following steps:
a.在铜片上覆干膜与电镀形成线路;a. Apply dry film and electroplating on the copper sheet to form a circuit;
b.对所述线路进行植入晶片;b. Implanting the circuit into a chip;
c.对所述晶片与线路之间进行连线;c. connecting the chip and the circuit;
d.灌胶覆盖所述晶片;d. potting glue to cover the wafer;
e.蚀刻去除所述铜片,使所述线路外露;e. Etching and removing the copper sheet to expose the circuit;
f.对应于线路的接点位置植入锡球;f. Implant solder balls corresponding to the contact positions of the lines;
g.蚀刻去除位于相邻晶片间的多余线路,以形成个别独立的晶片封装。g. Etching removes redundant lines between adjacent chips to form individual chip packages.
所述的球阵式集成电路封装方法,其特征在于:还包括涂布绿漆的步骤,在所述植入锡球的步骤完成后,进行涂布绿漆的步骤,以保护线路部份。The method for packaging the ball array integrated circuit is characterized in that it further includes the step of coating green paint. After the step of implanting solder balls is completed, the step of coating green paint is performed to protect the circuit part.
所述的球阵式集成电路封装方法,其特征在于:所述电镀形成的线路为外突的形式。The ball array integrated circuit packaging method is characterized in that: the circuit formed by the electroplating is in the form of protruding.
所述的球阵式集成电路封装方法,其特征在于:还包括一个涂布绿漆的步骤,在所述蚀刻去除多余线路的步骤后,再进行涂布绿漆的步骤。The ball array integrated circuit packaging method is characterized in that it also includes a step of coating green paint, and after the step of etching to remove redundant circuits, the step of coating green paint is performed.
本发明的球阵式集成电路封装方法与传统封装方式相比,具有如下效果:Compared with the traditional packaging method, the ball array integrated circuit packaging method of the present invention has the following effects:
本发明的封装方法仅形成有线路及电镀凸点30,可使外包装更趋轻盈小巧,且对缩小封装厚度有着积极的帮助,故为一具新颖性及进步性的球阵式集成电路封装方法。The packaging method of the present invention only has lines and electroplating bumps 30, which can make the outer package lighter and smaller, and actively help to reduce the thickness of the package, so it is a novel and progressive ball array integrated circuit package. method.
以下结合附图及实施例进一步说明本发明的具体结构特征及目的。The specific structural features and purposes of the present invention will be further described below in conjunction with the accompanying drawings and embodiments.
附图简要说明:Brief description of the drawings:
图1A~G是本发明的方法步骤示意图。1A-G are schematic diagrams of the method steps of the present invention.
本发明的可使最终成品获得无基板型式的封装形式,其封装方法,大致是如图1A~G所示,首先是在图1A的薄铜片10上经覆盖干膜20与对该未被干膜20遮蔽的位置进行电镀金属的步骤,以供形成如图1B朝上突起的电镀凸点30及各式线路图形(图面上均以凸点表示),然后进行植入晶片的步骤,此步骤是将数片晶片40以适当间隔距离黏合或结合方式附着于薄铜片10的具有电镀线路的表面上,之后,经如图1C的连线步骤,对各晶片40的各接脚焊接金线41以供连接至相应的电镀凸点30位置,其次,则进行如图1D的灌胶的步骤,此步骤是对各晶片40相应位置予以覆盖保护胶50,以防止晶片遭水份、空气或不当照射侵入,待保护胶50硬化后,即可进行如图1E所示,蚀刻去除前述薄铜片10,而使得前述各电镀凸点30及电镀线路呈外露状,之后,如图1F所示,在不需植入锡球的外露的电镀线路位置涂布绿漆(抗氧化膜),然后对外露的电镀凸点30进行植入锡球70的步骤,以使得相应于各晶片40底面形成阵列式的锡球接点(亦即形成BGA集成电路包装),由于在图1F中的相邻晶片40间仍有电镀线路11相互衔接,亦即在最后的步骤中,如图1G所示,再次进行一次蚀刻的步骤,以蚀刻去除前述的电镀线路11并再进行一道涂布绿漆保护的步骤,而使得相邻的晶片完全分离而呈独立的包装形式,如此即完成封装流程。In the present invention, the final product can be packaged without a substrate. The packaging method is roughly as shown in FIGS. 1A-G . The position covered by the dry film 20 is electroplated for forming electroplating bumps 30 protruding upward as shown in FIG. This step is to attach several chips 40 to the surface of the thin copper sheet 10 with electroplating lines by bonding or bonding at appropriate intervals, and then, through the wiring step as shown in Figure 1C, each pin of each chip 40 is welded Gold wires 41 are used to connect to corresponding electroplating bumps 30 positions. Next, the step of pouring glue as shown in FIG. Intrusion of air or improper irradiation, after the protective glue 50 hardens, can be carried out as shown in Figure 1E, etch to remove the aforementioned thin copper sheet 10, so that the aforementioned electroplating bumps 30 and electroplating lines are exposed, and then, as shown in Figure 1F As shown, green paint (anti-oxidation film) is coated on the exposed electroplating circuit positions that do not need to be implanted with solder balls, and then the exposed electroplating bumps 30 are implanted with solder balls 70, so that the corresponding wafers 40 The bottom surface forms an array of solder ball contacts (that is, forms a BGA integrated circuit package). Since there are still electroplating lines 11 connected to each other between adjacent chips 40 in FIG. 1F, that is, in the final step, as shown in FIG. 1G , performing an etching step again to etch and remove the aforementioned electroplating circuit 11 and then performing a step of coating green paint protection, so that adjacent chips are completely separated into independent packaging forms, thus completing the packaging process.
前述封装方式达了便于说明之故,而以仅附着两个晶片的方式描述,实际上,该封装方式是同时进行数片晶片的同时封装成型,特予陈明。For the sake of convenience of description, the above-mentioned packaging method is described as only two chips are attached. In fact, this packaging method is to carry out simultaneous packaging and molding of several chips at the same time, which is specially stated.
而在前述封装作业期间,即直接运用为位于薄铜片10做为中间流程的支撑,经灌胶后,即可利用保护胶50提供应有的支撑强度,因此,在后续步骤中,则可直接将薄铜片10蚀刻去除,而形成一种完全不含支撑基板的BGA集成电路包装,此即为本发明具创意及巧思之处,由前述本发明的最终成品(如图1G)来看,其是仅形成有线路及电镀凸点30,相比于传统封装方式,可使外包装更趋轻盈小巧,且对缩小封装厚度有着积极的帮助,故为一具新颖性及进步性的球阵式集成电路封装方法。During the aforementioned packaging operation, the thin copper sheet 10 is directly used as a support in the middle process. After the glue is poured, the protective glue 50 can be used to provide the proper support strength. Therefore, in the subsequent steps, it can be The thin copper sheet 10 is directly etched away to form a BGA integrated circuit package without a support substrate at all, which is the originality and ingenuity of the present invention. Look, it is only formed with lines and plating bumps 30. Compared with the traditional packaging method, the outer packaging can be made lighter and smaller, and it actively helps to reduce the thickness of the packaging. Therefore, it is a novel and progressive packaging method. Ball array integrated circuit packaging method.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97100004A CN1072393C (en) | 1997-02-05 | 1997-02-05 | Ball Array Integrated Circuit Packaging Method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97100004A CN1072393C (en) | 1997-02-05 | 1997-02-05 | Ball Array Integrated Circuit Packaging Method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1190252A CN1190252A (en) | 1998-08-12 |
| CN1072393C true CN1072393C (en) | 2001-10-03 |
Family
ID=5164706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97100004A Expired - Fee Related CN1072393C (en) | 1997-02-05 | 1997-02-05 | Ball Array Integrated Circuit Packaging Method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1072393C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446201C (en) * | 2004-09-30 | 2008-12-24 | 株式会社瑞萨科技 | Semiconductor device |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102136442B (en) * | 2010-01-22 | 2013-07-10 | 日月光封装测试(上海)有限公司 | Heating device for semiconductor packaging wire bonding process and fixture thereof |
| CN103560121A (en) * | 2013-08-31 | 2014-02-05 | 华天科技(西安)有限公司 | Frame csp package with bumping optimization technology based on chips of different sizes and production process thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222604A (en) * | 1995-02-15 | 1996-08-30 | Oki Electric Ind Co Ltd | Structure of semiconductor device and manufacturing method thereof |
-
1997
- 1997-02-05 CN CN97100004A patent/CN1072393C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08222604A (en) * | 1995-02-15 | 1996-08-30 | Oki Electric Ind Co Ltd | Structure of semiconductor device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100446201C (en) * | 2004-09-30 | 2008-12-24 | 株式会社瑞萨科技 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1190252A (en) | 1998-08-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3258764B2 (en) | Method for manufacturing resin-encapsulated semiconductor device, external lead-out electrode and method for manufacturing the same | |
| CN100385642C (en) | Pad redistribution layer and method for fabricating copper pad redistribution layer | |
| US8487441B2 (en) | Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging | |
| KR20000053618A (en) | Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device | |
| JP2000269381A (en) | Package substrate, semiconductor package and manufacturing method | |
| CN115547961A (en) | High-density integrated three-dimensional chip packaging structure and manufacturing method thereof | |
| KR100345166B1 (en) | Wafer level stack package and method of fabricating the same | |
| KR100780692B1 (en) | Chip stack package | |
| CN101383301A (en) | Method of forming flip chip bump carrier package | |
| US9209159B2 (en) | Hidden plating traces | |
| CN206558495U (en) | Chip is embedded in silicon substrate formula fan-out package structure | |
| KR100538485B1 (en) | Method for manufacturing bumped chip carrier package using lead frame | |
| CN1072393C (en) | Ball Array Integrated Circuit Packaging Method | |
| CN1190258A (en) | Ball array integrated circuit packaging method and package | |
| CN1072396C (en) | Ball array integrated circuit packaging method without substrate and solder ball | |
| CN1326432C (en) | High-density circuit board without pad design and manufacturing method thereof | |
| TW591782B (en) | Formation method for conductive bump | |
| CN1088968C (en) | Chip size package circuit board manufacturing method | |
| CN209312758U (en) | A kind of silicon wafer encapsulating structure | |
| CN100442465C (en) | Chip packaging body process without core dielectric layer | |
| KR100728978B1 (en) | Manufacturing Method of Wafer Level Package | |
| CN100367464C (en) | Method for manufacturing metal bump | |
| KR100599636B1 (en) | Manufacturing Method of Printed Circuit Board for BOS Semiconductor Packages | |
| TWI399839B (en) | Intermediary connector built into semiconductor package construction | |
| CN1180476C (en) | Integrated circuit packaging structure without solder mask and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20011003 |