CN107134409A - The ion injection method and transistor of transistor - Google Patents

Abstract

The present invention provides an ion implantation method for a transistor and the transistor, wherein the ion implantation method includes: forming a gate structure of the transistor to be prepared on a substrate on which a gate oxide layer is formed, and the regions on both sides of the gate structure are respectively A region reserved for the source and a region reserved for the drain; forming a sidewall on one side wall of the gate structure; after forming the sidewall, injecting the reserved region for the source and Ion implantation is performed in the reserved drain region, wherein the specified implantation angle is the angle between the vertical line of the gate structure and the trajectory of the ion implantation, when the vertical line is used as the starting point The track line and the side wall are distributed on opposite sides of the vertical line. Through the technical solution of the invention, the shadow effect in the ion implantation process is improved, and the device reliability of the transistor is improved.

Description

Ion implantation method of transistor and transistor

technical field

The invention relates to the technical field of semiconductor chips, in particular to an ion implantation method of a transistor and a transistor.

Background technique

In the related art, in order to prevent the tunneling effect in the process of manufacturing the transistor, the incident angle of the ion implantation is usually changed during the source-drain implantation process, wherein the incident angle is between the trajectory line of the ion implantation and the vertical line angle.

As shown in FIG. 1, in order to improve the shadow effect, the implantation process of the transistor adopts a multiple implantation process, which specifically includes: forming a silicon gate structure 103 on the silicon substrate 102 on which the gate oxide layer 101 is formed, and multiple ion implantation and driving The source electrode 104 and the drain electrode 105 are formed by implantation process. Specifically, the angle between the trajectory line 106 of the first ion implantation and the vertical line 108 is α, and the trajectory line 107 of the second ion implantation and the vertical line 108 The included angle between is also α, in order to reduce the possibility of shading efficiency.

However, the deviation of multiple injections will accumulate and lead to the deviation of the electrical parameters of the source 104 and the drain 105 . Therefore, multiple injections not only increase the production cost, but also seriously affect the device reliability of the transistor.

Therefore, how to design a low-cost transistor ion implantation scheme to improve the shadow effect has become an urgent technical problem to be solved.

Contents of the invention

Based on at least one of the above-mentioned technical problems, the present invention proposes a new ion implantation scheme for transistors. By forming a side wall on one side wall of the gate structure, the shadow effect can be improved by ion implantation at a specified implantation angle only once. , improve process stability and device reliability, and reduce production cost.

In view of this, the present invention proposes an ion implantation method for a transistor, including: forming a gate structure of the transistor to be prepared on a substrate forming a gate oxide layer, and the regions on both sides of the gate structure are respectively source electrodes A reserved region and a reserved drain region; forming a sidewall on one side wall of the gate structure; after forming the sidewall, injecting the reserved region of the source and the drain Ion implantation is performed in the reserved region of the electrode, wherein the specified implantation angle is the angle between the vertical line of the gate structure and the trajectory of the ion implantation, and when the vertical line is used as the starting point, the trajectory The line and the side wall are distributed on opposite sides of the plumb line.

In this technical solution, by forming a side wall on one side wall of the gate structure, the shadow effect is improved by only one ion implantation at a specified implantation angle, the process stability and device reliability are improved, and the production cost is reduced at the same time.

Specifically, the width a of the sidewall is determined by the height b of the silicon gate structure and the preset implantation angle α, and the formula tanα=a/b holds true.

In the above technical solution, preferably, the specified injection angle is greater than or equal to zero.

In any one of the above technical solutions, preferably, the specified injection angle ranges from 3° to 30°.

In any one of the above technical solutions, preferably, the specified injection angle is 7°.

In this technical solution, by determining that the specified implantation angle is 7°, and performing ion implantation on the source reserved region and the drain reserved region based on the sidewall, a preferred implementation of the implantation angle is provided. On the one hand, The tunnel effect is avoided, and on the other hand, the adverse effects caused by the shadow effect are improved.

In any one of the above technical solutions, preferably, before forming the gate structure of the transistor to be prepared on the substrate on which the gate oxide layer is formed, further comprising: thermal oxidation process at a temperature range of 900-1000° C. forming an oxide layer on the substrate; forming a polysilicon layer by a chemical vapor deposition process with a temperature range of 500-700°C; performing photolithography and etching on the polysilicon layer and the oxide layer to form the gate structure and the gate oxide layer.

In this technical scheme, an oxide layer is formed by a thermal oxidation process, a polysilicon layer is formed by a chemical vapor deposition process, and a gate structure and a gate oxide layer are formed by photolithography and etching, thereby improving the structural reliability of the transistor.

In any one of the above technical solutions, preferably, forming a side wall on one side wall of the gate structure specifically includes the following steps: using a chemical vapor deposition process with a temperature range of 600-900°C on the A silicon nitride layer is formed on the gate structure; photolithography and etching are performed on the silicon nitride layer to form the side walls.

In this technical solution, by forming a silicon nitride layer and forming sidewalls through photolithography and etching, the process compatibility is high, shadow effects and multiple injection inhomogeneities are avoided, and production costs are reduced.

In any one of the above technical solutions, preferably, forming a side wall on one side wall of the gate structure, specifically further includes the following steps: spin-coating a photoresist on the substrate on which the gate structure is formed , and sequentially perform exposure and development on the photoresist, and only retain the photoresist on one side wall of the gate structure to form the side wall.

In this technical solution, the reliability of the injection process is improved by forming the photoresist as the side wall, and the process is compatible with the standard CMOS process, thereby further reducing the production cost.

In any one of the above technical solutions, preferably, the ion-implanted ions are boron ions, the dose range is 1.0E12-1.0E16/cm ² , and the energy range is 40-200KeV.

In any one of the above technical solutions, preferably, the ion-implanted ions are phosphorus ions or arsenic ions, the dose range is 1.0E12-1.0E16/cm ² , and the energy range is 40-200KeV.

According to the second aspect of the present invention, a transistor is also proposed, which is prepared by the ion implantation method of the transistor described in any one of the above technical solutions. Therefore, the transistor has the same characteristics as described in any one of the above technical solutions. The same technical effect as the ion implantation method of transistors, will not be repeated here.

Through the above technical solution, by forming a side wall on one side wall of the gate structure, the shadow effect is improved by only one ion implantation at a specified implantation angle, the stability of the process and the reliability of the device are improved, and the production cost is reduced at the same time.

Description of drawings

FIG. 1 shows a schematic cross-sectional structure diagram of the shadow effect of a transistor in the related art;

FIG. 2 shows a schematic flowchart of an ion implantation method for a transistor according to an embodiment of the present invention;

3 to 5 show schematic cross-sectional views of the ion implantation process of the transistor according to the embodiment of the present invention.

detailed description

In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

In the following description, many specific details are set forth in order to fully understand the present invention. However, the present invention can also be implemented by a third party different from the third party described here. Therefore, the protection scope of the present invention is not limited by the following disclosure. The limitations of specific examples.

The ion implantation method of the transistor according to the embodiment of the present invention will be specifically described below with reference to FIG. 2 to FIG. 5 .

As shown in FIG. 2 to FIG. 5 , the ion implantation method for a transistor according to an embodiment of the present invention includes: step 202, forming a gate structure 303 of a transistor to be prepared on a substrate 302 on which a gate oxide layer 301 is formed, and The regions on both sides of the gate structure 303 are respectively a reserved source region 305 and a reserved drain region 306; Step 204, forming a sidewall 304 on one side wall of the gate structure 303; Step 206, After the sidewalls 304 are formed, ion implantation is performed on the source reserved region 305 and the drain reserved region 306 at a specified implantation angle α, wherein the specified implantation angle α is the gate structure 303 The angle α between the vertical line 307 of the ion implantation and the trajectory line 308 of the ion implantation, when the vertical line 307 is used as the starting point, the trajectory line 308 and the side wall 304 are distributed on the vertical line 307 opposite side.

In this technical solution, by forming a side wall 304 on one side wall of the gate structure 303, only one ion implantation with a specified implantation angle α can improve the shadow effect, improve the stability of the process and the reliability of the device, and at the same time reduce the Cost of production.

Specifically, the width a of the sidewall 304 is determined by the height b of the silicon gate structure and the preset implantation angle α, and the formula tanα=a/b holds true.

In the above technical solution, preferably, the specified injection angle α is greater than or equal to zero.

In any one of the above technical solutions, preferably, the specified injection angle α ranges from 3° to 30°.

In any one of the above technical solutions, preferably, the specified injection angle α is 7°.

In this technical solution, by determining that the specified implantation angle α is 7°, and performing ion implantation on the source reserved region 305 and the drain reserved region 306 based on the spacer 304, an implementation of the preferred implantation angle α is provided. The scheme, on the one hand, avoids the tunnel effect, and on the other hand, improves the adverse effects caused by the shadow effect.

In any of the above technical solutions, preferably, before forming the gate structure 303 of the transistor to be prepared on the substrate 302 on which the gate oxide layer 301 is formed, it further includes: a thermal oxidation process with a temperature range of 900-1000°C forming an oxide layer on the substrate 302; forming a polysilicon layer by a chemical vapor deposition process at a temperature range of 500-700° C.; performing photolithography and etching on the polysilicon layer and the oxide layer to form the Gate structure 303 and the gate oxide layer 301.

In this technical solution, an oxide layer is formed by a thermal oxidation process, a polysilicon layer is formed by a chemical vapor deposition process, and a gate structure 303 and a gate oxide layer 301 are formed by photolithography and etching, thereby improving the structural reliability of the transistor.

In any of the above-mentioned technical solutions, preferably, forming the side wall 304 on one side wall of the gate structure 303 specifically includes the following steps: using a chemical vapor deposition process with a temperature range of 600-900°C on the A silicon nitride layer is formed on the gate structure 303 ; photolithography and etching are performed on the silicon nitride layer to form the sidewall 304 .

In this technical solution, by forming a silicon nitride layer and forming sidewalls 304 through photolithography and etching, the process compatibility is high, shadow effects and unevenness of multiple injections are avoided, and production costs are reduced.

In any of the above technical solutions, preferably, forming a side wall 304 on one side wall of the gate structure 303 specifically includes the following steps: spinning the substrate 302 on which the gate structure 303 is formed Apply photoresist, and sequentially perform exposure and development on the photoresist, leaving only the photoresist on one side wall of the gate structure 303 to form the side wall 304 .

In this technical solution, by forming the photoresist as the side wall 304, the reliability of the injection process is improved, and the process is compatible with the standard CMOS process, further reducing the production cost.

In any one of the above technical solutions, preferably, the ion-implanted ions are boron ions, the dose range is 1.0E12-1.0E16/cm ² , and the energy range is 40-200KeV.

In any one of the above technical solutions, preferably, the ion-implanted ions are phosphorus ions or arsenic ions, the dose range is 1.0E12-1.0E16/cm ² , and the energy range is 40-200KeV.

The technical solution of the present invention has been described in detail above in conjunction with the accompanying drawings. Considering the problems in the related technologies, the present invention proposes how to design a low-cost transistor ion implantation scheme to improve the technical problem of the shadow effect. The present invention proposes a The new ion implantation scheme for transistors, by forming a side wall on one side of the gate structure, only one ion implantation at a specified implantation angle improves the shadow effect, improves process stability and device reliability, and reduces production costs. cost.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. a kind of ion injection method of transistor, it is characterised in that including：

The grid structure of transistor to be prepared, the grid are formed on the substrate for forming gate oxide The two side areas of structure is respectively source electrode reserved area and drain electrode reserved area；

Side wall is formed on the side side wall of the grid structure；

After the side wall is formed, to specify implant angle to the source electrode reserved area and the drain electrode Reserved area carries out ion implanting,

Wherein, the specified implant angle is the plumb line and the ion implanting of the grid structure Angle between trajectory, the trajectory is distributed in the offside of the plumb line with the side wall.

2. the ion injection method of transistor according to claim 1, it is characterised in that institute Specified implant angle is stated more than or equal to zero.

3. the ion injection method of transistor according to claim 2, it is characterised in that institute The scope for stating specified implant angle is 3~30 °.

4. the ion injection method of transistor according to claim 3, it is characterised in that institute Specified implant angle is stated for 7 °.

5. the ion injection method of transistor according to claim 4, it is characterised in that Formed on the substrate for forming gate oxide before the grid structure of transistor to be prepared, in addition to：

Oxide layer is formed over the substrate by 900~1000 DEG C of thermal oxidation technology of temperature range；

Polysilicon layer is formed by 500~700 DEG C of chemical vapor deposition method of temperature range；

Photoetching and etching are carried out to the polysilicon layer and the oxide layer, to form the grid structure With the gate oxide.

6. the ion injection method of transistor according to any one of claim 1 to 5, its It is characterised by, forms side wall on the side side wall of the grid structure, specifically include following steps：

Formed by 600~900 DEG C of chemical vapor deposition method of temperature range on the grid structure Silicon nitride layer；

Photoetching and etching processing are carried out to the silicon nitride layer, to form the side wall.

7. the ion injection method of transistor according to claim 6, it is characterised in that Side wall is formed on the side side wall of the grid structure, it is specific further comprising the steps of：

The spin coating photoresist on the substrate for forming the grid structure, and the photoresist is carried out successively Exposure and development treatment, only retains the photoresist of the side side wall of the grid structure, described to be formed Side wall.

8. the ion injection method of transistor according to claim 7, it is characterised in that institute The ion for stating ion implanting is boron ion, and dosage range is 1.0E12~1.0E16/cm², energy range For 40~200KeV.

9. the ion injection method of the transistor according to claim 7 or 8, its feature exists In the ion of the ion implanting is phosphonium ion or arsenic ion, and dosage range is 1.0E12~1.0E16/cm², energy range is 40~200KeV.

10. a kind of transistor, it is characterised in that using as any one of claim 1 to 9 The ion injection method of transistor be prepared from.