CN107123438A - Simulate Multiport approach and simulation multiport memory body - Google Patents
Simulate Multiport approach and simulation multiport memory body Download PDFInfo
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- G—PHYSICS
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- G11C—STATIC STORES
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- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
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- G—PHYSICS
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Abstract
The embodiment of the present invention provides simulation Multiport approach and its memory body.The memory body includes：Data input output ports, memory controller, module for reading and writing, row decoder module, N number of memory block, Continuity signal guiding system and switching network.The row decoder module includes row decoder 1 to row decoder Q Q row decoder；Row decoder address wire connection corresponding with the n-th memory block；The row decoder module is under the configuration of the memory controller, make corresponding row decoder output Continuity signal, the Continuity signal is exported to the address wire of n-th memory block, Continuity signal guiding system is used to guide the Continuity signal in addition to the n-th memory block, remaining corresponding address wire of each memory block.The switching network is connected by the module for reading and writing with N number of memory block, and the memory block and data input output ports are matched according to pre-defined rule.
Description
Technical field
The present invention relates to storage device technical field, Multiport approach and simulation multiport memory are more particularly to simulated
Body.
Background technology
General, memory body can be divided into two kinds of single port and multiport.Operation may only every time for single port memory body
An address is inputted, the data of the address are read or write.Multiport memory body every time operation can then input it is multiple arbitrarily
Location signal, any data for reading or writing corresponding address signal.
Existing semiconductor IP supplier typically only provides single port or dual-port static memory body SRAM memory body production
Raw device.Memory body based on single port or multiport can arbitrarily produce different size of memory body.
For example, Fig. 1 is the 6T bitcell (memory cell) of the single-port SRAM usually used in the prior art circuit
Schematic diagram.As shown in figure 1, the single-port memory cell is made up of 2 p-type pipes and 4 N-type pipes, WL is selection line.It is 1 in WL
When, M5 and M6 can be turned on, so as to make the memory cell conducts.BL and BLB is a pair of differential data signals lines, is connected to read-write
Module.Typically before write-in or reading, while being initialized to high level, difference is done again further according to reading or writing data.One
In the individual clock cycle, the single-port memory cell can only perform write-in or read an operation.
Fig. 2 is the dual-port SRAM usually used in the prior art 8T bitcell (memory cell) circuit theory
Figure.As shown in Fig. 2 the dual port memory unit is compared to Fig. 1, add M7 and M8 switching tubes, with 2 selection line WL1 and
WL2 and two pair of differential data signals line (BL1, BL2, BLB1, BLB2).The dual port memory unit can be a clock week
2 read-write operations are performed in phase simultaneously.
In some applications, such as image procossing, video frequency signal processing, communication field from memory body, it is necessary to connect
Resume studies and write the data of multiple addresses.For example, processor (CPU) is more from typically can continuously be read during the reading instruction of main program memory body
Cache device (cache) inside individual instruction deposit, is then reading and is performing from cache one by one.Either in signal
In processing procedure, since some address K of memory body, continuously read N number of data (K, K+1 are until K+N-1) and handled.
To meet above-mentioned application scenarios, usual solution is to use single port memory body, and in several clocks week
In phase, multiple read-write operation continuously is performed to single port memory body, so as to complete the reading to the data of multiple addresses in memory body
Write operation.
In process of the present invention is realized, inventor has found that correlation technique has problems with：Existing single port memory body,
The data of one address of read-write are required to carry out a read-write operation every time.Thus, multiple continuous data addresses are being carried out
During read-write operation, power consumption is higher, and reading and writing data time delay is longer.Although and using the memory body of more multiport to reduce reading
Clock cycle and power consumption needed for write operation, but chip area can be caused to dramatically increase.
The content of the invention
The embodiment of the present invention provides simulation Multiport approach and simulation multiport memory body, can solve the problem that single in the prior art
Port memory body read-write data power consumption is higher, when the problem of extend.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of simulation multiport memory body.It includes：Data are defeated
Enter output port, memory controller, module for reading and writing, row decoder module, the 1st memory block to N memory blocks, the storage
Block is the memory cell array of P row Q rows；Selection line in each memory block with the memory cell of a line is connected to same
In address wire, each memory block has Q address wire, and N, P and Q are equal positive integer；The row decoder module includes row decoder 1
To row decoder Q Q row decoder；Row decoder module address wire connection corresponding with the n-th memory block；The row
Decoder module is under the configuration of the memory controller, order correspondence row decoder output Continuity signal conducting n-th storage
The address wire of block；N is the positive integer between 1-N；Continuity signal guides system, and the Continuity signal guiding system is used for institute
State Continuity signal to guide in addition to the n-th memory block, remaining corresponding address wire of each memory block；And switching network, it is described
Switching network is connected by the module for reading and writing with N number of memory block, according to predetermined exchange regulation match the memory block and
Data input output ports.
Alternatively, if the simulation multiport memory body has 0-K K address, each memory cell has unique
Address；First access unit address of the q rows of the n-th memory block be：(q-1)×N+(n-1)；N is 1 between N
Positive integer, q is 1 to the positive integer between Q；Last access unit address of N memory blocks is K.
Alternatively, the Continuity signal guiding system includes：It is correspondingly arranged with the 1st memory block to N-1 memory blocks
N-1 address wire selecting module；The address wire selecting module includes selector 1 to selector Q Q selector, described
Selector is alternative selector；The address wire q connections of selector q output end and corresponding memory block；The two of selector q
Individual input is coupled with row decoder q and row decoder q+1 respectively；Q is 1 to the positive integer between Q；Wherein, selector 1 is defeated
Enter end to couple with row decoder Q and row decoder 1 respectively.
Alternatively, the Continuity signal guiding system includes：It is correspondingly arranged with the 1st memory block to N-1 memory blocks
N-1 address wire selecting module；The address wire selecting module includes selector 1 to selector Q Q selector, described
Selector is alternative selector；The address wire q connections of selector q output end and corresponding memory block；The two of selector q
Individual input is coupled with row decoder q and row decoder q+1 respectively；Q is 1 to the positive integer between Q；Wherein, the row decoding
Module also includes an extra row decoder Q, and the extra row decoder Q is arranged on by the row decoder 1, the choosing
The input for selecting device 1 is coupled with the extra row decoder Q and row decoder 1 respectively.
Alternatively, the data input output ports at least include：Address signal input port, N number of write-in FPDP,
N number of read data ports and N number of read-write operation port；N is the port number for simulating multiport memory body.
Alternatively, the switching network includes several switching networks 1 for being correspondingly arranged with the memory block to switching network N；
The switching network is according to predetermined exchange regulation, selection correspondence memory block and said write FPDP and reading data terminal
Mouth matching.
In order to solve the above technical problems, another embodiment of the present invention provides a kind of method for simulating multiport.The side
Method includes：A data read write command is received, the reading and writing data instruction includes：Address signal and read-write operation signal；Root
According to the address signal Continuity signal is exported in corresponding row decoder；According to the address signal, make the Continuity signal defeated
Enter address wire corresponding to each memory block, the memory cell of conducting correspondence row；According to the read-write operation signal, institute is controlled
State memory cell and perform respective operations；By the address signal, N number of memory block and data input output ports are determined
Matching relationship.
Alternatively, methods described also includes：Data are write to the 1st row of N number of memory block successively according to address；Institute
Stating address includes 0-K K address；
After the 1st row write of all memory blocks enters to finish, data are write to the of N number of memory block successively again
2 rows；Above-mentioned data write operation is repeated until last address K of N memory blocks is written into.
Alternatively, it is described according to the address signal, make the Continuity signal input corresponding to each memory block
Location line, the memory cell of conducting correspondence row, is specifically included：
Row decoder q exports Continuity signal to the address wire q of N memory blocks, makes the memory cell conducts of q rows；
The Continuity signal is made to pass sequentially through some selectors, into N-1 memory blocks to the 1st memory block；
When the Continuity signal is from currently stored block into next memory block, under being entered by selector selection
The current row address line or next row address line of one memory block, order correspondence row memory cell conducts, q be 1-Q between just
Integer.
Alternatively, when the Continuity signal is from currently stored block into next memory block, selected by the selector
Select the current row address line or next row address line into next memory block, the memory cell conducts of order correspondence row, specific bag
Include：
Address signal is parsed, the n-th memory block corresponding with address signal is obtained；
To the corresponding selector output first choice signal of the n-th memory block；The first choice signal turns on for control
Signal enters the selection signal of next row address line；
The second selection signal is inputted to other selectors, second selection signal enters current line for control Continuity signal
The selection signal of address wire.
Alternatively, methods described also includes：, will during selector output first choice signal corresponding to the n-th memory block
The Continuity signal of row decoder Q outputs, is guided to the address wire 1 of the n-th memory block.The simulation provided in the embodiment of the present invention is more
Port method and simulation multiport memory body, can use single-port memory cell to realize the effect of multiport simulation.Needing
When being written and read operation to multiple continuation addresses of memory body, it is only necessary to once-through operation is performed to memory body, a clock week
It can be completed in phase, power consumption and reading and writing data time delay can also be reduced while chip area is saved.
Brief description of the drawings
One or more embodiments are illustrative by the picture in corresponding accompanying drawing, these exemplary theorys
The element with same reference numbers label is expressed as similar element in the bright restriction not constituted to embodiment, accompanying drawing, removes
Composition is not limited the non-figure having in special statement, accompanying drawing.
Fig. 1 is typical 6T bitcell circuit theory diagrams；
Fig. 2 is typical 8T bitcell circuit theory diagrams；
Fig. 3 is the application environment schematic diagram of memory body provided in an embodiment of the present invention；
Fig. 4 is the input/output end port schematic diagram of typical single port memory body；
Fig. 5 is the structured flowchart of typical single port memory body；
Fig. 6 is the input/output end port schematic diagram provided in an embodiment of the present invention for simulating multiport memory body；
Fig. 7 is the structured flowchart provided in an embodiment of the present invention for simulating multiport memory body；
The structured flowchart for the simulation multiport memory body that Fig. 8 provides for another embodiment of the present invention；
The structured flowchart for the simulation multiport memory body that Fig. 9 provides for further embodiment of this invention；
Figure 10 is the method flow diagram provided in an embodiment of the present invention for simulating Multiport approach.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the present invention, not
For limiting the present invention.
Fig. 3 is the application environment schematic diagram of memory body provided in an embodiment of the present invention.In the application environment, including memory
Body 10 and processor 20.
The memory body 10 has multiple addresses, points to corresponding memory cell (such as each address and a data pair
Should, or each address can be corresponding with 8bit or 32bit digit data).Each memory cell stores 1 data.Place
Device 20 is managed during execute program instructions, such as performing some image processing algorithms, Video processing or communication frame processing,
Need to carry out read/write operation to continuous multiple addresses of memory body 10.
As processor 20 reads continuous 3 of the address n to n+2 of memory body 10 in some image processing algorithms, it is necessary to perform
Operation in the data of address, and the memory cell that the result writing address n+3 after computing is pointed to.
Fig. 4 and Fig. 5 is existing single port memory body.Below in conjunction with Fig. 4 and Fig. 5, the application shown in Fig. 3 is described in detail in
In environment, the read-write operation process of existing single port memory body is used.
As shown in figure 4, the instruction needed for existing single port memory body in operating process is written and read or data,
Specifically include：Address signal addr, write-in data wdata, enable signal cs, read-write operation signal rwen, clock signal clk with
And read data rdata.Above-mentioned signal can use various suitable forms, be configured according to actual conditions.For example, can
So that read-write operation signal rwen to be configured to：In rwen=1, control memory body performs read operation, reads address addr
The data of corresponding memory cell are exported as data rdata is read；In rwen=0, control memory body performs write operation,
It will write in the memory cell that data wdata write-in memory bodys address addr is pointed to.
Fig. 5 is the functional block diagram of the single port memory body shown in Fig. 4.As shown in figure 5, the memory body can include：It is used to
Receive command signal and make the memory controller 100, row decoder module 200, sense amplifier/write-in of alignment processing operation
Buffer 300 and the memory cell array 400 being made up of several single-port memory cells.
During specific read-write operation, memory controller 100 can be set in clock signal clk rising edge
Enable signal cs, read-write operation signal rwen and the address signal addr of input are decoded, so that confirm needs execution is to read
Or the memory cell that operation address, the operation address of write operation and read/write operation execution are pointed to.Memory controller
100 enable signal rowen according to analysis result, by corresponding control signal ctrl and row decoder module exports to described respectively
In row decoder module 200 and sense amplifier/write buffer 300.
The row decoder module 200 includes the row decoder that the line number of several and memory cell array is correspondingly arranged, and connects
After the enable signal rowen that admission controller is provided, decoded address signals make corresponding row decoder output Continuity signal make storage
Certain a line conducting in cell array 400.
The control signal that the sense amplifier is then provided according to memory controller 100, amplification address signal addr refers to
To memory cell BL and BLB signals, be used as read data rdata output.For example, the sense amplifier can be configured
For：When the level of BL signals is higher than BLB, the sense amplifier output signal 1, otherwise output signal 0.Said write is buffered
The control signal that device is then provided according to memory controller 100, will write depositing for data wdata writing address signals addr sensings
Storage unit.For example, write buffer is configurable to：When wdata is 1, the voltage of BL stops after initialization is made, BLB's
Voltage is pulled down to close to VSS, then opposite when wdata is 0.
Because sense amplifier and write buffer are arranged in pairs, respectively for the digital independent of certain array storage unit
And data write operation.It is easy for statement, read-out amplifier is represented with One function frame 300 in Figure of description below and write
Enter buffer, and referred to as " module for reading and writing " 300.
To complete the task of the application environment shown in Fig. 3, processor 20 can be in each clock cycle to memory body
10 send read/write operation instruction (instruction or data needed is as shown in Figure 4), are write on an address of memory body 10
Data or the data for reading some address.For example, in the 1st clock cycle, completing the read operation to address n；At the 2nd
Clock cycle, complete address n+1 read operation；In the 3rd clock cycle, address n+2 read operation and during at the 4th
In the clock cycle, complete the write operation to address n+3.
Such, if using single port memory body, in the application environment shown in Fig. 3, the operation to N number of address needs to hold
Operation of the row n times to memory body, required power consumption is larger, and the time being related to is also longer (N number of clock cycle).
In further embodiments, the memory body (example with multiport can also be used in the application environment shown in Fig. 3
Such as 4 port memory bodys).Such, processor 20 is when performing the read/write operation to continuous 4 addresses of memory body, it is only necessary to
In 1 clock cycle, operation once to memory body is performed.But, the memory body of more multiport needs the chip area taken
It is larger, and the standardized product that more multiport memory body (such as 3 ports, 4 port memory bodys) is not commonly used, general semiconductor
IP manufacturers can't supply such product, it is necessary to designed, designed.
Performed for preferably lifting single port memory body shown in Fig. 3, processor is carried out to the continuation address of memory body
Performance during read/write operation, multiport memory body is being simulated the embodiments of the invention provide one kind.The simulation multiport memory body
Can be on the basis of using single port memory body, the functional module set up by some realizes the effect of simulation multiport, from
And obtain balance between chip area, memory body cost and memory body port number.
In simulation multiport memory body provided in an embodiment of the present invention, the memory cell used is the 6T's shown in Fig. 1
Single-port memory cell.It is, of course, also possible to use the memory cell of other suitable types.
Fig. 6 is the port schematic diagram provided in an embodiment of the present invention for simulating multiport memory body.As shown in fig. 6, the memory
Body can include data input output ports as described below, to input corresponding number to simulate the memory body of N number of port
According to/instruct or export corresponding data：
Clock signal port clk, enable signal port cs, address signal port addr, write-in FPDP wdata1 are extremely
WdataN, read-write operation port rwen1 to rwenN and read data ports rdata1 to rdataN.
Wherein, N for example can specifically set N by technical staff according to setting the need for actual conditions or usage scenario
It is set to 4.Address signal addr is performs first address signal of read/write operation, and such as processor 20 is needed to 4-7 this 4
When continuation address performs read/write operation, the address signal addr inputted in Fig. 6 is 4.
Read-write operation port rwen1-rwenN is to input the read-write operation signal for each address.That is, read-write behaviour
Make port rwen1 input signal it is corresponding be address signal addr read-write operation signal, rwen2 corresponding is address addr
+ 1 read-write operation signal, until rwenN corresponding address addr+N-1 read-write operation signal.
The read-write operation signal can be configured according to actual conditions, for example, in corresponding ports input " 1 ", representing
Control memory body to perform read operation in the address, in corresponding ports input " 0 ", represent that control memory body is performed in the address
Write operation.In another embodiment of the invention, it can also increase according to actual needs or economization some extra data
Port and be not limited to shown in Fig. 6.
Fig. 7 is the structured flowchart provided in an embodiment of the present invention for simulating multiport memory body.As shown in fig. 7, except existing
Outside module needed for single port memory body, the simulation multiport memory body also includes the 1st to N N number of independent memory block
Block 400, N-1 address wire selecting module 500 and N number of switching network 600.
Wherein, each memory block 400 is the storage array of P row Q rows.Each memory block 400 has corresponding with Q rows
Address wire 1 be then connected to corresponding module for reading and writing to address wire Q, differential data signals the line BL and BLB of each memory cell
In 300, the memory cell positioned at same row shares differential data line BL and BLB.
Alternatively, one module for reading and writing 300 of use that the memory cell of each row both can be independent.One can also be shared
Module for reading and writing 300 simultaneously increases extra selection device, selects the memory cell of the respective column of conducting to perform read/write operation.
One of memory block 400 is connected that (N as shown in Figure 7 is deposited with the row decoder module 200 of single port memory body
Storage area block).Row decoder module 200 includes row decoder 1 to row decoder Q Q row decoder, the row decoder q and N
The corresponding address wire q connections of memory block, q is the positive integer between 1-Q.
When performing memory body read operation, under the configuration of memory controller 100, row decoder module 200 is corresponding
Row decoder will export a Continuity signal.The Continuity signal enters in the corresponding address wire of N memory blocks, turns on the row
Memory cell.The memory cell of conducting can be read or write-in data by module for reading and writing 300.
As shown in fig. 7, the address wire selecting module 500 connects two adjacent memory blocks 400.N-1 address wire
Selecting module 500 constitutes a Continuity signal guiding system.By the Continuity signal guide system, can guide Continuity signal from
N memory blocks have respectively entered the remaining 1st to the corresponding address wire of N-1 memory blocks, so as to make N number of memory block
In certain a line memory cell conducts.
In actual mechanical process, specifically predetermined control can be configured according to the actual address facilities of memory block
Signal processed or rule, make Continuity signal guiding system order control row that each memory block needs to turn on (for example,
Controlled in Fig. 7 using selection control signal sel_n, n is 1 to N-1 positive integer, respectively with N-1 address wire selecting module
Correspondence, such as sel_1, sel_2 ..., sel_N-1).
As shown in fig. 7, in certain embodiments, the selection control signal sel_n can be by extra address line options
The controller 502 of module is determined according to the address signal of input.It is any suitable that the controller 502 can specifically be used,
ALU with correspondence decoding capability is realized.It may be integrally incorporated in address wire selecting module, be used as address line selection
A part for module is selected, it can also be provided that discrete functional module.
In embodiments of the present invention, system is guided by the Continuity signal being made up of multiple address wire selecting modules, only needed
Once-through operation is carried out to memory body, you can realize and read/write operation is performed to one of address of each memory block, thus
To realize the effect of simulation multiport.
Certainly, except guiding system by addition to the guiding of Continuity signal to each memory block by Continuity signal, memory body control
Device 100 processed also needs to the address arrangement mode according to memory block, determines specific corresponding between each memory block and port
Relation is to ensure that read/write operation can be carried out correctly in order.For example, it is desired to determine the 1st address signal addr read-write behaviour
Make the corresponding memory block of signal, n-th of the address addr+n-1 corresponding memory block of read-write operation signal etc..
In the present embodiment, by connecting memory block and write-in FPDP wdata1-wdataN, read-write operation end
Mouthful rwen1-rwenN and read data ports rdata1-rdataN switching network 600 completes above-mentioned port and memory block
Matching.The switching network 600, by memory block and corresponding port match, makes memory body according to the exchanged form configured
Digital independent or write operation of the 10 orderly completions to continuous N number of address.
In certain embodiments, the switching network 600 can pass through 2 N:1 selector is realized.
It is, for example, possible to use 24:1 selector realizes the switching network 600 as shown in Fig. 8 or Fig. 9.Practical implementation
In, according to addr [1:0] and the corresponding storage block of switching network calculates the corresponding selection signal of two selectors, select respectively
One of them in wdata1~wdata4 is output to one rdata_bank1~rdata_ of wdata_bank4 and selection
Bank4 to rdata4.
Simulation multiport memory body provided in an embodiment of the present invention is extra by setting based on single-port memory cell
Continuity signal guiding system, switching network and arranged according to actual address, configure corresponding control mode, realize simulation multiterminal
The effect of mouth.
In the application environment shown in Fig. 3, during using simulation multiport memory body provided in an embodiment of the present invention, processor
20 can perform once-through operation to memory body to complete to perform read/write behaviour in continuous N number of address within a clock cycle
Make.Compared with single port memory body of the prior art, required clock cycle and the number of operations of memory body is obtained
Great reduction, and due to being realized based on single-port memory cell, the chip area of occupancy is smaller.
Fig. 8 sets schematic diagram for the address of memory block provided in an embodiment of the present invention.Below with Fig. 8 memory block
Exemplified by location is set, it is described in detail how to configure above-mentioned Continuity signal guiding system and switching network.
As shown in figure 8, setting the simulation multiport memory body has 0-99 100 addresses, be divided into the 1st to the 4th 4 are only
Vertical memory block.Each memory block is the memory cell array of the row of 1 row 25, with address wire 1 to address wire 25 (as schemed
8 show WL1-WL25).
The address set-up mode of memory block is：1 address is set in the first row of the 1st memory block, successively at each
The first row of memory block is placed, until being booked after whole memory blocks, sets next in the second row of the 1st memory block again
Individual address.
Under such arrangement mode, the q rows of the n-th memory block (n and q are positive integer, q span for 1 to
Last column Q, n of memory block span be 1 to last memory block N) first memory cell it is corresponding
Address is：(q-1)×N+(n-1).In another embodiment, if desired comprising more address, it can continue to use upper
Address set-up mode is stated, makes memory cell array that there are more row, such as memory cell array of the row of 2 row 25.
In the present embodiment, the address wire selecting module 500 is made up of that (including selector 1 is to choosing Q selector 501
Select device Q).N-1 address wire selecting module 500 is connected with the corresponding 1st to N-1 memory blocks respectively, is arranged on adjacent
Between two memory blocks.The selector 501 is alternative selector, including selects control signal input, an output
End, input 1 and input 0.
Wherein, the output end of selector 501 is connected with the address wire of preceding memory block, two inputs respectively with
Selector 501 in the one's own profession of memory block afterwards and the address wire connection of lastrow, same address wire selecting module is total to
Control signal is selected with identical.It is such, except with addition to the N memory blocks that row decoder module 200 is connected, the selector
501 can according to the selection control signal sel_n of input select output end export be input 1 or input 0 value, from
And realize the guiding of Continuity signal.For example, input 1 is exported to output end the (the such as the 3rd when input selection control signal value is 1
Memory block will be by selector, into the address wire 2 of the 2nd memory block in the Continuity signal (address 2) of the 1st row), and input
When selection control signal value is 0, input 0 is exported to output end,.
In addition, the output coupling of the input 1 of selector 1 and row decoder Q.That is, in previous memory block for most
Latter row address line conducting, when selection control signal value is 1, Continuity signal will be directed into the 1st row of next memory block
Address wire.For example, the address 98 of the 3rd memory block is turned on, the selection control signal that selector is received is selection Continuity signal
When being into next row address line of next memory block, selector then guides Continuity signal to the 1st row of the 2nd memory block
Address wire (i.e. address 1 is turned on).
When using the memory structure shown in Fig. 8, the specific control configuration mode tool of the simulation multiport memory body
Body is as follows：
1) to read-write operation signal rwen1-rwen4 distribution：
In the present embodiment, can be according to the binary signal addr [1 of one two:0] come determine 4 memory blocks with
Matching relationship between read-write operation signal rwen1-rwen4, signal addr [1:0] specific distribution is as shown in Table 1：
Form 1
Binary signal addr [1:0] specific value is determined by the address signal addr inputted.addr[1:Taking 0]
It is worth the integer that scope is 0-3, the quantity with memory block is corresponding.It will be appreciated by persons skilled in the art that can also basis
The number change of memory block, configures the binary signal of more long number to determine its relations of distribution.For example, with 8 storages
During block, the span of the binary signal is 0-7, it is necessary to the binary signal of 3.
2) to selection control signal sel_n configuration：
The selection control signal can also be according to signal addr [1:0] determine, its specific rules is to include：Work as addr
[1:When 0]=1, the selection control signal of the 1st address wire selecting module input is sel_1=1, and other situations then take 0；Work as addr
[1:When 0]=2, the selection control signal sel_2=1 of the 2nd address wire selecting module input, other situations then take 0；Work as addr
[1:When 0]=3, the selection control signal sel_3=1 of the 3rd address wire selecting module input, other situations then take 0.Work as address wire
When the selection control signal that selecting module 500 is inputted is 1, the selection of selector 501 for belonging to the address wire selecting module 500 will be defeated
Enter the guiding of end 1 to output end.
The above-mentioned collocation method to selecting control signal se_l can also be further generalized to N number of memory block
Used in situation.That is, when using simulation N-port memory body mutually isostructural with memory body shown in Fig. 8, selection control is believed
Number sel_n collocation method is：(such as n-th deposits memory block where the memory cell that determination address signal addr is pointed to first
Storage area block).Then, the selection signal sel_n of the corresponding nth address line options module of the n-th memory block value is made to take 1, it is other
The value of selection signal of address wire selecting module take 0.
3) it is right between write-in FPDP wdata1-wdata4, read data ports rdata1-rdate4 and memory block
The configuration that should be related to：
It is the data that the n-th memory block writes to set wdata_bank (n), and rdata_bank (n) reads for the n-th memory block
The data taken.
The switching network 600 matches memory block and write-in FPDP wdata1- by rule as described below
Wdata4 and read data ports rdata1-rdate4：
For wdata1-wdata4：Then there are wdata1=wdata_bank (addr [1:0]+1)；Wdata2=wdata_
bank(addr[1:0]+2)；Wdata3=wdata_bank (addr [1:0]+3)；Wdata4=wdata_bank (addr [1:
0]+4)。
For read data ports rdata1-rdate4：Then there are rdata1=rdata_bank (addr [1:0]+1)；
Rdata2=rdata_bank (addr [1:0]+2)；Rdata3=rdata_bank (addr [1:0]+3)；Rdata4=
rdata_bank(addr[1:0]+4)。
addr[1:0]+n is the numbering of correspondence memory block.In the present embodiment, maximum numbering is 4.If addr [1:
0] when+n is more than 4, then 1 is recycled to successively and is recalculated.
Pass through above-mentioned configuration step, it may be determined that operation to be performed is needed in each memory block, and determine to write data
Port wdata1-wdata4, read data ports rdata1-rdate4 and memory block corresponding relation, orderly performs reading
Write operation.
The course of work to the simulation multiport memory body shown in Fig. 8 is described in detail with reference to embodiments.Figure 10
For the method flow diagram of simulation Multiport approach provided in an embodiment of the present invention.Method shown in application drawing 10 can realize Fig. 7
Or the simulation multiport memory body shown in Fig. 8, make memory body under the hardware condition of single port, with multiport memory body
It is convenient.
Embodiment 1：
If in the application environment shown in Fig. 3, processor 20 needs to perform on this four addresses of the address 2-5 of memory body 10
Read/write operation.Wherein, performed on address 2 and 3 and perform write operation on the address of read operation, 4 and 5.
As shown in Figure 10, memory body receives a data read write command first.The reading and writing data instruction includes：Believe address
Number and read-write operation signal (step 100).In embodiment 1, the reading and writing data instruction of the simulation multiport memory body can
With including：The address signal addr [6 of one 7:0]=2 (decimal system expression), four read-write control signals (wherein rwen1 and
Rwen2 is 1, rwen3 and rwen4 is 0), write-in FPDP wdata3 and wdata4 receives two write-in data, are respectively written into
Address 4 and 5, and distinguish from rdata1 and rdata2 the reading data of OPADD 2 and 3.
Then, Continuity signal (step 200) is exported in corresponding row decoder according to the address signal.I.e. according to address
Signal addr [6:2], Continuity signal is exported in row decoder 1 after the row decoder module 200 is decoded, other decoders export nothing
Imitate signal.
Memory controller 100 is according to address signal addr [6:2], corresponding binary signal addr [1 is determined:0]=
2.Then according to form 1, using control signal wire ctrl1-ctrl4 respectively by read-write control signal rwen1, rwen2, rwen3
And rwen4 is assigned in the module for reading and writing 300 of correspondence memory block.That is, rwen3 is exported to the 1st memory block by ctrl1
Block, rwen4 is exported to the 2nd memory block by ctrl2, and rwen1 is transmitted to the 3rd memory block by ctrl3, and rwen2 passes through
Ctrl4 is transmitted to the 4th memory block.
As shown in Figure 10, after output Continuity signal, the Continuity signal can be made to input to each memory block correspondence
Address wire, conducting correspondence row memory cell (step 300).In embodiment 1, according to input addr [1:0]=2, it is determined that
The selection control signal sel_2 of 2nd address wire selecting module is 1, and the selection control signal of other address wire selecting modules is 0
And export.Such, Continuity signal is turned on after the 1st row of the 4th and the 3rd memory block, in the guiding of the 2nd address wire selecting module
Under, turn on the 2nd row of the 2nd and the 1st memory block (such as Fig. 8 thick frame of black is shown).
Due to different memory blocks, it is necessary to according to the read-write operation signal, control the memory cell to perform
Respective operations (step 400).That is, the module for reading and writing 300 can be held according to read-write control signal in corresponding memory block
Row read-write operation.In embodiment 1, module for reading and writing 300 performs write operation in the 1st and the 2nd memory block, and the 3rd and the 4th
Memory block performs read operation.
Finally, in addition it is also necessary to by the address signal, determine the matching relationship of memory block and data input output ports
(step 500).In embodiment 1, it can be completed by the switching network 600.According to addr [1:0]=2, each switching network 600
By above-mentioned pre-defined rule, the data that read operation is obtained will be performed in the 3rd and the 4th memory block, exchange to rdata1 and
Rdata2 is exported.Also, two writing for writing address 4 and 5 that FPDP wdata3 and wdata4 are received will be write
Enter data to exchange respectively into the module for reading and writing 300 of the 1st and the 2nd memory block, write the 1st and the 2nd memory block.
Embodiment 2：
If in the application environment shown in Fig. 3, processor 20 needs to hold on this four addresses of the address 98-1 of memory body 10
Row read-write operation.Wherein, read operation, address 0 and 99 are performed on address 98 and 1 and performs write operation on address.
The reading and writing data instruction of the simulation multiport memory body includes：Address signal addr [6:0]=6 ' b110_0010
(binary expression)=98 (decimal system expression), four read-write control signals (are respectively rwen1=1, rwen2=0, rwen3=
0 and rwen4=1).
Memory controller 100 is according to address signal addr [6:0], corresponding binary signal addr [1 is determined:0]=
2 ' b10=2.Then according to form 1, using control signal wire ctrl1-ctrl4 respectively by read-write control signal rwen1,
Rwen2, rwen3 and rwen4 are assigned in the module for reading and writing 300 of correspondence memory block.That is, rwen3 is exported by ctrl1
To the 1st memory block, rwen4 is exported to the 2nd memory block by ctrl2, and rwen1 is transmitted to the 3rd memory block by ctrl3
Block, rwen2 is transmitted to the 4th memory block by ctrl4.That is, write operation is sent by ctrl2 and ctrl3 to module for reading and writing
Control signal, read operation control signal is sent to module for reading and writing by ctrl1 and ctrl4.
According to address signal addr [6:2]=5 ' b11000=24, after being decoded through space decoder module, the decoding of the 25th address
Device exports Continuity signal, and other address decoder output invalid signals (can set the value of Continuity signal as 1, the value of invalid signals
For 0).
The address wire selecting module 500 is according to addr [1:0]=2, the selection of the 2nd address wire selecting module is made to control letter
Number sel_2 is 1, and the selection control signal of other address wire selecting modules is 0.It is such, the 25th row of the 4th memory block
Continuity signal is directed to the 25th row address line of the 3rd memory block by memory cell conducts, the 3rd address wire selecting module.2nd ground
The Continuity signal that the selector 501 of location line options module then exports the 25th address decoder, is directed to the of the 2nd memory block
On 1 row address line, so as to make the 1st line storage unit of the 2nd memory block turn on, the 1st address wire selecting module will further be led
Messenger is guided to the 1st row address line of the 1st memory block (the thick frame of black as shown in Figure 9 is shown).
According to addr [1:0]=2, the switching network 600 can be exchanged to wdata1 based on above-mentioned preset rules
Wdata_bank3, wdata2 exchange to wdata_bank4, and wdata3 exchanges to wdata_bank1 and wdata4 is exchanged to
wdata_bank2.Because read-write operation instruction performs read operation to the 1st memory block and the 4th memory block, wdata2 and
Wdata3 can be ignored.Also, rdata_bank3 is exchanged into rdata1, rdata_bank4 exchanges to rdata2, rdata_
Bank1 exchanges to rdata3 and rdata_bank2 exchanges to rdata4.Due to read-write operation instruction to the 2nd memory block and
3rd memory block performs write operation, and rdata1 and rdata4 can be ignored.
Situation is guided to meet the Continuity signal of embodiment 2, as shown in Figure 8, it is necessary to which Continuity signal guiding system makes
With connecting line across whole row address decoding module link address decoder 25 and the first selection of each address wire selecting module
The input 1 of device.
The simulation multiport memory body that Fig. 9 provides for another embodiment of the present invention.As shown in figure 9, above-mentioned to avoid setting
Across the big connecting line of length, an extra row decoder 25 can also be set in the top of row decoder 1.It is extra by this
The row decoder 25 of setting, can be easy to implement the execution of address wire selecting module and guide the Continuity signal of last column to first
Capable operation, it is not necessary to which longer connecting line is set.
Simulation multiport memory body provided in an embodiment of the present invention, can using on the premise of single-port memory cell,
The effect of simulation multiport is realized, within a clock cycle, is performed by a read operation to memory body to continuous N
The read-write operation of individual address.The simulation multiport memory body can the memory cell based on less port, taking less chip
In the case of area, the facility (perform time short and power saving) compared with multiport memory body is obtained.
The signal configuration rule that those skilled in the art disclose according to above-described embodiment, in further embodiments, works as mould
Intend multiport memory body when there is more memory blocks, such as 6,8 or more, to simulate more port numbers
When, the more signals of digit can be used to set up the allocation table similar with the embodiment of the present invention, and provide corresponding control letter
Number rule.
Professional should further appreciate that, each example described with reference to the embodiments described herein
Multiport simulation steps (the reading and writing data mode of simulation multiport as shown in Figure 10), can be soft with electronic hardware, computer
Part or the combination of the two are realized, in order to clearly demonstrate the interchangeability of hardware and software, have been pressed in the above description
The composition and step of each example are generally described according to function.These functions are performed with hardware or software mode actually,
Depending on the application-specific and design constraint of technical scheme.Professional and technical personnel can be used each specific application
Distinct methods realize described function, but this realization is it is not considered that beyond the scope of this invention.Described computer
Software can be stored in computer read/write memory medium, and the program is upon execution, it may include such as the embodiment of above-mentioned each method
Flow.Wherein, described storage medium can be magnetic disc, CD, read-only memory or random access memory etc..
Embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize this
Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations
Technical field, is included within the scope of the present invention.
Claims (11)
1. one kind simulation multiport memory body, including：Data input output ports, memory controller, module for reading and writing and row
Decoder module, it is characterised in that also include：
1st memory block is to N memory blocks, and the memory block is the memory cell array of P row Q rows；Each memory block
In be connected to the selection line of the memory cell of a line in same address wire, each memory block has Q address wire, N, P and Q
For equal positive integer；
The row decoder module includes row decoder 1 to row decoder Q Q row decoder；The row decoder module is deposited with n-th
The corresponding address wire connection of storage area block；The row decoder module is under the configuration of the memory controller, order correspondence row solution
Code device output Continuity signal turns on the address wire of n-th memory block；N is the positive integer between 1-N；
Continuity signal guides system, and the Continuity signal guiding system is used to guide the Continuity signal to except the n-th memory block
Outside block, remaining corresponding address wire of each memory block；
Switching network, the switching network is connected by the module for reading and writing with N number of memory block, is matched according to predetermined exchange regulation
The memory block and data input output ports.
2. simulation multiport memory body according to claim 1, it is characterised in that set the simulation multiport memory body tool
There is 0-K K address, each memory cell has unique address；
First access unit address of the q rows of the n-th memory block be：(q-1)×N+(n-1)；N be 1 between N just
Integer, q is 1 to the positive integer between Q；Last access unit address of N memory blocks is K.
3. simulation multiport memory body according to claim 1, it is characterised in that the Continuity signal guides system bag
Include：N-1 address wire selecting module being correspondingly arranged with the 1st memory block to N-1 memory blocks；
The address wire selecting module includes selector 1 to selector Q Q selector, and the selector selects for alternative
Device；
The address wire q connections of selector q output end and corresponding memory block；Selector q two inputs respectively with row
Decoder q and row decoder q+1 couplings；Q is 1 to the positive integer between Q；
Wherein, the input of selector 1 is coupled with row decoder Q and row decoder 1 respectively.
4. simulation multiport memory body according to claim 1, it is characterised in that the Continuity signal guides system bag
Include：N-1 address wire selecting module being correspondingly arranged with the 1st memory block to N-1 memory blocks；
The address wire selecting module includes selector 1 to selector Q Q selector, and the selector selects for alternative
Device；
The address wire q connections of selector q output end and corresponding memory block；Selector q two inputs respectively with row
Decoder q and row decoder q+1 couplings；Q is 1 to the positive integer between Q；
Wherein, the row decoder module is also arranged on institute including extra row decoder a Q, the extra row decoder Q
State by row decoder 1, the input of the selector 1 is coupled with the extra row decoder Q and row decoder 1 respectively.
5. simulation multiport memory body according to claim 1, it is characterised in that the data input output ports are at least
Including：
Address signal input port, N number of write-in FPDP, N number of read data ports and N number of read-write operation port；N is institute
State the port number of simulation multiport memory body.
6. simulation multiport memory body according to claim 5, it is characterised in that the switching network includes several and institute
Switching network 1 that memory block is correspondingly arranged is stated to switching network N；
The switching network is according to predetermined exchange regulation, selection correspondence memory block and said write FPDP and reading number
According to port match.
7. a kind of method for simulating multiport, applied to the memory body of simulation multiport as claimed in claim 1, its feature exists
In, including：
A data read write command is received, the reading and writing data instruction includes：Address signal and read-write operation signal；
Continuity signal is exported in corresponding row decoder according to the address signal；
According to the address signal, the Continuity signal is made to input address wire corresponding to each memory block, conducting correspondence row
Memory cell；
According to the read-write operation signal, the memory cell is controlled to perform respective operations；
By the address signal, the matching relationship of N number of memory block and data input output ports is determined.
8. method according to claim 7, it is characterised in that methods described also includes：
Data are write to the 1st row of N number of memory block successively according to address；The address includes 0-K K address；
After the 1st row write of all memory blocks enters to finish, data are write to the 2nd row of N number of memory block successively again；
Above-mentioned data write operation is repeated until last address K of N memory blocks is written into.
9. method according to claim 8, it is characterised in that described according to the address signal, makes the Continuity signal
Input to the corresponding address wire of each memory block, the memory cell of conducting correspondence row is specifically included：
Row decoder q exports Continuity signal to the address wire q of N memory blocks, makes the memory cell conducts of q rows；
The Continuity signal is made to pass sequentially through some selectors, into N-1 memory blocks to the 1st memory block；
When the Continuity signal is from currently stored block into next memory block, next deposit is entered by selector selection
The current row address line or next row address line of storage area block, q are the positive integer between 1-Q.
10. method according to claim 9, it is characterised in that the Continuity signal enters next from currently stored block
During memory block, select to enter the current row address line or next row address line of next memory block by the selector, tool
Body includes：
Address signal is parsed, the n-th memory block corresponding with address signal is obtained；
To the corresponding selector output first choice signal of the n-th memory block；The first choice signal is control Continuity signal
Into the selection signal of next row address line；
The second selection signal is inputted to other selectors, second selection signal enters current row address for control Continuity signal
The selection signal of line.
11. method according to claim 10, it is characterised in that methods described also includes：
During selector output first choice signal corresponding to the n-th memory block, the Continuity signal that row decoder Q is exported draws
It is directed at the address wire 1 of the n-th memory block.
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