CN107123407A - A kind of drive circuit system and the liquid crystal display comprising the drive circuit system - Google Patents
A kind of drive circuit system and the liquid crystal display comprising the drive circuit system Download PDFInfo
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- CN107123407A CN107123407A CN201710471291.6A CN201710471291A CN107123407A CN 107123407 A CN107123407 A CN 107123407A CN 201710471291 A CN201710471291 A CN 201710471291A CN 107123407 A CN107123407 A CN 107123407A
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- 239000004973 liquid crystal related substance Substances 0.000 title claims description 32
- 230000005611 electricity Effects 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 238000013499 data model Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 235000018734 Sambucus australis Nutrition 0.000 description 2
- 244000180577 Sambucus australis Species 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- OGFXBIXJCWAUCH-UHFFFAOYSA-N meso-secoisolariciresinol Natural products C1=2C=C(O)C(OC)=CC=2CC(CO)C(CO)C1C1=CC=C(O)C(OC)=C1 OGFXBIXJCWAUCH-UHFFFAOYSA-N 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of drive circuit system, including timing controller, grid drive chip and switch element, timing controller includes producing the first output end of the first control signal, wherein：The Enable Pin of first output end connection grid drive chip and the control end of switch element, the input access cut-in voltage of switch element, the output end of switch element connect the control end of grid drive chip；First control signal includes the open signal and the enable signal positioned at the second time interval for being located at very first time interval, and in the very first time is interval, whether open signal turns on for controlling switch element；In the second time interval, enable whether signal turns off output for control gate driving chip；The effective voltage of open signal is differed with enabling the effective voltage of signal.Implement the present invention, can by enabling signal necessary to grid drive chip, enable control signal this 2 signal line and merge into one, realize panel narrow frame.
Description
Technical field
The present invention relates to technical field of liquid crystal display, and in particular to a kind of drive circuit and the liquid crystal comprising the drive circuit
Display.
Background technology
In recent years, liquid crystal display (Liquid Crystal Display, LCD) technology is with its low-power consumption, Low emissivity, light and handy
Easily unique advantage is popularized rapidly.Wherein, narrow frame panel technology is because that can simplify panel making technology, improve liquid crystal
The integrated level of panel and favored by people.
To shorten the frame of liquid crystal display panel, prior art is typically the raster data model core that will be controlled in liquid crystal display
Some functions of piece (Gate driver) are set on COF (Chip On Flex or Film, chip on film), but due to grid
Control signal needed for the driving chip normal work of pole must be provided by glass end cabling, and the way is shortening panel border
The validity of aspect is not high, it is easy to reaches the shortening limit.
The content of the invention
The embodiment of the present invention provides a kind of drive circuit and the liquid crystal panel comprising the drive circuit, by by raster data model
Enabling signal (STV) required for chip normal work, enable control signal this 2 control signals and be multiplexed, reduction one
Signal wire, can effectively shorten the frame region of liquid crystal display, realize panel narrow frame.
First aspect of the embodiment of the present invention provides a kind of drive circuit system, and the drive circuit system includes sequential control
Coremaking piece, grid drive chip and switch element, the timing controller include the first output end, wherein：
First output end of the timing controller connects the Enable Pin of the grid drive chip and described opened
The control end of element is closed, the input access cut-in voltage of the switch element, the output end connection of the switch element is described
The control end of grid drive chip；
First output end of the timing controller is used to produce the first control signal, first control signal
It is interval in the very first time including the open signal and the enable signal positioned at the second time interval positioned at very first time interval
Interior, the open signal is used to control whether the switch element turns on, when the switching elements conductive, the cut-in voltage
Start to export the first row gate drive signal for triggering the grid drive chip；It is described in second time interval
Enabling signal is used to control whether the grid drive chip turns off output；The effective voltage of the open signal is enabled with described
The effective voltage of signal is differed.
Wherein, the switch element includes first switch pipe, and first output end of the timing controller is connected
The grid of the first switch pipe, the source electrode of the first switch pipe accesses the cut-in voltage, the leakage of the first switch pipe
Pole connects the control end of the grid drive chip；
In the very first time is interval, when the open signal is effective, the effective voltage of the open signal is more than
The cut-in voltage.
Wherein, the switch element includes bleeder circuit and second switch pipe, the input connection institute of the bleeder circuit
First output end of timing controller is stated, the output end of the bleeder circuit connects the grid of the second switch pipe,
The source electrode of the second switch pipe accesses the cut-in voltage, and the drain electrode of the second switch pipe connects the grid drive chip
Control end；
In the very first time is interval, when the open signal is effective, the output voltage of the bleeder circuit is more than
The cut-in voltage.
Wherein, the bleeder circuit includes the first divider resistance and the second divider resistance, the of first divider resistance
One end is connected to first output end of the timing controller, is opened described in the second end connection of first divider resistance
Close the grid of pipe and the first end of the second divider resistance, the second end ground connection of the divider resistance.
Wherein, in second time interval, when the enable signal is effective, the enable signal is used to control institute
State grid drive chip shut-off output.
Wherein, the timing controller also includes the second output end, and second output end connects the raster data model
The Clock control end of chip, second output end is used to produce clock signal；In second time interval, make when described
During energy invalidating signal, the grid drive chip exports each row gate drive signal according to the clock signal.
Wherein, in the very first time is interval, the open signal continuously effective.
Wherein, the very first time interval includes the first sub- time interval and the second sub- time interval, the open signal
In the first sub- time interval effectively, invalid in the described second sub- time interval, the second sub- time interval is described the
After one sub- time interval.
Wherein, the effective voltage of the open signal is more than the effective voltage of the enable signal.
Second aspect of the embodiment of the present invention is there is provided a kind of liquid crystal display, including as described in the first aspect of the invention
Drive circuit system.
The drive circuit system that first aspect according to embodiments of the present invention is provided, insertion switch element is to the SECO
First control signal that first output end of chip is produced is multiplexed, and electricity is opened in the input access of the switch element
Pressure, the output end of the switch element connects the control end of the grid drive chip, and first control signal includes being located at
The very first time interval open signal and the enable signal positioned at the second time interval, it is described in the very first time is interval
Open signal is used to control whether the switch element turns on；In second time interval, the enable signal is used to control
Make whether the grid drive chip turns off output, can so be substituted with first control signal and enter grid in the prior art
2 control signal wire-enabling signals, enable control signals, so reduce a signal line, contract necessary to driving chip
The short frame region of liquid crystal panel, but the normal work of grid drive chip is not influenceed, implementing the embodiment of the present invention can have
Effect realizes panel narrow frame.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the accompanying drawing used required in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is the timing diagram of 3 control signals necessary to grid drive chip normal work in the prior art；
Fig. 2 is the first control signal, clock signal disclosed in the embodiment of the present invention, and liquid crystal panel the 1st, 2, N rows
The timing diagram of gate drive signal；
Fig. 3 is a kind of schematic diagram of drive circuit system disclosed in the embodiment of the present invention；
Fig. 4 is frame change of the liquid crystal panel before and after using drive circuit system disclosed by the invention；
Fig. 5 is the first control signal, clock signal disclosed in another embodiment of the present invention, and liquid crystal panel the 1st, 2, N
The timing diagram of capable gate drive signal；
Fig. 6 is the schematic diagram of another drive circuit system disclosed in the embodiment of the present invention；
Fig. 7 is the schematic diagram of another drive circuit system disclosed in the embodiment of the present invention；
Fig. 8 is the schematic diagram of another drive circuit system disclosed in the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in embodiment of the present invention, the technical scheme in embodiment of the present invention is carried out clear
Chu, it is fully described by.Obviously, described embodiment is a part of embodiment of the present invention, rather than whole embodiment party
Formula.Based on the embodiment in the present invention, those of ordinary skill in the art are obtained on the premise of creative work is not made
The every other embodiment obtained, should all belong to the scope of protection of the invention.
In addition, the explanation of following embodiment is with reference to additional diagram, the spy implemented to illustrate the present invention can be used to
Determine embodiment.The direction term being previously mentioned in the present invention, for example, " on ", " under ", "front", "rear", "left", "right", " interior ",
" outer ", " side " etc., are only the directions with reference to annexed drawings, therefore, and the direction term used is to more preferably, more clearly say
It is bright and understand the present invention, rather than indicate or infer the device or element of meaning and must have specific orientation, with specific side
Position construction and operation, therefore be not considered as limiting the invention.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or detachably connected, or integratedly be connected
Connect；Can mechanically connect；Can be joined directly together, can also be indirectly connected to by intermediary, can be in two elements
The connection in portion.For the ordinary skill in the art, the tool of above-mentioned term in the present invention can be understood with concrete condition
Body implication.
In addition, in the description of the invention, unless otherwise indicated, " multiple " are meant that two or more.If this
Occur the term of " process " in specification, it refers not only to independent process, when can not clearly be distinguished with other processes, as long as
It can realize that the effect desired by the process is then also included within this term.In addition, the numerical value represented in this specification with " ￣ "
Scope refers to the scope that the numerical value recorded before and after " ￣ " is included as minimum value and maximum.In the accompanying drawings, tie
The similar or identical unit of structure is indicated by the same numeral.
Thin Film Transistor-LCD (TFT Liquid Crystal Display, TFT-LCD) is that one kind utilizes TFT
Include multiple TFT being in array-like arrangement to produce voltage to control the display that liquid crystal molecule is turned to, in TFT-LCD.Often
Row TFT grid is connected with scan line (scan line), and the scanning drive signal of scan line is provided by grid drive chip,
It is responsible for certain a line TFT opening.Fig. 1 is 3 control signals necessary to grid drive chip normal work in the prior art
Timing diagram.Wherein, STV (Start Vertical) is the enabling signal of grid, is also the beginning of a two field picture, is mainly used for
Triggering grid drive chip starts to export the first row TFT gate drive signal.OE (Output Enable) is each row TFT grid
The output control signal of pole, the friendship for control gate driving chip adjacent rows TFT close/open in a liquid crystal display
Connect the stage to close the output of all rows, it is to avoid the situation that adjacent lines are opened simultaneously, further avoid data transmission fault.Clock
Signal CKV is Gate same period signal, is responsible for providing the work clock of grid drive chip internal digital circuit, is mainly used in
The rising edge of each clock cycle, opens a line TFT switch.And the friendship of the adjacent rows TFT risen in the 2nd row close/open
The stage is connect, all outputs are temporarily turned off by OE effect of signals.For example, after STV signals are opened, from clock signal first
The rising edge of individual clock cycle rises, and the gate drive signal that grid drive chip starts to export the first row (continues first clock
Cycle), and come interim in second rising edge of clock signal, stop output the first row gate drive signal.Clock signal exists
Second clock rising edge is between the 3rd rising edge clock, and OUT2 is exported, by that analogy.
From figure 1 it appears that STV signals only play a role during the first row TFT is opened, during effect with OE signals
Between it is different.Based on this, the embodiment of the present invention provides a kind of drive circuit system and the liquid crystal display based on the drive circuit system
Device, the line number signal of the transmission signal for reducing grid drive chip, solves the problem of liquid crystal panel frame is wider.Below
It is described in detail respectively.
Also referring to Fig. 2 and Fig. 3, Fig. 2 is the first control signal, clock signal disclosed in the embodiment of the present invention, and
Liquid crystal panel the 1st, 2, the timing diagram of the gate drive signal of N rows, Fig. 3 are a kind of drive circuit systems disclosed in the embodiment of the present invention
System.Drive circuit system described in the present embodiment, including timing controller (TCON) 11, grid drive chip 12 and
Switch element 13.Timing controller 11 is that grid drive chip 12 provides control signal necessary to its normal work.It is described
Timing controller 11 includes the first output end O1, wherein：The first output end O1 connections of the timing controller 11
The Enable Pin C2 of the grid drive chip 12 and the control end 131 of the switch element 13, the input of the switch element 13
Cut-in voltage VGH is accessed at end 132, and the output end 133 of the switch element 13 connects the control end of the grid drive chip 12
C1.Control end C1 can be the internal core circuit for being connected to grid drive chip.
The first output end O1 of the timing controller 11 is used to produce the first control signal, as shown in figure 3, institute
Stating the first control signal (STV+OE) is included positioned at very first time interval t1 open signal STV and positioned at the second time interval t2
Enable signal OE.In very first time interval t1, the open signal STV is used for whether controlling the switch element 13
Conducting.Wherein, when the open signal STV is effective, the switch element 13 can be turned on.The input of the switch element 13
Terminate into the cut-in voltage just can input to the control end C1 of the grid drive chip 12, for triggering grid drive
Dynamic chip 12 starts output the first row gate drive signal OUT1.In the second time interval t2, the enable signal OE
For controlling whether the grid drive chip 12 turns off output, wherein, (it is in adjacent two when the enable signal OE is effective
When row TFT is in switching phase), enabling signal OE can control the grid drive chip 12 to turn off all outputs.Wherein, it is described to open
The effective voltage for opening signal STV effective voltage and the enable signal OE is differed.
The timing controller 11 also includes the second output end O2, the second output end O2 connections raster data model
The Clock control end C2, the second output end O2 of chip 12 are for producing clock signal CKV.In the second time interval t2
Interior, when the enable signal OE is invalid, the grid drive chip 12 exports each row grid according to the clock signal CKV and driven
Dynamic signal.And in very first time interval t1, by the open signal STV effective influences, from the clock signal
The rising edge of CKV first clock cycle starts, and the clock signal CKV control gates driving chip 12 is in first clock
The first row gate drive signal of output high level in cycle, until just being turned off when being influenceed by the enable signal OE defeated
Go out.
Referring to Fig. 2, in very first time interval t1, the open signal STV continuously effectives.Wherein, it is described to open
The effective voltage of signal STV effective voltage and the enable signal OE is differed, and the effective voltage of the open signal STV
Differed with the dead voltage of the enable signal OE.Such as open signal STV effective voltage (such as 5V) is more than described enable
Signal OE dead voltage (such as 3.3V), also greater than the effective voltage (such as 0V) of the enable signal OE.Wherein, it is described to make
Energy signal OE dead voltage can be equal to the cut-in voltage VGH.
In very first time interval t1, since time point 1, the unlatching of the access of control end 131 of switch element 13
Signal STV can turn on switch element 13, the cut-in voltage VGH that the input 132 of switch element 13 is accessed can export to
The control end C1 of the grid drive chip 12, it is possible to trigger the grid drive chip 12 and start the grid drive of output the first row
Dynamic signal OUT1.By the startup triggering of the open signal STV in very first time interval t1, from the of the clock signal CKV
The rising edge of one clock cycle starts when time point 1 (i.e.) in Fig. 2, the clock signal CKV control gate driving chips
12 start to export the first row gate drive signal OUT1 of high level, until stopping the first row gate drive signal during time point 2
Output.And from time point 2, in the absence of the open signal STV, the control end C1 of naturally described grid drive chip 12 without
Cut-in voltage VGH is inputted.And time point 2 is in second rising edge of clock signal, the enable signal OE is effective, in low
Level state, the enable signal OE controls the grid drive chip 12 to turn off the output, now, although clock signal
CKV is in the 2nd rising edge, and the gate drive signal of the 2nd row should be exported, but is influenceed by signal OE is enabled, the grid of the 2nd row
Drive signal OUT2 is not exported temporarily, but grid drive chip 12 internal circuit still in normal work, when time point 3,
The enable signal OE switches to high level by low level, and now the enable signal OE is invalid, the 2nd row gate drive signal
OUT2 just starts output, and continues to the 3rd rising edge of the clock signal CKV, behind each row gate drive signal it is defeated
Go out by that analogy.
In the embodiment of the present invention, pass through one first control of the first output end O1 generations to the timing controller 11
Signal processed is multiplexed, and is classified as the open signal STV in very first time interval t1 and making positioned at the second time interval t2
Can signal OE, so can be in very first time interval t1, the open signal STV can control the switch element 13 to be
No conducting；In the second time interval t2, the enable signal OE can control whether the grid drive chip 12 turns off
Output, 2 controls necessary to entering grid drive chip in the prior art can be so substituted with first control signal and are believed
Number line-enabling signal, control signal is enabled, and do not influence the normal work of grid drive chip, so reduce a bars
Line (result is as shown in Figure 4), hence it is evident that shorten the frame region of liquid crystal panel, adds the effective display area of liquid crystal panel, real
Panel narrow frame can effectively be realized by applying the embodiment of the present invention.
Alternatively, the cut-in voltage VGH is certain value.
Alternatively, in the other embodiment of the present invention, first control signal, the timing diagram of clock signal also may be used
With as shown in Figure 5.First control signal (STV+OE) includes being located at very first time interval t1 open signal STV and is located at
Second time interval t2 enable signal OE, but in very first time interval t1, the open signal STV is not always
Effectively, but partly effectively.E.g., the very first time interval t1 included for the first sub- sub- times of time interval t11 and second
Interval (t1-t11), the open signal is effective in the first sub- time interval t11, the nothing in the described second sub- time interval
Effect, the second sub- time interval is after the described first sub- time interval t11.With Fig. 3 except that, described second son
In time interval (t1-t11), the open signal is invalid, it is impossible to which the switch element 13 is turned on into (such as described open signal
STV dead voltage is not more than the cut-in voltage VGH), the control end C1 of the grid drive chip 12 is without cut-in voltage VGH
Input.But due in the described second sub- time interval (t1-t11), in the absence of the enable signal OE, and clock letter is not reached
Number CKV second rising edge, the gate drive signal OUT1 of the first row is uninterruptedly normally exported.
Referring to Fig. 6, Fig. 6 is another drive circuit system disclosed in the embodiment of the present invention.Described in the present embodiment
Drive circuit system, as shown in fig. 6, drive circuit system shown in drive circuit system and Fig. 3 shown in the present embodiment
Overall architecture is essentially identical, specifically refer to the description to drive circuit system shown in Fig. 3 in above-described embodiment, no longer goes to live in the household of one's in-laws on getting married herein
State.
Further, its difference is, in the drive circuit system described in embodiment shown in Fig. 6, the switch
Element includes first switch pipe T1, the first output end O1 connections first switch pipe T1 of the timing controller 11
Grid, the source electrode of the first switch pipe T1 accesses the cut-in voltage VGH, the drain electrode connection institute of the first switch pipe T1
State the control end C1 of grid drive chip 12.Wherein, the first switch pipe T1 is the enhanced metal-oxide-semiconductor of N-channel；It is described to open letter
Number STV effective voltage is more than the cut-in voltage VGH (such as 3.3V).
The first control signal that the first output end O1 of the timing controller 11 is produced, its timing diagram can be as
Shown in Fig. 2 or Fig. 5, first control signal (STV+OE) includes the open signal STV and position positioned at very first time interval t1
In the second time interval t2 enable signal OE.The open signal STV can effectively the period in the very first time area
Between in t1, the enable signal OE can effectively the time be in the second time interval t2.
In very first time interval t1, when the open signal STV is effective, the open signal STV's is effective
Voltage is more than the cut-in voltage VGH (when i.e. first switch pipe T1 grid voltage is more than source voltage), the first switch
Pipe T1 is turned on, and the cut-in voltage VGH of the source electrode connection of the first switch pipe T1 is exported to the grid drive chip 12
Control end C1, with trigger the grid drive chip 12 start export the first row gate drive signal.It is interval by the very first time
The open signal STV effectively starts in t1, since the rising edge of first clock cycle of the clock signal CKV,
The clock signal CKV control gates driving chip 12 starts to export the first row gate drive signal OUT1 of high level, until
Second rising edge of clock signal arrives, and the enable signal OE effectively, stops the output of the first row gate drive signal.I.e.
It is ((t1-t11) section in such as Fig. 5), the nothing of the open signal STV within the open signal STV invalid periods to make
Imitate voltage and be not less than the cut-in voltage VGH (i.e. when the grid voltage of first switch pipe T1 has been not more than source voltage), it is described
First switch pipe T1 ends, and the output of the first row gate drive signal is not still influenceed.
In second time t2, the first switch pipe T1 is not turned on always, i.e. the voltage for enabling signal OE
(effective voltage or dead voltage) is no more than the cut-in voltage VGH；When the enable signal OE is effective, the enable letter
Number OE controls the shut-off of grid drive chip 12 output, and when the enable signal OE is invalid, the grid drive chip
12 export each row gate drive signal according to the clock signal CKV.
In the present embodiment, the effective voltage of the open signal STV is more than the cut-in voltage VGH, the open signal
STV effective voltage can be more than the dead voltage (such as 3.3V) of the enable signal OE, and the open signal STV's have
Imitate the effective voltage (such as 0V) that voltage is more than the enable signal OE.Wherein, the dead voltage for enabling signal OE can be with
Equal to the cut-in voltage VGH.But the dead voltage of the open signal STV however less than the cut-in voltage VGH.
, can be to SECO based on first switch pipe T1 introducing by implementing drive circuit system as shown in Figure 6
First control signal that first output end O1 of chip 11 is produced is multiplexed, and replacement enters raster data model core in the prior art
2 control signal wire-enabling signals that action time necessary to piece differs, control signal is enabled, so reduce one
Signal wire does not influence the normal work of grid drive chip again, hence it is evident that shortens the frame region of liquid crystal panel, adds liquid crystal
The effective display area of panel, panel narrow frame can effectively be realized by implementing the embodiment of the present invention.
Referring to Fig. 7, Fig. 7 is another drive circuit system disclosed in the embodiment of the present invention.Described in the present embodiment
Drive circuit system, as shown in fig. 7, drive circuit system shown in drive circuit system and Fig. 3 shown in the present embodiment
Overall architecture is essentially identical, specifically refer to the description to drive circuit system shown in Fig. 3 in above-described embodiment, no longer goes to live in the household of one's in-laws on getting married herein
State.
Further, its difference is, in the drive circuit system described in embodiment shown in Fig. 7, the switch
Element 13 includes bleeder circuit 131 and second switch pipe T2, and the input 132 of the bleeder circuit 131 connects the sequential control
The first output end O1 of coremaking piece 11, the output end 134 of the bleeder circuit 131 connects the grid of the second switch pipe T2
Pole, the source electrode of the second switch pipe T2 accesses the cut-in voltage VGH, and the drain electrode of the second switch pipe T2 connects the grid
The control end C1 of pole driving chip 12.Wherein, the second switch pipe T2 is the enhanced metal-oxide-semiconductor of N-channel；The open signal
STV effective voltage is more than the cut-in voltage VGH, and further, the effective voltage of the open signal STV is through the partial pressure
After the partial pressure of circuit 13, the voltage that the bleeder circuit 13 is exported is more than the cut-in voltage VGH.
The first control signal that the first output end O1 of the timing controller 11 is produced, its timing diagram can be as
Shown in Fig. 2 or Fig. 5, first control signal (STV+OE) includes the open signal STV and position positioned at very first time interval t1
In the second time interval t2 enable signal OE.In very first time interval t1, when the open signal STV is effective,
The output voltage of the bleeder circuit 131 is more than the cut-in voltage VGH, and (i.e. second switch pipe T2 grid voltage is more than its source
During pole tension), the second switch pipe T2 conductings, the cut-in voltage VGH of the source electrode connection of the second switch pipe T2 is defeated
Go out to the control end C1 of the grid drive chip 12, the grid drive of output the first row is started to trigger the grid drive chip 12
Dynamic signal.
Wherein, in very first time interval t1, the open signal STV can with continuously effective (as shown in Figure 2),
Can partly effectively (as shown in Figure 5).It is apparent that in very first time interval t1, when the open signal STV is invalid
When, the output voltage of the bleeder circuit 131 is less than or equal to the cut-in voltage VGH (i.e. described second switch pipe T2 grid
Pole tension is less than or equal to the voltage of its source electrode), the second switch pipe T2 cut-offs do not influence the first row raster data model to believe
Number output, i.e. the grid drive chip 12 according to the clock signal CKV export the first row gate drive signal, until
The arrival of second rising edge of clock signal is enabled signal OE effective influences by described in the second time interval t2.
In the second time interval t2, the output voltage of the bleeder circuit 131 is less than or equal to the unlatching electricity
VGH, the second switch pipe T2 is pressed to be not turned on always.When the enable signal OE is effective, the enable signal OE controls institute
The shut-off output of grid drive chip 12 is stated, and when the enable signal OE is invalid, the grid drive chip 12 is according to described
Clock signal CKV exports each row gate drive signal.
By implementing drive circuit system as shown in Figure 7, based on opening that bleeder circuit 131 and second switch pipe T2 are constituted
The introducing of element 131 is closed, the first output end O1 of timing controller 11 first control signal produced can be carried out
Multiplexing, control signal wire-startup that 2 action times necessary to replacement enters grid drive chip in the prior art differ
Signal, enable control signal, so reduce a signal line and do not influence the normal work of grid drive chip, hence it is evident that shorten
The frame region of liquid crystal panel, adds the effective display area of liquid crystal panel, and implementing the embodiment of the present invention can effectively realize
Panel narrow frame.
Referring to Fig. 8, Fig. 8 is another drive circuit system disclosed in the embodiment of the present invention.Described in the present embodiment
Drive circuit system, as shown in figure 8, drive circuit system shown in drive circuit system and Fig. 7 shown in the present embodiment
Overall architecture is essentially identical, specifically refer to the description to drive circuit system shown in Fig. 7 in above-described embodiment, no longer goes to live in the household of one's in-laws on getting married herein
State.
Further, its difference is, in the drive circuit system described in embodiment shown in Fig. 8, the partial pressure
Circuit 131 includes the first divider resistance R1 and the second divider resistance R2, and the first end of the first divider resistance R1 is connected to institute
The first output end O1 of timing controller 11 is stated, the second end of the first divider resistance R1 connects the second switch
The first end of pipe T2 grid and the second divider resistance R2, the second end ground connection of the divider resistance R2.Wherein, described second point
The voltage of piezoresistance R2 first end is that is, the voltage that the output end 134 of bleeder circuit 131 is exported in Fig. 7.
The embodiment of the present invention also provides a kind of liquid crystal display of the drive circuit system shown in any figure in-Fig. 8 including Fig. 2
Device.The description of the above-mentioned drive circuit system to shown in Fig. 2-Fig. 8 is refer to, be will not be repeated here.Such liquid crystal display
Frame it is narrower, effective display area domain is more.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means to combine specific features, structure, material or the feature that the embodiment or example are described
It is contained at least one embodiment of the present invention or example.In this manual, the schematic representation of above-mentioned term is differed
Surely identical embodiment or example are referred to.Moreover, specific features, structure, material or the feature of description can be any one
Combined in an appropriate manner in individual or multiple embodiments or example.
The drive circuit system and liquid crystal display provided above the embodiment of the present invention is described in detail, herein
In apply specific case the principle and embodiment of the present invention be set forth, the explanation of above example is only intended to side
The method and its core concept of the assistant solution present invention；Simultaneously for those of ordinary skill in the art, the think of according to the present invention
Think, will change in specific embodiments and applications, in summary, this specification content should not be construed as pair
The limitation of the present invention.
Claims (10)
1. a kind of drive circuit system, it is characterised in that including timing controller, grid drive chip and switch element,
The timing controller includes the first output end, wherein：
First output end of the timing controller connects the Enable Pin and switch member of the grid drive chip
The control end of part, the input access cut-in voltage of the switch element, the output end of the switch element connects the grid
The control end of driving chip；
First output end of the timing controller is used to produce the first control signal, and first control signal includes
Interval open signal and the enable signal positioned at the second time interval positioned at the very first time, in the very first time is interval,
The open signal is used to control whether the switch element turns on, and the cut-in voltage is used to trigger the grid drive chip
Start to export the first row gate drive signal；In second time interval, the enable signal is used to control the grid
Whether driving chip turns off output；Wherein, the effective voltage not phase of the effective voltage of the open signal and the enable signal
Together.
2. drive circuit system according to claim 1, it is characterised in that the switch element includes first switch pipe,
First output end of the timing controller connects the grid of the first switch pipe, the source electrode of the first switch pipe
Access the cut-in voltage, the control end of the drain electrode connection grid drive chip of the first switch pipe；It is described to open letter
Number effective voltage be more than the cut-in voltage.
3. drive circuit system according to claim 1, it is characterised in that the switch element includes bleeder circuit and the
Two switching tubes, the input of the bleeder circuit connects first output end of the timing controller, the partial pressure electricity
The output end on road connects the grid of the second switch pipe, and the source electrode of the second switch pipe accesses the cut-in voltage, described
The control end of the drain electrode connection grid drive chip of second switch pipe；
In the very first time is interval, when the open signal is effective, the output voltage of the bleeder circuit is more than described
Cut-in voltage.
4. drive circuit system according to claim 3, it is characterised in that the bleeder circuit includes the first divider resistance
With the second divider resistance, the first end of first divider resistance is connected to first output of the timing controller
End, the second end of first divider resistance connects the grid of the second switch pipe and the first end of the second divider resistance, institute
State the second end ground connection of divider resistance.
5. the drive circuit system according to claim any one of 1-4, it is characterised in that in second time interval
Interior, when the enable signal is effective, the enable signal is used to control the grid drive chip shut-off output.
6. the drive circuit system according to claim any one of 1-4, it is characterised in that the timing controller is also wrapped
The second output end is included, second output end connects the Clock control end of the grid drive chip, and second output end is used
In generation clock signal；In second time interval, when it is described enable invalidating signal when, the grid drive chip according to
The clock signal exports each row gate drive signal.
7. the drive circuit system according to claim any one of 1-4, it is characterised in that interval in the very first time
It is interior, the open signal continuously effective.
8. drive circuit system according to claim 1, it is characterised in that the very first time interval includes first period of the day from 11 p.m. to 1 a.m
Between interval and the second sub- time interval, the open signal in the first sub- time interval effectively, in the described second sub- time zone
Interior invalid, the second sub- time interval is after the described first sub- time interval.
9. the drive circuit system according to Claims 2 or 3, it is characterised in that the effective voltage of the open signal is big
It is more than the effective voltage of the enable signal in the effective voltage of the dead voltage of the enable signal, and the open signal.
10. a kind of liquid crystal display, it is characterised in that including the drive circuit system described in claim any one of 1-9.
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| CN201710471291.6A CN107123407B (en) | 2017-06-20 | 2017-06-20 | A kind of drive circuit system and the liquid crystal display comprising the drive circuit system |
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| CN201710471291.6A CN107123407B (en) | 2017-06-20 | 2017-06-20 | A kind of drive circuit system and the liquid crystal display comprising the drive circuit system |
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| CN109119045A (en) * | 2018-11-01 | 2019-01-01 | 惠科股份有限公司 | Display driving device, display device and display module |
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| Publication number | Publication date |
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| CN107123407B (en) | 2019-08-02 |
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