CN107005216B - Attenuator - Google Patents

Abstract

An attenuator for attenuating a signal is disclosed. The attenuator (100) comprises a differential input port (Inp; Inn) having a positive input node (Inp) and a negative input node (Inn) for receiving a signal; and a differential output port (Outp; Outn) having a positive output node (Outp) and a negative output node (Outn) for outputting the attenuated signal. The attenuator (100) further comprises a first switched resistor network (102) connected between the positive input node (Inp) and the positive output node (Outp); and a second switched resistor network (104) connected between the negative input node (Inn) and the negative output node (Outn). There is also a pair of compensation paths connected between the first and second switched resistor networks (102; 104) for cancellation of parasitic leakage thereof, wherein the first compensation path (106) is connected between the positive input node (Inp) and the negative output node (Outn), and the second compensation path (108) is connected between the negative input node (Inn) and the positive output node (Outp). The attenuator (100) further comprises a control circuit (110) for generating control signals for controlling the first and second switched resistor networks (102; 104).

Description

Attenuator

technical field

Embodiments herein relate to attenuators for attenuating signals. In particular, embodiments relate to radio frequency broadband step attenuators for attenuating radio frequency signals in electronic devices.

Background technique

An attenuator is a circuit used to continuously or stepwise control the amplitude of a signal. When the signal is gradually controlled by an attenuator, the attenuator is called a step attenuator. Attenuators or graded attenuators are widely used in various electronic devices, examples of which are as follows: in wireless communication devices (including, for example, multi-antenna systems in radio base stations for communication and positioning, user equipment or mobile devices and base stations), as well as in other general-purpose electronic circuits and equipment (such as automatic gain control circuits and measurement equipment, etc.), radio frequency transceivers or radio frequency front-ends. For radio frequency front ends, on-chip graded attenuators designed in complementary metal-oxide-semiconductor (CMOS) technology offer the advantages of small size, low cost, flexibility, and high levels of integration. There are some requirements for designing on-chip stepped attenuators, such as good linearity, low insertion loss, wide bandwidth, and accuracy in the attenuation step.

In Cheng, W. et al, A Wideband IM3 Cancellation Technique for CMOSAttenuators, IEEE International Solid-State Circuits Conference , 2012 and in Cheng, W. et al, A Wideband IM3 Cancellation Technique for CMOS π- and T-Attenuators, IEEE Journal of Solid-State Circuits , 2013, Vol. 48, NO. 2, the disclosed on-chip Pi-type and T-type stepped attenuators provide 6, 12, 18, and 24 dB of attenuation steps. However, the disclosed Pi-type and T-type stepped attenuators, when operating in a lower attenuation mode, that is, when the attenuation level is low, such as an attenuation step of 6 or 12 dB, especially when no attenuation is required, has a large insertion loss. A high insertion loss will reduce the required signal-to-noise ratio (SNR) and gain of the input signal. In addition, the disclosed Pi-type and T-type stepped attenuators also suffer from switching leakage that impairs the attenuation level of the input signal at high frequencies during the deep attenuation mode.

In Xiao, J. et al, A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner, IEEE Journalof Solid-State Circuits , 2007, Vol. 42, No.2, presented a possible solution for mobile digital television (DTV) tuners variable gain amplifier. Variable gain is achieved using capacitive attenuators and current steering transconductance stages. Although the variable gain amplifier presented provides gain and attenuation, it suffers from poor linearity due to the active device, ie, the transconductance stage. Poor linearity will result in poor frequency selectivity of the radio frequency front end, and thus degrade the required SNR, due to interference from other unwanted frequency signals.

SUMMARY OF THE INVENTION

It is therefore an object of embodiments herein to provide attenuators with improved performance.

According to one aspect of the embodiments herein, the object is achieved by an attenuator for attenuating a signal. The attenuator includes: a differential input port having a positive input node and a negative input node for receiving a signal; and a differential output port having a positive output node and a negative output node for outputting the attenuated signal. The attenuator also includes: a first switched resistor network connected between the positive input node and the positive output node; and a second switched resistor network connected between the negative input node and the negative output node. The attenuator also includes a pair of compensation paths for cancellation of parasitic leakage in the first and second switched resistor networks. The pair of compensation paths are connected such that the first compensation path is connected between the positive input node and the negative output node, and the second compensation path is connected between the negative input node and the positive output node. The attenuator also includes a control circuit for generating a control signal for controlling the first and second switched resistor networks.

Since the attenuator according to embodiments herein uses the pair of compensation paths, parasitic leakage in the first and second switched resistor networks is eliminated. The cancellation is achieved by cross-coupling the pair of compensation paths, that is, a first compensation path is connected between the positive input node and the negative output node, and a second compensation path is connected between the negative input node and the positive output node. In this way, any leakage signal at the positive input node is coupled to the negative output node so as to cancel any leakage signal at the negative output node. In the same way, any leakage signal at the negative input node is coupled to the positive output node so as to cancel any leakage signal at the positive output node. This results in good attenuation performance, especially at high frequencies and in deep attenuation stages. Furthermore, the switched resistor network is passive and therefore highly linear.

Accordingly, embodiments herein provide attenuators with improved performance, such as with respect to attenuation levels and linearity at high frequencies and in deep attenuation stages.

Description of drawings

Examples of embodiments herein are described in greater detail with reference to the accompanying drawings, in which:

FIG. 1 is a general block diagram of an attenuator according to embodiments herein.

Figure 2 is a schematic block diagram illustrating an attenuator with a Pi-type switched resistor network according to embodiments herein.

Figure 3 is a schematic block diagram illustrating an attenuator with a T-type switched resistor network according to embodiments herein.

FIG. 4 is a schematic diagram illustrating a switchable variable series resistor according to embodiments herein.

5 is a schematic diagram illustrating a switchable variable shunt resistor according to embodiments herein.

FIG. 6 is a schematic diagram illustrating a compensation path according to embodiments herein.

FIG. 7 is a simplified schematic diagram illustrating the equivalent circuit of the Pi-type switched resistor network in FIG. 2 .

Figure 8 is a graph showing the frequency response of an attenuator according to one embodiment herein.

FIG. 9 is a graph showing the frequency response of an attenuator according to another embodiment herein.

FIG. 10 is a diagram illustrating an example layout of a compensation inductor according to embodiments herein.

11 is a block diagram illustrating an electronic device in which embodiments herein may be implemented.

Detailed ways

Shown in FIG. 1 is a general view of an attenuator 100 for attenuating signals according to embodiments herein. The attenuator 100 includes a differential input port Inp/Inn having a positive input node Inp and a negative input node Inn for receiving signals, and a differential output port Outp/Outn having a positive output node Outp and a negative output node Outn for outputting attenuated signal.

The attenuator 100 also includes a first switched resistor network 102 connected between the positive input node Inp and the positive output node Outp, and a second switched resistor network 104 connected between the negative input node Inn and the negative output node Outn between. The first and second switched resistor networks 102/104 are configured to form the desired attenuation.

The attenuator 100 also includes a pair of compensation paths for the cancellation of parasitic leakage in the first and second switched resistor networks 102/104. As shown in FIG. 1, the first compensation path 106, referred to in FIG. 1 as neutralizing compensation NC 106, is connected between the positive input node Inp and the negative output node Outn, and the second compensation path 108 is referred to in FIG. 1 as NC 108, connected between the negative input node Inn and the positive output node Outp.

In addition, the attenuator 100 also includes a control circuit 110 for generating control signals for controlling the first and second switched resistor networks 102/104.

According to some embodiments, the control circuit 110 in the attenuator 100 may also be configured to generate a control signal for controlling the pair of compensation paths 106/108.

The control signals CtrlS, CtrlP and CtrlNC are generated by the control circuit 110 through the digital data interface. The first and second switched resistor networks 102/202 are controlled by control signals CtrlP and CtrlS so that the resistance values of the first and second switched resistor networks 102/202 are adjustable. The control signal CtrlNC is used to control the compensation paths 106/108.

According to some embodiments, the attenuator 100 may further include: a first pair of inductors L1a/L1b connected to the differential input ports Inp/Inn, and a second pair of inductors L2a/L2b connected to the differential output ports Outp/Outn. In these embodiments, the first and second switched resistor networks 102/104 are coupled to the differential input/output ports through the first and second pairs of inductors, respectively. The first and second pairs of inductors L1a/L1b, L2a/L2b are used to compensate for the bandwidth of the attenuator 100 . According to some embodiments, the first and second pairs of inductors are mutually coupled inductors having coupling coefficients M1 and M2, respectively.

According to one embodiment, the attenuator 100 may be implemented by the circuit shown in FIG. 2, wherein the first and second switched resistor networks 102/104 may be implemented by Pi-type switched resistor networks 202/204.

As shown in FIG. 2, each Pi-type switched resistor network 202/204 includes two switchable variable parallel resistors Rp and one switchable variable series resistor Rs.

According to one embodiment, the attenuator 100 may be implemented by the circuit shown in FIG. 3, wherein the first and second switched resistor networks 102/104 may be implemented by a T-type switched resistor network 302/304.

As shown in FIG. 3, each T-type switched resistor network 302/304 includes one switchable variable parallel resistor Rp and two switchable variable series resistors Rs.

According to some embodiments, the switchable variable series resistor Rs may be implemented by the circuit shown in FIG. 4 , where FIG. 4( a ) shows the symbol of the switchable variable series resistor Rs and FIG. 4( b ) An example structure of the switchable variable series resistor Rs is shown, and FIG. 4( c ) shows each branch of the switchable variable series resistor Rs in more detail.

As shown in FIG. 4(b), the switchable variable series resistor Rs includes one or more switched resistor branches 400, 401, . . . , 40n, the one or more switched resistor branches 400, 401, . Each of 401, . . ., 40n includes a resistor Rs ₀ , Rs ₁ , . . , Rs _n in series with the switch. The switchable variable series resistor Rs also includes a bypass path 40b.

As shown in Figure 4(c), for one or more switches, a bootstrap path comprising a capacitor in series with a resistor is connected between: the gate; and the drain or source , depending on the size of one or more switches. Using a guide path can effectively improve switching linearity. However, for smaller sized switches, the guide paths may not be needed, eg, in branch 400, there are no guide paths connected between: the gate; and the drain or source of the switch Ts ₀ .

As shown in Figure 4(c), bypass path 40b includes switch Tb, and a lead path including capacitor Cb in series with resistor Rb is connected between switch Tb: the gate; and the drain or source pole.

When the switchable variable series resistor Rs includes a plurality of switchable resistor branches 400, 401, . . . , 40n, the control signal CtrlS generated by the control circuit 110 includes a plurality of control signals Ctrls0, Ctrls1, . . . Ctrlsn, which controls the switches in each branch, where n is a positive integer. The control signal CtrlS also includes Ctrlspass for controlling the bypass path 40b.

According to some embodiments, the switchable variable shunt resistor Rp may be implemented by the circuit shown in FIG. 5 , where FIG. 5( a ) shows the symbol of the switchable variable shunt resistor Rp and FIG. 5( b ) An example structure of the switchable variable shunt resistor Rp is shown, and Figure 5(c) shows each branch of the switchable variable shunt resistor Rp in more detail.

As shown in Figure 5(b), the switchable variable parallel resistor Rp includes one or more switchable resistor branches 500, 501, . . . , 50m, and the switchable variable parallel resistor Rp also includes A resistor (RPb) connected in series with the switched resistor branches 500, 501, ..., 50m. Each of the one or more switched resistor branches 500, 501, ..., 50m includes a resistor _Rpo , Rp ₁ , ..., _Rpm in series with the switch.

As shown in Figure 5(c), for one or more switches, a lead path including a capacitor in series with a resistor is connected between the switches: the gate; and the drain or source, depending on The size of one or more switches. For example, for the smaller sized switch Tp ₀ in branch 500 , there is no lead path connecting between the following two of the switch Tp ₀ : the gate; and the drain or source.

When the switchable variable parallel resistor Rp includes a plurality of switchable resistor branches 500, 501, . . . , 50m, the control signal CtrlP generated by the control circuit 110 includes a plurality of control signals Ctrlp0, Ctrlp1, . . . Ctrlpm to control the switches in each branch, where m is a positive integer.

According to some embodiments, the compensation paths 106/108 may be implemented by the circuit shown in FIG. 6, wherein FIG. 6(a) shows the symbols of the compensation paths 106/108 and FIG. 6(b) shows the symbols of the compensation paths 106/108. Example structure, and Fig. 6(c) shows another example structure of compensation paths 106/108. As shown in Figures 6(b) and 6(c), each compensation path 106/108 includes one or more switched capacitor branches, and each switched capacitor branch includes and resistors Rnc, Rnc ₀ , Rnc ₁ , ..., Rnc _k capacitors Cnc, Cnc ₀ , Cnc ₁ , ..., Cnc _k connected in series. In bypass mode, the compensation path for eliminating parasitic leakage can be cut off in order to reduce insertion loss.

According to some embodiments, each switched capacitor branch in the compensation path 106/108 further includes capacitors Cnc, Cnc ₀ , Cnc ₁ , . . . , Cnc _k and resistors Rnc, Rnc ₀ , Rnc ₁ , . _Rnck switches connected in series.

When the compensation path 106/108 includes multiple switched capacitor branches, the control signal CtrlNC includes multiple control signals Ctrlnck, . . . , Ctrlnc1, Ctrlnc0 for controlling the switches in each branch, where k is greater than or equal to 0 Integer.

Implementation details, performance, and advantages of the attenuator 100 according to embodiments herein are described below. As described above, switched resistor networks 102/104 are used to set the desired attenuation. To illustrate the relationship between desired attenuation and resistor value, example design equations are derived for Pi-type switched resistor networks 202/204. A simplified equivalent circuit of the Pi-type switched resistor network 202/204 without the compensation path is shown in FIG. 7, where FIG. 7(a) shows the Pi-type switched resistor network 202/204, connected differentially, and Figure 7(b) shows its single-ended portion.

For simplicity, analyze the Pi-type switched resistor network 202/204 connected in a single-ended manner in Figure 7(b), with the input and output port impedances _RL =50 added to it. In ideal conditions for matching to the requirements, the switched resistor network 202/204 should match the input and output port impedances _RL = 50 ohm, ie:

When in matched conditions, the voltage gain vg is given by:

From matching requirements, given:

So Rs can be expressed as:

Substituting the Rs expression in (4) for Rs in the attenuation or gain expression (2), this gives:

（对于理想纯电阻器情况）。in

(for the ideal pure resistor case).

Rp can be written as a function of expected decay:

，以及VG是以dB为单位的所要求或期望的衰减。in

, and VG is the required or desired attenuation in dB.

It should be noted that the above formula is an example design formula for a Pi type switched resistor network, those skilled in the art will realize that the design formula will be different for a T type switched resistor network.

Returning to FIG. 4, there is shown the structure of the switchable variable series resistor Rs according to one embodiment herein. As described above, the switchable variable series resistor Rs includes the bypass path 40b as shown in the dashed box at the bottom of FIGS. 4(b) and 4(c). When there is no need to attenuate the input signal, the attenuator 100 is set to bypass mode and all switched resistor branches 400, 401, . . . , 40n are bypassed by opening switch Tb in bypass path 40b. The control signal CtrlSpass is set to logic high during bypass mode. As shown in Figure 4(c), in the bypass path 40b, a lead path including a capacitor Cb in series with a resistor Rb is connected between: the gate; and the drain or source of the switch Tb. The purpose of the capacitor Cb is to steer the gate voltage of the switch Tb by using the input signal at the drain or source of the switch Tb, and to keep the voltage between the gate and the drain or source close to that determined by the control signal Constant DC voltage provided by CtrlSpass. This means that the conduction resistor Ron of the MOS switch transistor Tb is close to constant, thus improving the linearity of the switch Tb. The resistor Rb inserted in the lead path is used to avoid increasing the capacitive load in the signal path, and also to reduce leakage caused by the parasitic capacitance of the switching transistor Tb. The resistor Rg is a resistor connected in series between the control node and the gate of the switching transistor Tb, and the time constant of RgCb should be much larger than the period of the lowest operating frequency. In this way, lower insertion loss for higher frequency input signals is achieved. In other decay modes, the control signal CtrlSpass is set to logic low, the switch Tb is turned off, and then the bypass path is disconnected.

Switched resistor branches 400, 401, . . . , 40n are used to include different attenuation settings for bypass mode. In bypass mode, all control signals Ctrls0, Ctrls1, . .

When in other attenuation settings, only some of the switched resistor branches 400, 401, . . . , 40n conduct and provide the resistance value Rs according to the expression given by Eq. (4). Due to silicon process variations, the resistance values of on-chip resistors can vary in the range ±25%. So in practice, more control bits can be added to adjust the resistance.

是电阻最小的电阻器，以及开关

是大小最大的开关。增大

的大小可减少开关

传导电阻Ron的影响，以便提高线性，但代价是在信号路径中引入较大寄生电容。因此，如图4（c）中所示，在这里用于提高线性的引导路径对于较大大小的开关更有效。然而，对于较小大小的开关，引导路径可能不需要。如从图4（c）所见，对于开关式电阻器分支400，没有用于开关Ts₀的引导路径。 _The resistors in the switched resistor branches ₄₀₀ , ₄₀₁ , . R/2 ⁿ . For the switched resistor branch 40n, it can be viewed as ²ⁿ branches of the unit resistor cell R in parallel. so

is the smallest resistance resistor, and the switch

is the largest switch. increase

size reduces switching

The effect of conduction resistance Ron in order to improve linearity, but at the cost of introducing large parasitic capacitance in the signal path. Therefore, as shown in Fig. 4(c), the guide paths used here to improve linearity are more effective for larger size switches. However, for smaller sized switches, the bootstrap path may not be needed. As can be seen from Figure 4(c), for the switched resistor branch 400, there is no lead path for the switch _Ts0 .

As shown in FIG. 5, for the switchable variable parallel resistor Rp, binary weighted resistors can also be used in the switched resistor branches 500, 501, . . . , 50m. In bypass mode, all switched resistor branches are disconnected, so insertion loss is minimized.

，而对于开关式电阻器分支500中的最小开关Tp₀，引导路径被忽略。In other decay modes, the value of Rp can be selected according to Eq. (6). As shown in Fig. 5(c), a pilot path is also optionally used depending on the size of the switch, eg a pilot path is used for the largest switch in the switched resistor branch 50m

, while for the smallest switch Tp ₀ in the switched resistor branch 500 , the pilot path is ignored.

In practice, parasitic leakages exist due to parasitic capacitances between the three nodes (ie gate, drain and source of switch Tb), and these leakages impair the attenuation settings in deep attenuation stages. Figure 8 shows the attenuation level Vs frequency for bypass mode and different attenuation stages, where the desired attenuation level is plotted in solid lines and the actual attenuation level due to parasitic capacitance is plotted in dashed lines. It can be seen that parasitic leakage due to parasitic capacitance destroys the desired attenuation level, especially at higher frequencies.

As shown in Figures 1-3, the attenuator 100 is of a differential configuration, which enables the addition of a pair of compensation paths NC 106/108 for neutralizing or eliminating leakage. Cancellation is achieved by cross-coupling the pair of compensation paths 106/108, that is, the first compensation path 106 is connected between the positive input node Inp and the negative output node Outn, and the second compensation path 108 is connected between the negative input node Inn and the positive output between nodes Outp. In this way, any leakage signal at the positive input node is coupled to the negative output node, thereby eliminating any leakage signal at the negative output node. In the same way, any leakage signal at the negative input node is coupled to the positive output node, thereby canceling any leakage signal at the positive output node. This results in good attenuation performance, especially at high frequencies and in deep attenuation stages, as shown in the solid line in Figure 8, where the slope of the attenuation level is the same for all stages after compensation.

As described above, the compensation paths 106/108 include one or more switched capacitor branches. As shown in Fig. 6(b), when only one switched capacitor branch is used to reduce insertion loss, the switching transistor is turned off in bypass mode, so the compensation path is disconnected from the switched resistor network. However, it should be noted that the switching transistors in the compensation path are optional, i.e. the compensation path may consist only of capacitors and resistors, and may be connected all the way to the switched resistors in bypass mode and other attenuation settings network.

In Figure 6(c), several switched capacitor branches are used, so this would give more freedom to adjust compensation for different attenuation settings or levels. Since this is a programmable approach, this also handles design errors and process variations due to inaccurate extraction of capacitor and resistor values in the design tool.

It can be seen from Figure 8 that the attenuation level has a slope along the frequency axis. This means that the insertion loss at higher frequencies is higher than at lower frequencies, which results in a narrower bandwidth of the attenuator. To increase the bandwidth, a pair of inductors with mutual coupling can be used at the input port and the output port. As shown in Figures 1-3, the first pair of inductors L1a/L1b are connected at the differential input ports Inp/Inn for resonating with the input parasitic capacitance at the desired frequency, and the second pair of inductors L2a/L2b are connected at the differential output Ports Outp/Outn are used to resonate with the output parasitic capacitance at the desired frequency. In this way, the slope of the attenuation level is reduced, and the bandwidth of the attenuator 100 is expanded. This is illustrated in Figure 9, where the solid curve is the frequency response, that is, attenuation level Vs frequency, with inductor compensation, and the dashed line is the uncompensated frequency response.

An example layout of these two pairs of mutually coupled inductors is shown in Figure 10, where the layouts of L1a/L1b and L2b/L2b are designed in an interleaved fashion to save silicon area and increase the Q factor. Of course other types of split inductors can be used, but at the expense of a large silicon area and slightly more insertion loss.

Summarizing the discussion above, advantages of various embodiments of attenuator 100 include:

• Accurate attenuation levels or grading: The switched resistor network in Pi or T configuration enables adjustable resistance and also handles process variations, thus providing accurate attenuation levels and grading.

• Larger attenuation range: The compensation path is used to eliminate parasitic leakage for more accurate attenuation levels or grading at deep attenuation, so the attenuator 100 achieves a larger attenuation range.

· Higher linearity and low insertion loss: in some embodiments lead paths for larger sized switching transistors and for bypass paths to improve linearity and reduce insertion loss;

• Wide bandwidth: In some embodiments compensation inductors are used at the input port and output port to resonate with the input and output parasitic capacitances, respectively, thus expanding the bandwidth of the attenuator 100 .

The attenuator 100 according to the embodiments herein may be used in various electronic devices. Figure 11 shows a block diagram of an electronic device 1100, which may be, for example, a radio frequency transceiver, a radio frequency front end, a wireless communication device (such as a user equipment or a mobile device and/or a base station, a multi-antenna system in a radio base station), Or any general purpose electronic circuit or device (such as automatic gain control circuits, measurement equipment, etc.). The electronic device 1100 may include other units, wherein a processing unit 1110 is shown, which may interact with the control circuit 110 in the attenuator 100 for different attenuation settings or modes of operation.

Those skilled in the art will understand that although the compensation paths 104/106, the bypass path 40b, and the switching transistors in the switched resistor arrays Rs, Rp of the attenuator 100 shown in FIGS. 4-6 are field effect transistors (FETs) , but any other types of transistors such as metal oxide semiconductor FETs (MOSFETs), junction FETs (JFETs), bipolar junction transistors (BJTs), etc. may be included in the attenuator 100 . When the word "comprising" is used, it should be construed as non-limiting, that is, it means "consisting of at least".

The embodiments herein are not limited to the preferred embodiments described above. Various alternatives, modifications and equivalents can be used. Accordingly, the above embodiments should not be considered as limiting the scope of the invention, which is defined by the appended claims.

Claims (23)

1. An attenuator (100) for attenuating a signal, comprising: a differential input port (Inp; Inn) having a positive input node (Inp) and a negative input node (Inn) for receiving said signal; A differential output port (Outp; Outn) with a positive output node (Outp) and a negative output node (Outn) for outputting attenuated signals; a first switched resistor network (102) connected between the positive input node (Inp) and the positive output node (Outp); a second switched resistor network (104) connected between the negative input node (Inn) and the negative output node (Outn); a pair of compensation paths for cancellation of parasitic leakage in said first and second switched resistor networks (102; 104), wherein a first compensation path (106) is connected between said positive input node (Inp) and between said negative output nodes (Outn), and a second compensation path (108) is connected between said negative input node (Inn) and said positive output node (Outp); and A control circuit (110) for generating control signals for controlling the first and second switched resistor networks (102; 104). 2. The attenuator (100) of claim 1, wherein the attenuator (100) further comprises a first pair of inductors (L1a; L1b) connected at the differential input ports (Inp; Inn) and at The second pair of inductors (L2a; L2b) connected to the differential output ports (Outp; Outn). 3. The attenuator (100) of any of claims 1-2, wherein the control circuit (110) is further configured to generate a control signal for controlling the pair of compensation paths (106; 108) . 4. The attenuator (100) of any of claims 1-2, wherein each of the first and second switched resistor networks (102; 104) is a Pi-type resistor network (202) 204), the Pi-type resistor network (202; 204) includes two switchable variable parallel resistors (Rp) and one switchable variable series resistor (Rs). 5. The attenuator (100) of any of claims 1-2, wherein each of the first and second switched resistor networks (102; 104) is a T-type resistor network (302) 304), the T-type resistor network (302; 304) includes a switchable variable parallel resistor (Rp) and two switchable variable series resistors (Rs). 6. The attenuator (100) of claim 4, wherein the switchable variable series resistor (Rs) comprises one or more switched resistor branches (400, 401, . . . , 40n) and Bypass path (40b). 7. The attenuator (100) of claim 5, wherein the switchable variable series resistor (Rs) comprises one or more switched resistor branches (400, 401, . . . , 40n) and Bypass path (40b). 8. The attenuator (100) of claim 6, wherein the bypass path (40b) comprises a switch (Tb), and wherein the lead path comprising a capacitor (Cb) in series with a resistor (Rb) is connected at Between the following two of the switch (Tb): gate; and drain or source. 9. The attenuator (100) of claim 7, wherein the bypass path (40b) comprises a switch (Tb), and wherein the lead path comprising a capacitor (Cb) in series with a resistor (Rb) is connected at Between the following two of the switch (Tb): gate; and drain or source. 10. The attenuator (100) of claim 4, wherein the switchable variable parallel resistor (Rp) comprises one or more switched resistor branches (500) connected in series with a resistor (RPb) , 501, ..., 50m). 11. The attenuator (100) of claim 5, wherein the switchable variable parallel resistor (Rp) comprises one or more switched resistor branches (500) connected in series with a resistor (RPb) , 501, ..., 50m). 12. The attenuator (100) of claim 6, wherein each of the one or more switched resistor branches (400, 401, ..., 40n; 500, 501, ..., 50m) comprising a resistor in series with the switch, and wherein for one or more switches, depending on the size of the one or more switches, a lead path comprising a capacitor in series with the resistor is connected between the following two of the switches : gate; and drain or source. 13. The attenuator (100) of claim 7, wherein each of the one or more switched resistor branches (400, 401, ..., 40n; 500, 501, ..., 50m) comprising a resistor in series with the switch, and wherein for one or more switches, depending on the size of the one or more switches, a lead path comprising a capacitor in series with the resistor is connected between the following two of the switches : gate; and drain or source. 14. The attenuator (100) of claim 8, wherein each of the one or more switched resistor branches (400, 401, ..., 40n; 500, 501, ..., 50m) comprising a resistor in series with the switch, and wherein for one or more switches, depending on the size of the one or more switches, a lead path comprising a capacitor in series with the resistor is connected between the following two of the switches : gate; and drain or source. 15. The attenuator (100) of claim 9, wherein each of the one or more switched resistor branches (400, 401, ..., 40n; 500, 501, ..., 50m) comprising a resistor in series with the switch, and wherein for one or more switches, depending on the size of the one or more switches, a lead path comprising a capacitor in series with the resistor is connected between the following two of the switches : gate; and drain or source. 16. The attenuator (100) of claim 10, wherein each of the one or more switched resistor branches (400, 401, ..., 40n; 500, 501, ..., 50m) comprising a resistor in series with the switch, and wherein for one or more switches, depending on the size of the one or more switches, a lead path comprising a capacitor in series with the resistor is connected between the following two of the switches : gate; and drain or source. 17. The attenuator (100) of claim 11, wherein each of the one or more switched resistor branches (400, 401, ..., 40n; 500, 501, ..., 50m) comprising a resistor in series with the switch, and wherein for one or more switches, depending on the size of the one or more switches, a lead path comprising a capacitor in series with the resistor is connected between the following two of the switches : gate; and drain or source. 18. The attenuator (100) of any of claims 1-2, wherein each of the pair of compensation paths (106; 108) comprises one or more switched capacitor branches, and each switch The type capacitor branch includes a capacitor (Cnc) connected in series with a resistor (Rnc). 19. The attenuator (100) of claim 18, wherein each of the switched capacitor branches further comprises a switch connected in series with the capacitor (Cnc) and the resistor (Rnc). 20. The attenuator (100) of claim 2, wherein the first and second pairs of inductors are mutually coupled inductors. 21. An electronic device (1100) comprising the attenuator (100) of any of claims 1-20. 22. The electronic device (1100) of claim 21, wherein the electronic device (1100) is a transceiver. 23. The electronic device (1100) of claim 21, wherein the electronic device (1100) is a radio base station.

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