CN106972916A - One kind is without synchronised clock demblee form serial communication sampling location system of selection - Google Patents
One kind is without synchronised clock demblee form serial communication sampling location system of selection Download PDFInfo
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- CN106972916A CN106972916A CN201710176185.5A CN201710176185A CN106972916A CN 106972916 A CN106972916 A CN 106972916A CN 201710176185 A CN201710176185 A CN 201710176185A CN 106972916 A CN106972916 A CN 106972916A
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- Prior art keywords
- clock
- synchronizing information
- data
- selection
- serial communication
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- 238000005070 sampling Methods 0.000 title claims abstract description 37
- 238000004891 communication Methods 0.000 title claims abstract description 36
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 24
- 238000001514 detection method Methods 0.000 claims abstract description 17
- 239000000872 buffer Substances 0.000 claims abstract description 14
- 230000003111 delayed effect Effects 0.000 claims 1
- 230000005540 biological transmission Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000011084 recovery Methods 0.000 description 3
- 229910002056 binary alloy Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000010187 selection method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
It is a kind of that without synchronised clock demblee form serial communication sampling location system of selection, serial communication data frame has fixed synchronizing information, including：Produce that 4 tunnels are identical with data baud rate using phaselocked loop, phase differs 90 degree of local sampling clock；Serial data stream is sampled using 4 produced local sampling clocks, and sampled result is sent into 4 fifo buffers；When the data in fifo buffer are more than 8, start to read the data in fifo buffer, and the data of reading are sent into synchronizing information detector；When synchronizing information detector at least 3 roads export detection pulse simultaneously, into next step, otherwise continue to detect；When synchronizing information detector has 3 roads while when exporting detection pulse, the clock of intermediate phase is selected as optimum sampling position clock, when synchronizing information detector has 4 roads while when exporting detection pulse, selection 180 degree phase clock is used as optimum sampling position clock.Demblee form, the reliability of multinode Random Communication, flexibility is greatly improved in the present invention.
Description
Technical field
The present invention relates to a kind of communication mode.More particularly to one kind is without synchronised clock demblee form serial communication sampling location
System of selection.
Background technology
In the application of many industry spots, in order to lift the reliability of interconnection and reduce the cost of interconnection, in communication band
Width is required in the case of not being very high, is often interconnected by the way of serial communication.Serial communication interconnection can with it is synchronous when
Clock, can also be without synchronised clock.The traffic rate of serial communication with synchronised clock is high, but as shown in Figure 1, it is necessary to transmit
Synchronised clock is transmitted while data, this is very inconvenient in many instances, data interconnection topology is more multiple especially in system
In the case of miscellaneous.Demblee form serial communication without synchronised clock communication efficiency in high-speed is high, but data recovery difficulty is big,
The big main cause of difficulty is the bad determination of sampling point position of data recovery, as shown in Figure 2.
The content of the invention
The technical problems to be solved by the invention are to provide one kind can be serial without synchronised clock with the solution of less cost
The data recovery problem of communication, and it is convenient realize without synchronised clock demblee form serial communication sampling location system of selection.
The technical solution adopted in the present invention is：One kind is without synchronised clock demblee form serial communication sampling location selecting party
Method, serial communication data frame has fixed synchronizing information, comprises the following steps：
1) produce that 4 tunnels are identical with data baud rate using phaselocked loop, phase differs 90 degree of local sampling clock；
2) serial data stream is sampled using 4 produced local sampling clocks, and sampled result is sent into 4
In fifo buffer；
3) when the data in fifo buffer are more than 8, start to read the data in fifo buffer, and will read
Data feeding synchronizing information detector；
4) when synchronizing information detector at least 3 roads export detection pulse simultaneously, into next step, otherwise continue to examine
Survey；
5) when synchronizing information detector has 3 roads while when exporting detection pulse, selecting the clock of intermediate phase as optimal
Sampling location clock, when synchronizing information detector has 4 roads while when exporting detection pulse, selection 180 degree phase clock is as most
Good sampling location clock；
6) terminate.
Step 2) described in fifo buffer be a kind of depth be more than 16 standard advanced first go out memory.
Step 3) described in synchronizing information detector be a kind of device detected to fixed serial sequence, detection data
Fixation synchronizing information in frame, a pulse can be exported when synchronizing information detector is detected after fixed synchronizing information.
Step 5) described in intermediate phase clock be refer to 3 tunnels output detection pulse distinguish corresponding three phases when
Zhong Zhong, that centrally located phase clock.
One kind of the present invention can solve multiple nodes without synchronised clock demblee form serial communication sampling location system of selection
The key issue of the serial communication network burst communication of composition, due to that need not transmit synchronised clock, is simplifying communication link
Meanwhile, by selecting optimal data sampling position, demblee form, the reliability of multinode Random Communication, spirit is greatly improved
Activity.
Brief description of the drawings
Fig. 1 is the communication scheme with synchronised clock serial communication；
Fig. 2 is the communication scheme of no synchronised clock serial communication；
Fig. 3 is the requirement schematic diagram of no synchronised clock serial communication data frame；
Fig. 4 is the local sampling clock schematic diagram of 90 ° of 4 road phase difference；
Fig. 5 is that 4 road clock sampling data enter FIFO schematic diagrames.
Embodiment
The a kind of of the present invention is selected without synchronised clock demblee form serial communication sampling location with reference to embodiment and accompanying drawing
Selection method is described in detail.
Data occur and without the transmission of synchronised clock information at random in unclocked demblee form serial communication frame, therefore
The difficult point of reception is the sampling location for determining local sampling clock, and receiving-transmitting sides transmission only has data, therefore this is adopted
Sample position can only determine that is accomplished by before sampling location is determined can not having real effective data transmission from data.
Need one specific character string of transmission to do determination sampling point position before sampled point is determined to use.
This specific character string is used for convenience, using binary system " 10101010 " totally 8 bit.
The requirement that frame structure can to sum up be determined is：Start as the burst of data of " 10101010 ", beginning
" 10101010 " are used for determining the sampling location that local data recovers as synchronizing information, and follow-up data are really to need to receive
Effective information, as shown in Figure 3.
The present invention's is a kind of without synchronised clock demblee form serial communication sampling location system of selection, serial communication data frame tool
There is fixed synchronizing information, comprise the following steps：
1) produce that 4 tunnels as shown in Figure 4 are identical with data baud rate, 90 degree of phase difference local sampling using phaselocked loop
Clock；
2) serial data stream is sampled using 4 produced local sampling clocks, and sampled result is sent into 4
In fifo buffer, as shown in Figure 5；Described fifo buffer is that a kind of standard advanced of depth more than 16 first goes out memory,
Such as realized by FPGA programming devices.
3) when the data in fifo buffer are more than 8, start to read the data in fifo buffer, and will read
Data feeding synchronizing information detector；Described synchronizing information detector is a kind of dress detected to fixed serial sequence
Put, can detect the fixation synchronizing information in data frame, one can be exported after fixed synchronizing information when synchronizing information detector is detected
Individual pulse.
4) when the output detection pulse of synchronizing information detector at least 3 tunnels, into next step, otherwise continue to detect；
5) when synchronizing information detector has the output detection pulse of 3 tunnels, the clock of selection intermediate phase is used as optimum sampling
Position clock, as shown in figure 5, the clock of described intermediate phase refers to distinguish corresponding three phases in the output detection pulse of 3 tunnels
In bit clock, that centrally located phase clock；When synchronizing information detector has the output detection pulse of 4 tunnels, selection
180 degree phase clock is used as optimum sampling position clock；
6) terminate.
Claims (4)
1. one kind is without synchronised clock demblee form serial communication sampling location system of selection, it is characterised in that serial communication data frame
With fixed synchronizing information, comprise the following steps：
1) produce that 4 tunnels are identical with data baud rate using phaselocked loop, phase differs 90 degree of local sampling clock；
2) serial data stream is sampled using 4 produced local sampling clocks, and 4 FIFO of sampled result feeding is delayed
Rush in area；
3) when the data in fifo buffer are more than 8, start to read the data in fifo buffer, and by the number of reading
According to feeding synchronizing information detector；
4) when synchronizing information detector at least 3 roads export detection pulse simultaneously, into next step, otherwise continue to detect；
5) when synchronizing information detector has 3 roads while when exporting detection pulse, the clock of selection intermediate phase is used as optimum sampling
Position clock, when synchronizing information detector has 4 roads while when exporting detection pulse, selection 180 degree phase clock is as most preferably adopting
Sample position clock；
6) terminate.
2. one kind according to claim 1 is without synchronised clock demblee form serial communication sampling location system of selection, its feature
Be, step 2) described in fifo buffer be a kind of depth be more than 16 standard advanced first go out memory.
3. one kind according to claim 1 is without synchronised clock demblee form serial communication sampling location system of selection, its feature
Be, step 3) described in synchronizing information detector be a kind of device detected to fixed serial sequence, detection data frame
In fixation synchronizing information, a pulse can be exported after fixed synchronizing information when synchronizing information detector is detected.
4. one kind according to claim 1 is without synchronised clock demblee form serial communication sampling location system of selection, its feature
Be, step 5) described in the clock of intermediate phase be to refer to distinguish corresponding three phase clocks in the output detection pulse of 3 tunnels
In, that centrally located phase clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710176185.5A CN106972916A (en) | 2017-03-22 | 2017-03-22 | One kind is without synchronised clock demblee form serial communication sampling location system of selection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710176185.5A CN106972916A (en) | 2017-03-22 | 2017-03-22 | One kind is without synchronised clock demblee form serial communication sampling location system of selection |
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| Publication Number | Publication Date |
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| CN106972916A true CN106972916A (en) | 2017-07-21 |
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| CN201710176185.5A Pending CN106972916A (en) | 2017-03-22 | 2017-03-22 | One kind is without synchronised clock demblee form serial communication sampling location system of selection |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112671527A (en) * | 2021-01-13 | 2021-04-16 | 北京方天长久科技股份有限公司 | Method and system for sampling serial communication data without synchronous clock |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6266799B1 (en) * | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
| CN103036667A (en) * | 2012-11-30 | 2013-04-10 | 北京控制工程研究所 | Self-adaption timing sequence calibrating method of high-speed serial communication interface |
| CN104579566A (en) * | 2014-12-31 | 2015-04-29 | 中国电子科技集团公司第七研究所 | Synchronous information detection method, system and general correlator |
| CN105468561A (en) * | 2014-08-14 | 2016-04-06 | 山东维航电子科技有限公司 | High-speed asynchronous serial communication method |
-
2017
- 2017-03-22 CN CN201710176185.5A patent/CN106972916A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6266799B1 (en) * | 1997-10-02 | 2001-07-24 | Xaqti, Corporation | Multi-phase data/clock recovery circuitry and methods for implementing same |
| CN103036667A (en) * | 2012-11-30 | 2013-04-10 | 北京控制工程研究所 | Self-adaption timing sequence calibrating method of high-speed serial communication interface |
| CN105468561A (en) * | 2014-08-14 | 2016-04-06 | 山东维航电子科技有限公司 | High-speed asynchronous serial communication method |
| CN104579566A (en) * | 2014-12-31 | 2015-04-29 | 中国电子科技集团公司第七研究所 | Synchronous information detection method, system and general correlator |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112671527A (en) * | 2021-01-13 | 2021-04-16 | 北京方天长久科技股份有限公司 | Method and system for sampling serial communication data without synchronous clock |
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