CN106951229A - A kind of method stressed compatible a variety of NAND FLASH of BOOT ROM - Google Patents
A kind of method stressed compatible a variety of NAND FLASH of BOOT ROM Download PDFInfo
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- CN106951229A CN106951229A CN201710094000.6A CN201710094000A CN106951229A CN 106951229 A CN106951229 A CN 106951229A CN 201710094000 A CN201710094000 A CN 201710094000A CN 106951229 A CN106951229 A CN 106951229A
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- child
- data
- nand
- flash
- stressed
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/142—Reconfiguring to eliminate the error
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Quality & Reliability (AREA)
- Read Only Memory (AREA)
Abstract
Technical scheme includes a kind of stressed methods of the compatible a variety of NAND FLASH of BOOT ROM, it is characterised in that this method includes:Command character, order, multiple addresses and multiple data of writing are set to a child-operation, wherein, one sub- operation set of multiple child-operation correspondences, a kind of NAND FLASH stressed operation of each child-operation collection correspondence;During programming firmware, according to NAND FLASH child-operation collection information, corresponding child-operation tables of data is generated, and child-operation tables of data is write into NAND FLASH correspondence positions;When BOOT ROM start, NAND FLASH child-operation tables of data is scanned for using resolver, if finding corresponding child-operation tables of data, performs and reads operation again, if not finding corresponding child-operation tables of data, stressed function is not provided.Beneficial effects of the present invention are:Do not increase hardware cost;On the basis of multiple backups, further increase the reliability of BOOT ROM datas.
Description
Technical field
The present invention relates to the method that a kind of compatible a variety of NAND-FLASH of BOOT-ROM are stressed, belong to Computer Storage neck
Domain.
Background technology
For the NAND-FLASH of current main flow, genuine is required to driving and visited using the method for reading (read retry) again
Ask, read the configuration that the special command for referring to, when the data read are wrong, can be specified by genuine changes NAND-FLASH again,
Re-read trial and obtain correct data, so as to strengthen data holding ability.
In practical application, current software-driven supports that this is operated, and is not supported in BOOT-ROM.First, due to
Different manufacturers, different processing procedure stressed method divergence it is very big, and the NAND-FLASH operation codes in BOOT-ROM have volume limit
System, it is impossible to which every kind of stressed method compatibility is entered;Second, BOOT-ROM are fixed after the completion of IC flows, it is impossible to changed, for
The new stressed parameter that later stage occurs, BOOT-ROM can not update.
NAND-FLASH is a kind of mass-memory unit being widely used, big with capacity, the low spy of unit price
Point, but due to Market competition, its processing procedure is reducing to reduce cost, reduced along with processing procedure always, NAND-FLASH's
Worse and worse, in order to ensure data reliability, stressed read method is also correspondingly occurred in that stability.Data are with electric charge
Form is stored in inside NAND-FLASH, with resting period, the growth of erasing times, and electric charge can be leaked at random, cause the position
It is inconsistent when the information of voltage put is with just write-in, if still with original voltage threshold being judged, it can cause to read information mistake
By mistake, the effect of " stressed " is that adjustment voltage judgment threshold, so that the data changed are correctly read.Therefore, for
In any case to NAND-FLASH access, it should all support to read operation again.
But in fact, as described above, due to code cubage limitation, limitation is updated, current BOOT-ROM designs are nothings
Method is supported to read again.The risk supported is not read again in order to tackle, and is all to use many numbers mostly in the case where not increasing cost
, can be using two grades of methods guided, i.e., using sufficiently stable reliable storage medium if allowing to increase cost according to the mode of backup
Equipment is guided as one-level.
The content of the invention
In view of the shortcomings of the prior art, technical scheme provides a kind of compatible a variety of NAND- of BOOT-ROM
Method stressed FLASH, this method different stressed methods it is abstract be some child-operations with general character, and in BOOT-ROM
In realize a resolver, for handling this kind of child-operation.A kind of stressed method actually sub- operation set, during programming firmware
Bundle operation set information is written to inside NAND-FLASH, therefore, as long as reading the operation set information during BOOT-ROM startups,
The stressed method for this NAND-FLASH can be got, so as to realize stressed operating function.
Technical scheme includes a kind of stressed methods of the compatible a variety of NAND-FLASH of BOOT-ROM, and its feature exists
In this method includes:A. command character, order, multiple addresses and multiple data of writing are set to a child-operation, wherein, it is multiple
Child-operation one sub- operation set of correspondence, a kind of NAND-FLASH stressed operation of each child-operation collection correspondence;B. during programming firmware,
According to NAND-FLASH child-operation collection information, corresponding child-operation tables of data is generated, and child-operation tables of data is write into NAND-
FLASH correspondence positions;When C.BOOT-ROM starts, NAND-FLASH child-operation tables of data is scanned for using resolver,
If finding corresponding child-operation tables of data, perform and read operation again, if not finding corresponding child-operation tables of data, no
There is provided and read function again.
According to the method that the compatible a variety of NAND-FLASH of described BOOT-ROM are stressed, described command character includes:For
The transmission order number of corresponding child-operation is specified, address number is sent and sends data amount check.
According to the method that the compatible a variety of NAND-FLASH of described BOOT-ROM are stressed, described child-operation collection includes:Weight
Initialization child-operation collection during reading, circulation child-operation collection and exit child-operation collection.
According to the method that the compatible a variety of NAND-FLASH of described BOOT-ROM are stressed, the child-operation tables of data includes:
Index information, for during operation is read again, index information to position the position of required child-operation, storing initialization action, circulation
Configuration parameter acts and exited action message, wherein the different child-operation data content of different action correspondences;Suboperand evidence, is used
Operating procedure and storage associative operation number are read again in instruction.
Beneficial effects of the present invention are:Do not increase hardware cost;On the basis of multiple backups, further increase BOOT-ROM
The reliability of data.
Brief description of the drawings
Fig. 1 show the overview flow chart according to embodiment of the present invention;
Fig. 2 show the stressed flow chart according to embodiment of the present invention;
Fig. 3 show the child-operation tables of data programming flow chart according to embodiment of the present invention;
Fig. 4 show the BOOT-ROM flow charts according to embodiment of the present invention.
Embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, below in conjunction with the accompanying drawings with specific embodiment pair
The present invention is described in detail.The method stressed compatible a variety of NAND-FLASH of the BOOT-ROM of the present invention is applied to BOOT-ROM
The processing of internal storage data.
Fig. 1 show the overview flow chart according to embodiment of the present invention.A. by command character, order, multiple addresses and many
Individual data of writing are set to a child-operation, wherein, one sub- operation set of multiple child-operation correspondences, each child-operation collection correspondence is a kind of
NAND-FLASH stressed operation;B. during programming firmware, according to NAND-FLASH child-operation collection information, corresponding sub- behaviour is generated
Make tables of data, and child-operation tables of data is write into NAND-FLASH correspondence positions;When C.BOOT-ROM starts, resolver pair is used
NAND-FLASH child-operation tables of data is scanned for, if finding corresponding child-operation tables of data, is performed and is read operation again, if
Corresponding child-operation tables of data is not found, then stressed function is not provided.
Fig. 2 show the stressed flow chart according to embodiment of the present invention.Any one read again operation can be seen as with
Lower three parts composition:Read initialization child-operation collection, circulation child-operation collection again, read again and exit child-operation collection, complete to read again according to Fig. 2
Operation.
Fig. 3 show the child-operation tables of data programming flow chart according to embodiment of the present invention;
Fig. 4 show the BOOT-ROM flow charts according to embodiment of the present invention.BOOT-ROM contains processing
In the resolver of Data Data, start-up course, subdata tables of data can be searched for first, if can find, then it represents that support to read behaviour again
Make, and when needing to read again, operation is read in triggering again, if can not find, stressed function is not provided.
Technical scheme further discloses composition schematic diagram and the composition signal of subdata tables of data of subdata
Figure, respectively shown in following Tables 1 and 2.
Table 1
Table 2
The above, simply presently preferred embodiments of the present invention, the invention is not limited in above-mentioned embodiment, as long as
It reaches the technique effect of the present invention with identical means, should all belong to protection scope of the present invention.In the protection model of the present invention
Its technical scheme and/or embodiment can have a variety of modifications and variations in enclosing.
Claims (4)
1. the method stressed a kind of compatible a variety of NAND-FLASH of BOOT-ROM, it is characterised in that this method includes:
A. command character, order, multiple addresses and multiple data of writing are set to a child-operation, wherein, multiple child-operation correspondences
One sub- operation set, a kind of NAND-FLASH stressed operation of each child-operation collection correspondence;
B. during programming firmware, according to NAND-FLASH child-operation collection information, corresponding child-operation tables of data is generated, and by sub- behaviour
Make tables of data write-in NAND-FLASH correspondence positions;
When C.BOOT-ROM starts, NAND-FLASH child-operation tables of data is scanned for using resolver, if finding pair
The child-operation tables of data answered, then perform and read operation again, if not finding corresponding child-operation tables of data, stressed work(is not provided
Energy.
2. the method stressed compatible a variety of NAND-FLASH of BOOT-ROM according to claim 1, it is characterised in that described
Command character include:
For specifying the transmission order number of corresponding child-operation, sending address number and sending data amount check.
3. the method stressed compatible a variety of NAND-FLASH of BOOT-ROM according to claim 1, it is characterised in that described
Child-operation collection include:
Initialization child-operation collection, circulation child-operation collection when reading again and exit child-operation collection.
4. the method stressed compatible a variety of NAND-FLASH of BOOT-ROM according to claim 1, it is characterised in that described
Child-operation tables of data includes:
Index information, for read again operation during, index information positioning needed for child-operation position, storing initialization action,
Loop configuration parameter acts and exited action message, wherein the different child-operation data content of different action correspondences;
Suboperand evidence, for indicating to read operating procedure again and depositing associative operation number.
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CN201710094000.6A CN106951229A (en) | 2017-02-21 | 2017-02-21 | A kind of method stressed compatible a variety of NAND FLASH of BOOT ROM |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107423160A (en) * | 2017-07-24 | 2017-12-01 | 山东华芯半导体有限公司 | A kind of method and device of raising NAND flash reading rates |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100322007A1 (en) * | 2009-06-19 | 2010-12-23 | Samsung Electronics Co., Ltd. | Flash memory device and method of reading data |
CN103914358A (en) * | 2014-04-03 | 2014-07-09 | 深圳市硅格半导体有限公司 | Flash memory rereading method and device |
CN106158038A (en) * | 2015-04-14 | 2016-11-23 | 飞思卡尔半导体公司 | The method reading data from nonvolatile memory |
-
2017
- 2017-02-21 CN CN201710094000.6A patent/CN106951229A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100322007A1 (en) * | 2009-06-19 | 2010-12-23 | Samsung Electronics Co., Ltd. | Flash memory device and method of reading data |
CN103914358A (en) * | 2014-04-03 | 2014-07-09 | 深圳市硅格半导体有限公司 | Flash memory rereading method and device |
CN106158038A (en) * | 2015-04-14 | 2016-11-23 | 飞思卡尔半导体公司 | The method reading data from nonvolatile memory |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107423160A (en) * | 2017-07-24 | 2017-12-01 | 山东华芯半导体有限公司 | A kind of method and device of raising NAND flash reading rates |
CN107423160B (en) * | 2017-07-24 | 2020-04-17 | 山东华芯半导体有限公司 | Method and device for improving NAND flash reading speed |
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