CN106959818B

CN106959818B - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN106959818B
Application number: CN201610015194.1A
Authority: CN
Inventors: 柯伯政
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2016-01-11
Filing date: 2016-01-11
Publication date: 2020-03-31
Anticipated expiration: 2036-01-11
Also published as: CN106959818A

Abstract

The present invention provides a data writing method, a memory control circuit unit and a memory storage device. The method includes recording a clearing instruction count and updating the clearing instruction count each time a clearing instruction is received from a host system. The method also includes extracting a first physical erase unit as an actuating physical unit and determining whether the clearing instruction count is greater than a clearing instruction count threshold value. The method also includes setting the writing mode of the actuating physical unit to a first writing mode if the clearing instruction count threshold value is greater than the clearing instruction count threshold value. The method also includes setting the writing mode of the actuating physical unit to a second writing mode if the clearing instruction count threshold value is not greater than the clearing instruction count threshold value.

Description

Data writing method, memory control circuit unit and memory storage device

Technical Field

The present invention relates to a data writing method, and more particularly, to a data writing method for a rewritable nonvolatile memory module, a memory control circuit unit and a memory storage device.

Background

Digital cameras, cell phones and MP3 have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high read-write speed and the like, the rewritable non-volatile memory is most suitable for portable electronic products such as notebook computers. A solid state disk is a memory storage device using a flash memory as a storage medium. Therefore, the flash memory industry has become a relatively popular segment of the electronics industry in recent years.

The NAND-type flash memory is classified into a Single Level Cell (SLC) NAND-type flash memory, a Multi-Level Cell (MLC) NAND-type flash memory, and a Triple Level Cell (TLC) NAND-type flash memory according to the number of bits that can be stored in each memory Cell, wherein the SLC NAND-type flash memory can store 1 bit of data (i.e., "1" and "0"), the MLC NAND-type flash memory can store 2 bits of data, and the TLC NAND-type flash memory can store 3 bits of data.

In the NAND type flash memory, a physical program unit is composed of a plurality of memory cells arranged on a same word line. Since each cell of the SLC NAND flash can store 1 bit of data, several cells arranged on the same word line correspond to one physical program unit in the SLC NAND flash.

In contrast to SLC NAND flash, the floating gate storage layer of each cell of MLC NAND flash can store 2 bits of data, where each storage state (i.e., "11", "10", "01", and "00") includes the Least Significant Bit (LSB) and the Most Significant Bit (MSB). For example, the value of the 1 st bit from the left side in the storage state is LSB, and the value of the 2 nd bit from the left side is MSB. Therefore, the memory cells arranged on the same word line can be configured into 2 physical programming units, wherein the physical programming unit composed of the LSB of the memory cells is referred to as a lower physical programming unit (low physical programming unit), and the physical programming unit composed of the MSB of the memory cells is referred to as an upper physical programming unit (upper physical programming unit). In particular, the writing speed of the lower physical programming unit is faster than that of the upper physical programming unit, and when an error occurs in the upper physical programming unit, the data stored in the lower physical programming unit may be lost.

Similarly, in the TLC NAND type flash memory, each memory cell can store 3 bits of data, wherein each storage state (i.e., "111", "110", "101", "100", "011", "010", "001", and "000") includes the LSB of the 1 st Bit from the left side, the middle Significant Bit (CSB) of the 2 nd Bit from the left side, and the MSB of the 3 rd Bit from the left side. Therefore, the memory cells arranged on the same word line can constitute 3 physical program units, wherein the physical program unit constituted by the LSBs of the memory cells is called a lower physical program unit, the physical program unit constituted by the CSBs of the memory cells is called a middle physical program unit, and the physical program unit constituted by the MSBs of the memory cells is called an upper physical program unit. In particular, in TLC NAND type flash memory, to ensure that data of one word line can be stably stored, three times of programming must be performed on the word line. For example, after the first programming is performed on the memory cells of the first word line, the memory cells of the first word line are in the first state (first state). While the memory cells of the second word line are programmed again. At this time, the memory cell of the first word line is in a foggy state. Then, the memory cells of the first word line and the second word line are programmed again while the memory cells of the third word line are being programmed, and the memory cells of the first word line are in good state (fine state). Furthermore, the memory cells of the second word line and the third word line are programmed again while the memory cells of the fourth word line are being programmed, and at this time, the memory cells of the second word line are in a good state, so that the data in the memory cells of the first word line can be stably stored. Based on the above principle, when the host system issues a flush command, the memory controller also needs to program the other three consecutive word lines in order to ensure that data is stably stored in the TLC NAND type flash memory. Each word line includes three physical programming units, so that the memory control circuit needs to write dummy data into 9 physical programming units, which results in excessive redundant writing, reduces the storage efficiency of the memory storage device, and shortens the life of the memory storage device.

Disclosure of Invention

The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can adjust the writing mode of a physical erasing unit according to the frequency of executing a bin clearing instruction, thereby reducing the writing of virtual data.

An exemplary embodiment of the present invention provides a data writing method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erase units, and each physical erase unit has a plurality of lower physical programming units and a plurality of upper physical programming units. The data writing method includes recording the bin-clearing instruction count. The data writing method also comprises the steps of extracting the first entity erasing unit from the entity erasing units to be used as an actuating entity unit, and judging whether the bin clearing instruction count is larger than the bin clearing instruction count threshold value or not. The data writing method also includes setting a writing mode of the physical actuation unit to a first writing mode if the bin clearing instruction count threshold is greater than the bin clearing instruction count threshold, wherein in the first writing mode, each memory cell constituting the physical actuation unit stores a first number of bits of data. The data writing method further includes setting the writing mode of the actuation entity unit to a second writing mode if the bin clearing instruction count threshold is not greater than the bin clearing instruction count threshold, wherein in the second writing mode, each memory cell constituting the actuation entity unit stores a second number of bits of data, wherein the first number is smaller than the second number.

In an exemplary embodiment of the invention, the step of recording the bin-clearing instruction count includes: the flush command count is updated each time a flush command is received from the host system.

In an exemplary embodiment of the invention, the step of recording the bin-clearing instruction count further includes: after the write mode setting of the active physical unit is set, the bin clearing instruction count is reset.

In an exemplary embodiment of the invention, the step of updating the flush instruction count includes incrementing the flush instruction count by 1, and the step of resetting the flush instruction count includes setting the flush instruction count to 0.

In an exemplary embodiment of the invention, the step of extracting the first physically erased cell from the physically erased cells as the active physically erased cell includes: extracting a super-physical unit composed of a first physical erasing unit and at least one other physical erasing unit from the physical erasing units as an active physical unit. In addition, the step of recording the bin-clearing instruction count further comprises: after the super entity unit is full, the flush instruction count is reset.

In an exemplary embodiment of the invention, the data writing method further includes receiving a write command and write data corresponding to the write command from the host system; and programming the write data to the action entity unit according to the write mode of the action entity unit.

In an exemplary embodiment of the invention, the data writing method further includes grouping the physical erase units into at least a data area and an idle area, wherein the step of extracting the first physical erase unit from the physical erase units as an active physical unit includes: the first physical erasing unit is extracted from the idle area to be used as an active physical unit.

In an exemplary embodiment of the present invention, each of the plurality of erase units further has a plurality of middle program units.

In an exemplary embodiment of the invention, the data writing method further includes: and dynamically adjusting the bin-clearing instruction counting threshold value according to the host write data volume and the actual programmed data volume.

In an exemplary embodiment of the invention, the step of dynamically adjusting the bin-clearing command count threshold according to the host write data amount and the actual programmed data amount comprises: the bin-clearing command count threshold is decreased as the value obtained by dividing the actual programmed data amount by the host write data amount increases.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module, which includes a host interface, a memory interface and a memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit is provided with a plurality of lower entity programming units and a plurality of upper entity programming units. The memory management circuit is electrically connected to the host interface and the memory interface and is used for recording the bin-clearing instruction count. In addition, the memory management circuit is further configured to extract the first physical erase unit from the physical erase units as an active physical unit, and determine whether the bin clearing instruction count is greater than the bin clearing instruction count threshold value. If the bin-clearing instruction count threshold value is greater than the bin-clearing instruction count threshold value, the memory management circuit sets the write mode of the actuation entity unit to a first write mode, wherein in the first write mode, each memory cell constituting the actuation entity unit stores a first number of bits of data. If the bin-clearing instruction count threshold is not greater than the bin-clearing instruction count threshold, the memory management circuit sets the write mode of the physical actuation unit to a second write mode, wherein in the second write mode, each memory cell constituting the physical actuation unit stores a second number of bits of data, wherein the first number is less than the second number.

In an exemplary embodiment of the invention, in the operation of recording the count of the flush command, the memory management circuit updates the count of the flush command each time the flush command is received from the host system.

In an exemplary embodiment of the invention, in the operation of recording the count of the flush instruction, the memory management circuit is further configured to reset the count of the flush instruction after setting the write mode setting of the active physical unit.

In an exemplary embodiment of the invention, the memory management circuit increments the flush instruction count by 1 in the operation of updating the flush instruction count, and sets the flush instruction count to 0 in the operation of resetting the flush instruction count.

In an exemplary embodiment of the invention, in the operation of extracting the first physical erase unit from the physical erase units as the active physical unit, the memory management circuit extracts the super physical unit composed of the first physical erase unit and at least one other physical erase unit from the physical erase units as the active physical unit. In addition, in the operation of recording the bin count, the memory management circuit resets the bin count after the super entity unit is full.

In an exemplary embodiment of the invention, the memory management circuit is further configured to receive a write command and write data corresponding to the write command from the host system, and issue a sequence of commands to program the write data to the active physical unit according to a write mode of the active physical unit.

In an exemplary embodiment of the invention, the memory management circuit is further configured to logically group the physically erased cells into at least a data area and an idle area. Wherein in the operation of extracting the first physical erasing unit from the physical erasing units as the active physical unit, the memory management circuit extracts the first physical erasing unit from the idle area as the active physical unit.

In an exemplary embodiment of the invention, the memory management circuit is further configured to dynamically adjust the bin count threshold according to the amount of host write data and the amount of actual programmed data.

In an exemplary embodiment of the invention, the memory management circuit decreases the flush command count threshold when a value obtained by dividing the amount of actual programmed data by the amount of host write data increases.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module, and a memory control circuit unit. The connection interface unit is used for electrically connecting to a host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit is provided with a plurality of lower entity programming units and a plurality of upper entity programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module and is used for recording the bin-cleaning instruction count. In addition, the memory control circuit unit is further used for extracting the first entity erasing unit from the entity erasing units as an action entity unit and judging whether the bin clearing instruction count is larger than the bin clearing instruction count threshold value or not. If the bin-clearing instruction count threshold value is greater than the bin-clearing instruction count threshold value, the memory control circuit unit sets the write mode of the actuation entity unit to a first write mode, wherein in the first write mode, each memory cell constituting the actuation entity unit stores a first number of bits of data. If the bin-clearing instruction count threshold value is not greater than the bin-clearing instruction count threshold value, the memory control circuit unit sets the write mode of the actuation entity unit to a second write mode, wherein in the second write mode, each memory cell constituting the actuation entity unit stores a second number of bits of data, wherein the first number is less than the second number.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to receive a write command and write data corresponding to the write command from the host system, and issue a sequence of commands to program the write data to the active physical unit according to a write mode of the active physical unit.

In an exemplary embodiment of the invention, in the operation of recording the count of the flush command, the memory control circuit unit updates the count of the flush command each time the flush command is received from the host system.

In an exemplary embodiment of the invention, in the operation of recording the count of the flush instruction, the memory control circuit unit is further configured to reset the count of the flush instruction after setting the write mode setting of the active physical unit.

In an exemplary embodiment of the present invention, the memory control circuit unit increments the flush instruction count by 1 in the operation of updating the flush instruction count, and sets the flush instruction count to 0 in the operation of resetting the flush instruction count.

In an exemplary embodiment of the present invention, in the operation of extracting the first physical erase unit from the physical erase units as the active physical units, the memory control circuit unit extracts the super physical unit composed of the first physical erase unit and at least one other physical erase unit from the physical erase units as the active physical units. In addition, in the operation of recording the bin-clearing instruction count, the memory control circuit unit resets the bin-clearing instruction count after the super-entity unit is full.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to logically group the physically erased cells into at least a data area and an idle area. Wherein in the operation of extracting the first physical erase unit from the physical erase units as the active physical unit, the memory control circuit unit extracts the first physical erase unit from the idle area as the active physical unit.

In an exemplary embodiment of the invention, the memory control circuit unit is further configured to dynamically adjust the bin count threshold according to the host write data amount and the actual programmed data amount.

In an exemplary embodiment of the present invention, the memory control circuit unit decreases the flush command count threshold when a value obtained by dividing the amount of actually programmed data by the amount of host write data increases.

Based on the above, the data writing method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention can effectively reduce the data amount of the dummy data written by executing the flush instruction, thereby prolonging the life of the rewritable nonvolatile memory.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment;

FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment;

FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment;

FIGS. 5A and 5B are schematic diagrams of a memory cell storage architecture and physically erased cells according to an example embodiment;

FIG. 6 is a schematic block diagram of memory control circuitry shown in accordance with an example embodiment;

FIGS. 7 and 8 illustrate exemplary managing physical erase units according to one exemplary embodiment;

FIGS. 9A and 9B are flowcharts illustrating a data writing method according to an example embodiment.

Reference numerals:

10: memory storage device

11: host system

12: input/output (I/O) device

110: system bus

111: processor with a memory having a plurality of memory cells

112: random Access Memory (RAM)

113: read-only memory (ROM)

114: data transmission interface

20: main board

201: portable disc

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network adapter

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

30: memory storage device

31: host system

32: SD card

33: CF card

34: embedded storage device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

410(0) to 410 (N): physical erase unit

502: memory management circuit

504: host interface

506: memory interface

508: buffer memory

510: power management circuit

512: error checking and correcting circuit

602: data area

604: idle zone

606: system area

608: substitution zone

LBA (0) to LBA (h): logical addresses

LZ (0) to LZ (M): logical area

S901: step of establishing bin-clearing instruction count and setting it to 0

S903: updating the bin-clearing instruction count each time a bin-clearing instruction is received from the host system

S905: step of receiving write command and corresponding write data from host system

S907: determining whether there is enough space for writing the write data in the active physical unit

S909: the step of issuing a sequence command to program the write data to the active entity unit and updating the logical address-physical address mapping table according to the write mode of the active entity unit

S911: the step of extracting a physical erase unit (hereinafter referred to as the first physical erase unit) as a new active physical unit

S913: judging whether the bin clearing instruction count is larger than the bin clearing instruction count threshold value

S915: setting the write mode of the first physical erase unit to the second write mode

S917: setting the write mode of the first physical erase unit to the first write mode

S919: resetting the bin clean instruction count to 0

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module and a controller (also referred to as a control circuit unit). Memory storage devices are typically used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment. And FIG. 2 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to another example embodiment.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may write data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the random access memory 112, the read only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transmission interface 114, the main board 20 can be electrically connected to the memory storage device 10 in a wired or wireless manner. The memory storage device 10 can be, for example, a flash Drive 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory Storage device 204 can be, for example, a Near Field Communication (NFC) memory Storage device, a wireless facsimile (WiFi) memory Storage device, a Bluetooth (Bluetooth) memory Storage device, or a low power Bluetooth memory Storage device (e.g., iBeacon) based on various wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34 used therein. The embedded storage device 34 includes various types of embedded Multi-media cards (eMMC) 341 and/or embedded Multi-chip package storage devices (eMCP) 342 to electrically connect the memory module directly to the embedded storage device on the substrate of the host system.

FIG. 4 is a schematic block diagram illustrating a host system and a memory storage device according to an example embodiment.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the exemplary embodiment, connection interface unit 402 is compliant with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also conform to the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the High-Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Ultra High Speed Specification-I (UHS-I) interface standard, the Ultra High Speed Specification-II (UHS-II) interface standard, the Secure Digital (SD) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-P Package) interface standard, the Multi-Media storage Card (Multi-Media, Multimedia storage Card (MMC, Multimedia storage Card (MMC), eMMC) interface standard, Universal Flash Storage (UFS) interface standard, embedded Multi-Chip Package (eMCP) interface standard, Compact Flash (CF) interface standard, Integrated Device Electronics (IDE) standard, or other suitable standard. In the present exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type, and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 410(0) -410 (N). For example, the physical erase units 410(0) -410 (N) may belong to the same memory die (die) or to different memory dies. Each entity erasing unit is respectively provided with a plurality of entity programming units, wherein the entity programming units belonging to the same entity erasing unit can be independently written and simultaneously erased. However, it should be understood that the invention is not limited thereto, and each of the plurality of physically erased cells may be composed of 64 physically programmed cells, 256 physically programmed cells, or any other number of physically programmed cells.

In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. The physical programming unit is a minimum unit for programming. That is, the physical programming unit is the minimum unit for writing data. Each physical programming cell typically includes a data bit region and a redundancy bit region. The data bit region includes a plurality of physical access addresses for storing user data, and the redundant bit region is used for storing system data (e.g., control information and error correction codes). In the exemplary embodiment, each physical program unit includes 8 physical access addresses in the data bit region, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, the data bit region may include a greater or lesser number of physical access addresses, and the size and number of the physical access addresses are not limited in the present invention. For example, in an exemplary embodiment, the physically erased cells are physical blocks, and the physically programmed cells are physical pages or physical sectors, but the invention is not limited thereto.

In the present exemplary embodiment, the rewritable nonvolatile memory module 406 is a multi-level (TLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory Cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may also be a Multi-level cell (MLC) NAND-type flash memory module (i.e., a flash memory module capable of storing 2 data bits in one memory cell) or other memory modules with the same characteristics.

FIGS. 5A and 5B are schematic diagrams illustrating an example memory cell storage architecture and physically erased cells according to an example embodiment.

Referring to fig. 5A, the storage status of each memory cell of the rewritable nonvolatile memory module 406 can be identified as "111", "110", "101", "100", "011", "010", "001", or "000" (as shown in fig. 5A), wherein the 1 st bit from the left side is LSB, the 2 nd bit from the left side is CSB, and the 3 rd bit from the left side is MSB. In addition, the memory cells arranged on the same word line may constitute 3 physical program units, wherein the physical program unit constituted by the LSBs of the memory cells is referred to as a lower physical program unit, the physical program unit constituted by the CSBs of the memory cells is referred to as a middle physical program unit, and the physical program unit constituted by the MSBs of the memory cells is referred to as an upper physical program unit.

Referring to FIG. 5B, a physical erase unit is composed of a plurality of physical program unit groups, wherein each physical program unit group includes a lower physical program unit, a middle physical program unit and an upper physical program unit composed of a plurality of memory cells arranged on the same word line. For example, in the solid erase cell, the 0 th solid program cell belonging to the lower solid program cell, the 1 st solid program cell belonging to the middle solid program cell, and the 2 nd solid program cell belonging to the upper solid program cell are regarded as one solid program cell group. Similarly, the 3 rd, 4 th, and 5 th physical programming cells are considered as a physical programming cell group, and the other physical programming cells are classified into a plurality of physical programming cell groups according to the same manner.

FIG. 6 is a schematic block diagram of a memory control circuit unit shown in accordance with an example embodiment.

Referring to FIG. 6, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, a memory interface 506, a buffer memory 508, a power management circuit 510, and an error checking and correcting circuit 512.

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations when the memory storage device 10 is in operation.

In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are recorded in the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

FIGS. 7 and 8 illustrate exemplary embodiments of managing physically erased cells, according to an exemplary embodiment.

It should be understood that, when describing the operation of the physically erased cells of the rewritable non-volatile memory module 406, it is a logical concept to operate the physically erased cells by the words "extract", "group", "partition", "associate", and the like. That is, the physical locations of the physical erase units of the rewritable nonvolatile memory module are not changed, but the physical erase units of the rewritable nonvolatile memory module are logically operated.

Referring to FIG. 7, the memory control circuit unit 404 (or the memory management circuit 502) logically groups the physical erase units 410(0) -410 (N) into a data area 602, an idle area 604, a system area 606, and a replacement area 608.

The physically erased cells logically belonging to the data area 602 and the idle area 604 are used for storing data from the host system 11. Specifically, the wear-leveling cells in the data area 602 are regarded as the wear-leveling cells storing data, and the wear-leveling cells in the idle area 604 are used to replace the wear-leveling cells in the data area 602. That is, when receiving a write command and data to be written from the host system 11, the memory management circuit 502 writes the data by extracting the physical erase unit from the idle region 604 to replace the physical erase unit in the data region 602.

The physically erased cells logically belonging to the system area 606 are used for recording system data. For example, the system data includes information about the manufacturer and model of the rewritable nonvolatile memory module, the number of physically erased cells of the rewritable nonvolatile memory module, the number of physically programmed cells per physically erased cell, and the like.

The physically erased cells logically belonging to the replacement area 608 are used in the bad-physically-erased-cell replacement procedure to replace the damaged physically erased cells. Specifically, if there are normal physically erased cells in the replacement area 608 and the physically erased cells in the data area 602 are damaged, the memory management circuit 502 extracts the normal physically erased cells from the replacement area 608 to replace the damaged physically erased cells.

In particular, the number of physically erased cells in the data area 602, the idle area 604, the system area 606 and the replacement area 608 may vary according to different memory specifications. Moreover, it should be understood that during operation of the memory storage device 10, the grouping relationship of the physically erased cells associated with the data area 602, the idle area 604, the system area 606 and the replacement area 608 may dynamically change. For example, when the physically erased cells in the idle area 604 are damaged and replaced by the physically erased cells in the replacement area 608, the physically erased cells in the replacement area 608 are associated with the idle area 604.

Referring to fig. 8, the memory control circuit unit 404 (or the memory management circuit 502) configures logical addresses LBA (0) to LBA (h) to map the physical erase units of the data area 602, where each logical address has a plurality of logical units to map the physical programming units of the corresponding physical erase units. Moreover, when the host system 11 is going to write data to the logical address or update the data stored in the logical address, the memory control circuit unit 404 (or the memory management circuit 502) will extract a physical erase unit from the idle area 604 as an active physical unit to write data, so as to replace the physical erase unit of the data area 602. Moreover, when the physical erase unit as the active physical unit is full, the memory controller 404 (or the memory management circuit 502) will extract the empty physical erase unit from the idle area 504 as the active physical unit to continue writing the update data corresponding to the write command from the host system 11. In addition, when the number of available physical erase units in the idle area 604 is smaller than a predetermined value, the memory controller 404 (or the memory management circuit 502) performs a valid data merging procedure (also called a garbage collection procedure) to collate the valid data in the data area 602 so as to re-associate the physical erase units in the data area 602 that do not store valid data with the idle area 604.

In order to identify the physical erase unit in which the data of each logical address is stored, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) records the mapping between the logical address and the physical erase unit. For example, in the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) stores a mapping table of logical addresses and physical addresses in the rewritable nonvolatile memory module 406 to record the physical erase unit mapped by each logical address. When data is to be accessed, the memory control circuit unit 404 (or the memory management circuit 502) loads the logical address-physical address mapping table into the buffer memory 508 for maintenance, and writes or reads data according to the logical address-physical address mapping table.

It should be noted that, since the buffer 508 has a limited capacity and cannot store a mapping table for recording mapping relationships of all logical addresses, in the exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the logical addresses LBA (0) -LBA (h) into a plurality of logical zones LZ (0) -LZ (m), and configures a logical address-physical address mapping table for each logical zone. In particular, when the memory control circuit unit 404 (or the memory management circuit 502) wants to update the mapping of a logical address, the logical address-physical address mapping table corresponding to the logical area to which the logical address belongs is loaded into the buffer memory 508 for updating.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable nonvolatile memory module 406 (for example, a system area dedicated to storing system data in the memory module) by using a program code type. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the rom has a driver code, and when the memory control circuit unit 404 is enabled, the microprocessor unit first executes the driver code segment to load the control command stored in the rewritable nonvolatile memory module 406 into the ram of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment of the invention, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the entity erasing unit of the rewritable nonvolatile memory module 406; the memory writing circuit is used for issuing a writing instruction to the rewritable nonvolatile memory module 406 so as to write data into the rewritable nonvolatile memory module 406; the memory reading circuit is used for sending a reading instruction to the rewritable nonvolatile memory module 406 so as to read data from the rewritable nonvolatile memory module 406; the memory erasing circuit is used for issuing an erasing instruction to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406; the data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406.

Referring to fig. 6, the host interface 504 is electrically connected to the memory management circuit 502 and is electrically connected to the connection interface unit 402 for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may also be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the UHS-I interface standard, the UHS-II interface standard, the SD standard, the MS standard, the MMC standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506.

The buffer memory 508 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406.

The power management circuit 510 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.

The error checking and correcting circuit 512 is electrically connected to the memory management circuit 502 and is used for performing an error checking and correcting process to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the Error Checking and Correcting circuit 512 generates an Error Checking and Correcting Code (ECC Code) corresponding to the data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC Code into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the corresponding error checking and correcting codes are simultaneously read, and the error checking and correcting circuit 512 performs an error checking and correcting process on the read data according to the error checking and correcting codes.

In the present exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) records a flush command count, and the memory control circuit unit 404 (or the memory management circuit 502) updates the flush command count each time a flush command is received from the host system 11. For example, the memory control circuit unit 404 (or the memory management circuit 502) will add 1 to the current value of the current flush instruction count as the updated flush instruction count.

In particular, whenever one physical unit is full and another physical unit is erased from the idle region 604 as a new physical unit, the memory control circuit 404 (or the memory management circuit 502) determines whether the flush instruction count is greater than the flush instruction count threshold. If the bin-clearing instruction count is greater than the bin-clearing instruction count threshold, the memory control circuit unit 404 (or the memory management circuit 502) sets the write mode of the currently active physical unit to the first write mode; if the number of the flush command counts is not greater than the threshold number, the memory control circuit unit 404 (or the memory management circuit 502) sets the write mode of the currently active physical unit to the second write mode. After the write mode of the currently active physical unit is set, the memory control circuit unit 404 (or the memory management circuit 502) resets the flush instruction count. For example, the memory control circuitry 404 (or the memory management circuitry 502) may reset the value of the flush instruction count to 0. That is, in the exemplary embodiment, each time a new active entity unit is replaced, the memory control circuit 404 (or the memory management circuit 502) determines the write mode of the current active entity unit according to the current count of the flush instruction.

The first write mode is a program mode in which one memory cell stores one bit of data. For example, in the first write mode, the memory control circuit unit 404 (or the memory management circuit 502) programs the memory cells constituting the active physical unit in a single layer memory cell (SLC) mode, a lower physical programming (lower physical programming) mode, a hybrid programming (mixture programming) mode, or a less layer memory cell (lower layer memory cell) mode. That is, in the first write mode, the memory control circuit unit 404 (or the memory management circuit 502) only performs the data write operation on the next physical program unit. Thus, only one-third of the capacity of a physically erased cell programmed in the first write mode is used.

The second write mode is a program mode in which one memory cell stores a plurality of bits. For example, in the second writing mode, the memory control circuit unit 404 (or the memory management circuit 502) programs the memory cells constituting the physical operating unit in a multi-level cell (MLC) programming mode, a multiple level (TLC) cell programming mode, or the like. That is, when data is written using the second write mode, the memory control circuit unit 404 (or the memory management circuit 502) programs a physical unit group. It is worth mentioning that the life time of the physically erased cells operated in the second write mode is shorter than that of the physically erased cells operated in the first write mode. Specifically, the number of times each physically erased cell can be written or erased is limited, and when the number of times a physically erased cell is written exceeds a threshold, the physically erased cell may be damaged and cannot be written with data any more, wherein the threshold corresponding to the physically erased cell operated in the second writing mode is lower than the threshold corresponding to the physically erased cell operated in the first writing mode.

As described above, in the present exemplary embodiment, when the bin-clearing instruction count is greater than the bin-clearing instruction count threshold, the memory control circuit unit 404 (or the memory management circuit 502) sets the write mode of the new active physical unit to the first write mode, so that when the bin-clearing instruction is subsequently received, the memory control circuit unit 404 (or the memory management circuit 502) only writes the dummy data into the lower physical programming unit with the next three characters on line, which can greatly reduce the data amount of the dummy data programmed into the rewritable nonvolatile memory module 406.

Referring to fig. 9A, in step S901, after the memory storage device 100 is powered on, the memory control circuit unit 404 (or the memory management circuit 502) establishes the flush command count and sets it to 0, and in step S903, the memory control circuit unit 404 (or the memory management circuit 502) updates the flush command count (for example, adds 1 to the value of the flush command count) each time a flush command is received from the host system 11.

Referring to fig. 9B, in step S905, the memory control circuit unit 404 (or the memory management circuit 502) receives a write command and corresponding write data from the host system 11.

In step S907, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the physical unit has enough space to write the write data.

If the active entity unit has enough space to write the write data, in step S909, the memory control circuit unit 404 (or the memory management circuit 502) issues a sequence command to program the write data to the active entity unit and update the logical address-physical address mapping table according to the write mode of the active entity unit.

If there is not enough space for writing the write data into the physical unit, in step S911, the memory control circuit unit 404 (or the memory management circuit 502) extracts a physical erase unit (hereinafter referred to as a first physical erase unit) from the idle area 604 as a new physical unit. Thereafter, in step S913, the memory control circuit unit 404 (or the memory management circuit 502) determines whether the flush instruction count is greater than the flush instruction count threshold.

If the count of the flushing instructions is not greater than the threshold value of the count of the flushing instructions, in step S915, the memory control circuit unit 404 (or the memory management circuit 502) sets the write mode of the first physical erase unit to the second write mode. If the bin count is greater than the bin count threshold, in step S917, the memory control circuit unit 404 (or the memory management circuit 502) sets the write mode of the first physical erase unit to the first write mode. Thereafter, in step S919, the memory control circuit unit 404 (or the memory management circuit 502) resets the flush instruction count to 0. Then, step S909 is executed to program the data.

It should be noted that, in the present exemplary embodiment, the threshold value of the bin-clearing instruction count is a fixed value, and after the write mode of the active physical unit is set, the memory control circuit unit 404 (or the memory management circuit 502) resets the bin-clearing instruction count to recalculate the number of received bin-clearing instructions after each physical erase unit is used, so as to determine whether the first write mode or the second write mode is used in the next active physical unit. However, the present invention is not limited thereto, and in another exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) keeps counting the flush instruction count without resetting the flush instruction count, and adjusts the write mode of the active physical unit when the flush instruction count reaches a multiple of a predetermined value.

It should be noted that, in the present exemplary embodiment, the bin count threshold is a pre-calculated fixed value. For example, in an example where the physical erase unit has a capacity of 384 Megabytes (MB) and the memory cells of each word line have a capacity of 3MB, during programming of an active physical unit, the amount of dummy data written is the count of the flush command multiplied by 3MB, and the amount of host write data is the capacity of the active physical unit (i.e., the amount of actual programmed data) minus the amount of dummy data written. The actual programmed data amount divided by the host write data amount (also called write amplification) can measure whether the rewritable nonvolatile memory module 406 has too many redundant writes. The more redundant writes that represent the shorter the life of the rewritable nonvolatile memory module 406 when the write expansion value is large in months. If the user sets the tolerable write-expansion value to 1.2, the memory control circuit unit 404 (or the memory management circuit 502) calculates that the flush instruction count must be less than 7 (i.e., 1.2< (384MB/(384 MB-flush instruction count × 9 MB)), so the memory control circuit unit 404 (or the memory management circuit 502) fixedly sets the flush instruction count threshold value to 7.

It should be appreciated, however, that in the exemplary embodiment, the flush instruction count threshold may also be dynamically determined during operation of the memory storage device 100. For example, the memory control circuit unit 404 (or the memory management circuit 502) may actually measure the amount of write data received from the host system 11 and the amount of data actually written to the rewritable nonvolatile memory module 406 over a period of time, thereby calculating the current write amplification value. In particular, if the current write expansion value is greater than the tolerable write expansion value, the memory control circuit unit 404 (or the memory management circuit 502) lowers the flush instruction count threshold (e.g., decreases the current flush instruction count threshold by 1), thereby reducing the dummy data written by executing the flush instruction.

In the above exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) performs the write operation in units of physical erase units. It must be understood, however, that the present invention is not so limited. In another exemplary embodiment, the memory control circuit unit 404 (or the memory management circuit 502) groups the physical erase cells into a plurality of super-physical cells for management, and each super-physical cell includes at least two physical erase cells. For example, when a write command is issued by the host system, the memory control circuit unit 404 (or the memory management circuit 502) may use a super entity unit to program data. For example, at least two physically erased cells in a super-physical cell belong to different operation units, e.g., different planes or dies, so that they can be programmed simultaneously or alternatively. In this example, the memory control circuit unit 404 (or the memory management circuit 502) uses a super entity unit as an active entity unit, and the memory control circuit unit 404 (or the memory management circuit 502) resets the flush instruction count after the super entity unit as the active entity unit is fully written. That is, the memory control circuit unit 404 (or the memory management circuit 502) counts the number of flush instructions received during the period of writing to one super entity unit, thereby determining the write mode when performing the write operation to the next super entity unit.

In summary, the data writing method, the memory control circuit unit and the memory storage device according to the exemplary embodiments of the invention can adjust the writing mode of the physical erase unit according to the frequency of executing the bin purge instruction to reduce the data amount of the dummy data written into the rewritable non-volatile memory module, thereby prolonging the life of the rewritable non-volatile memory module.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by one skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data writing method is used for a rewritable nonvolatile memory module, and is characterized in that the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit is provided with a plurality of lower entity programming units and a plurality of upper entity programming units, and the data writing method comprises the following steps:

recording the bin clearing instruction count;

extracting a first physical erasing unit from the plurality of physical erasing units as an active physical unit;

judging whether the bin clearing instruction count is larger than a bin clearing instruction count threshold value or not;

if the bin-clearing instruction count threshold value is greater than the bin-clearing instruction count threshold value, setting the write mode of the actuation entity unit to a first write mode, wherein in the first write mode, each memory cell constituting the actuation entity unit stores a first number of bits of data; and

if the bin clearing instruction count threshold is not greater than the bin clearing instruction count threshold, setting the write mode of the active entity unit to a second write mode, wherein in the second write mode, each memory cell constituting the active entity unit stores a second number of bits of data, wherein the first number is less than the second number.

2. The data writing method according to claim 1, wherein the step of recording the count of the flush instructions comprises:

the flush command count is updated each time a flush command is received from the host system.

3. The data writing method according to claim 2, wherein the step of recording the count of the flush instructions further comprises:

and resetting the bin cleaning instruction count after setting the write mode setting of the actuating entity unit.

4. The data writing method according to claim 2, wherein the step of updating the flush instruction count includes incrementing the flush instruction count by 1, and the step of resetting the flush instruction count includes setting the flush instruction count to 0.

5. The data writing method of claim 2, wherein the step of extracting the first physically erased cell from the plurality of physically erased cells as the active physical cell comprises: extracting a super-physical unit composed of the first physical erase unit and at least one other physical erase unit from the plurality of physical erase units as the active physical unit,

wherein the step of recording the bin purge instruction count further comprises: resetting the flush instruction count after the super entity unit is full.

6. The data writing method according to claim 1, further comprising:

receiving a write command and write data corresponding to the write command from a host system; and

programming the write data to the actuation entity unit according to the write mode of the actuation entity unit.

7. The data writing method according to claim 1, further comprising:

logically grouping the physical erase units into at least a data region and an idle region,

wherein the step of extracting the first physically erased cell from the plurality of physically erased cells as the active physically unit comprises: and extracting the first entity erasing unit from the idle area as the actuating entity unit.

8. The method of claim 1, wherein each of the plurality of physically erased cells further has a plurality of middle-programmed cells.

9. The data writing method according to claim 1, further comprising:

and dynamically adjusting the bin-clearing instruction counting threshold value according to the host write data volume and the actual programmed data volume.

10. The method of claim 9, wherein dynamically adjusting the bin-clearing command count threshold according to the amount of host-written data and the amount of actual programmed data comprises:

decreasing the bin flush instruction count threshold when a value obtained by dividing the actual programmed data amount by the host write data amount increases.

11. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:

a host interface for electrically connecting to a host system;

a memory interface electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of entity erasing units, and each entity erasing unit has a plurality of lower entity programming units and a plurality of upper entity programming units; and

a memory management circuit electrically connected to the host interface and the memory interface and used for recording the bin-clearing instruction count,

wherein the memory management circuit is further configured to extract a first physical erase unit from the plurality of physical erase units as an active physical unit, and determine whether the bin clearing instruction count is greater than a bin clearing instruction count threshold value,

wherein if the bin-clearing instruction count threshold is greater than the bin-clearing instruction count threshold, the memory management circuit sets a write mode of the actuation entity unit to a first write mode in which each memory cell constituting the actuation entity unit stores a first number of bits of data,

if the bin clearing instruction count threshold is not greater than the bin clearing instruction count threshold, the memory management circuit sets the write mode of the active physical unit to a second write mode, wherein in the second write mode, each memory cell constituting the active physical unit stores a second number of bits of data, wherein the first number is less than the second number.

12. The memory control circuit unit of claim 11, wherein in the operation of recording the count of flush instructions, the memory management circuit updates the count of flush instructions each time a flush instruction is received from the host system.

13. The memory control circuit unit of claim 12, wherein in operation of recording the flush command count, the memory management circuit is further configured to reset the flush command count after setting a write mode setting of the active physical unit.

14. The memory control circuit unit of claim 12, wherein in the operation of updating the flush instruction count, the memory management circuit increments the flush instruction count by 1, and in the operation of resetting the flush instruction count, the memory management circuit sets the flush instruction count to 0.

15. The memory control circuit unit of claim 12, wherein in the operation of extracting the first physical erase unit from the plurality of physical erase units as the active physical unit, the memory management circuit extracts a super physical unit composed of the first physical erase unit and at least one other physical erase unit from the plurality of physical erase units as the active physical unit,

wherein in operation of recording the flush instruction count, the memory management circuitry resets the flush instruction count after the super entity unit is full.

16. The memory control circuit unit of claim 11, wherein the memory management circuit is further configured to receive a write command and write data corresponding to the write command from the host system, and issue a sequence command to program the write data to the active physical unit according to the write mode of the active physical unit.

17. The memory control circuit unit of claim 11, wherein the memory management circuit is further configured to logically group the physically erased cells into at least a data region and an idle region,

wherein in the operation of extracting the first physical erase unit from the plurality of physical erase units as the active physical unit, the memory management circuit extracts the first physical erase unit from the idle region as the active physical unit.

18. The memory control circuit unit of claim 11, wherein each of the plurality of physically erased cells further has a plurality of middle-programmed cells.

19. The memory control circuit unit of claim 11, wherein the memory management circuit is further configured to dynamically adjust the flush command count threshold based on an amount of host write data and an amount of actual program data.

20. The memory control circuit unit of claim 19, wherein in operation to dynamically adjust the threshold value for the count of flush commands based on the amount of host write data and the amount of actual programmed data, the memory management circuit decreases the threshold value for the count of flush commands as a value obtained by dividing the amount of actual programmed data by the amount of host write data increases.

21. A memory storage device, comprising:

the connection interface unit is used for electrically connecting to a host system;

the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit is provided with a plurality of lower entity programming units and a plurality of upper entity programming units; and

a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module, wherein the memory control circuit unit is used for recording the bin-clearing instruction count,

wherein the memory control circuit unit is further configured to extract a first physical erasing unit from the plurality of physical erasing units as an active physical unit, and determine whether the bin clearing instruction count is greater than a bin clearing instruction count threshold value,

wherein if the bin-clearing instruction count threshold is greater than the bin-clearing instruction count threshold, the memory control circuit unit sets a write mode of the actuation entity unit to a first write mode in which each memory cell constituting the actuation entity unit stores a first number of bits of data and resets the bin-clearing instruction count,

if the bin-clearing instruction count threshold is not greater than the bin-clearing instruction count threshold, the memory control circuit unit sets the write mode of the actuation entity unit to a second write mode in which each memory cell constituting the actuation entity unit stores a second number of bits of data, and resets the bin-clearing instruction count, wherein the first number is smaller than the second number.

22. The memory storage device according to claim 21, wherein in the operation of recording the count of the flush command, the memory control circuit unit updates the count of the flush command each time a flush command is received from the host system.

23. The memory storage device of claim 22, wherein in operation of recording the count of flush instructions, the memory control circuit unit is further configured to reset the count of flush instructions after setting a write mode setting of the actuation entity unit.

24. The memory storage device according to claim 22, wherein in the operation of updating the flush instruction count, the memory control circuit unit increments the flush instruction count by 1, and in the operation of resetting the flush instruction count, the memory control circuit unit sets the flush instruction count to 0.

25. The memory storage device of claim 22, wherein in the operation of extracting the first physically erased cell from the plurality of physically erased cells as the active physical unit, the memory control circuit unit extracts a super physical unit composed of the first physically erased cell and at least one other physically erased cell from the plurality of physically erased cells as the active physical unit,

in the operation of recording the bin-clearing instruction count, the memory control circuit unit resets the bin-clearing instruction count after the super entity unit is full.

26. The memory storage device of claim 21 wherein the memory control circuit unit is further configured to receive a write command and write data corresponding to the write command from the host system and issue a sequence command to program the write data to the active entity unit according to the write mode of the active entity unit.

27. The memory storage device of claim 21, wherein the memory control circuit unit is further configured to logically group the physically erased cells into at least a data region and an idle region,

wherein in the operation of extracting the first physical erase unit from the plurality of physical erase units as the active physical unit, the memory control circuit unit extracts the first physical erase unit from the idle area as the active physical unit.

28. The memory storage device of claim 21, wherein each of the plurality of physically erased cells further has a plurality of middle-programmed cells.

29. The memory storage device of claim 21, wherein the memory control circuit unit is further configured to dynamically adjust the flush command count threshold based on a host write data amount and an actual programmed data amount.

30. The memory storage device of claim 29, wherein in operation of dynamically adjusting the bin-clearing command count threshold based on the amount of host-write data and the amount of actual-programmed data, the memory control circuitry unit decreases the bin-clearing command count threshold as a value obtained by dividing the amount of actual-programmed data by the amount of host-write data increases.