CN106932976A - Display device, array base palte and pixel cell - Google Patents

Abstract

The disclosure provides a display device, an array substrate and a pixel unit. The pixel unit includes a plurality of sub-pixels, and each sub-pixel includes a first sub-sub-pixel and a second sub-sub-pixel; the first sub-sub-pixel includes a first pixel electrode and a first thin film transistor, and the first pixel electrode has a plurality of A slit of the first width and a plurality of first sub-electrodes separated by each slit; the control terminal of the first thin film transistor is connected to the first gate line, the first terminal is connected to the first data line, and the second terminal is connected to the second terminal. A pixel electrode; the second sub-sub-pixel includes a second pixel electrode and a second thin film transistor, the second pixel electrode has a plurality of slits with a second width and a plurality of second sub-electrodes separated by each slit, and the second The width is not equal to the first width; the control terminal of the second thin film transistor is connected to the second gate line, the first terminal is connected to the second data line, and the second terminal is connected to the second pixel electrode.

Description

Display device, array substrate and pixel unit

technical field

The present disclosure relates to the field of display technology, and in particular, to a display device, an array substrate and a pixel unit.

Background technique

Currently, in the field of thin film transistor liquid crystal displays, IPS (In-Plane Field Effect) displays and FFS (Fringe Field Effect) displays are widely used because of their advantages of wide viewing angle, high transmittance, and fast response. For the existing IPS display and FFS display, the array substrates of both include a plurality of pixel units distributed in an array, and each pixel unit includes a plurality of sub-pixels; the pixel electrodes of these sub-pixels generally adopt upper and lower dual-domain Symmetrical slit electrodes. Among them, the electrode spacing of the slit electrodes has a relatively obvious influence on the display effect. In other words, the smaller the electrode spacing, the higher the transmittance and driving voltage of liquid crystal molecules, so the brightness and power consumption are higher; the larger the electrode spacing, the lower the transmittance and driving voltage of liquid crystal molecules, so the brightness is higher. and lower power consumption.

In the prior art, the structure and working mode of the existing pixel unit are single, in order to obtain high transmittance and high brightness to improve the display effect, the driving voltage will be increased, and the power consumption will be increased accordingly; Reducing power consumption will reduce the transmittance and brightness, and can only display the display effect of low gray scale and low brightness images; therefore, it is impossible to achieve multiple brightness and different power consumption requirements, and the scope of application is small. It is beneficial for the user to adjust according to the actual situation.

It should be noted that the information disclosed in the above background section is only for enhancing the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.

Contents of the invention

The purpose of the present disclosure is to provide a display device, an array substrate, and a pixel unit, so as to overcome one or more problems caused by limitations and defects of related technologies at least to a certain extent.

According to one aspect of the present disclosure, a pixel unit is provided, including a plurality of sub-pixels, each of which includes a first sub-sub-pixel and a second sub-sub-pixel; wherein:

The first sub-sub-pixel includes:

a first pixel electrode having a plurality of slits of a first width and a plurality of first sub-electrodes separated by each of the slits;

a first thin film transistor, the control terminal of the first thin film transistor is connected to the first gate line, the first terminal is connected to the first data line, and the second terminal is connected to the first pixel electrode;

The second sub-sub-pixel includes:

A second pixel electrode, the second pixel electrode has a plurality of slits with a second width and a plurality of second sub-electrodes separated by each of the slits, and the second width is not equal to the first width ;

A second thin film transistor, the control terminal of the second thin film transistor is connected to the second gate line, the first terminal is connected to the second data line, and the second terminal is connected to the second pixel electrode.

In an exemplary embodiment of the present disclosure, the control terminal of the first thin film transistor and the control terminal of the second thin film transistor are connected to the same gate line, and the first gate line and the second gate line for the same grid line;

The first end of the first thin film transistor and the first end of the second thin film transistor are connected to different data lines, and the first data line and the second data line are different data lines.

In an exemplary embodiment of the present disclosure, the control terminal of the first thin film transistor and the control terminal of the second thin film transistor are connected to different gate lines, and the first gate line and the second gate The lines are different raster lines;

The first end of the first thin film transistor and the first end of the second thin film transistor are connected to the same data line, and the first data line and the second data line are the same data line.

In an exemplary embodiment of the present disclosure, the first pixel electrode includes a first region and a second region, a plurality of first sub-electrodes are distributed in the first region and the second region, and the The first sub-electrodes in the second region and the first sub-electrodes in the first region are arranged at a first angle and do not intersect, and the first angle is less than 180°;

The second pixel electrode includes a third area and a fourth area, a plurality of second sub-electrodes are distributed in the third area and the fourth area, and the second sub-electrodes in the fourth area are connected to the The second sub-electrodes in the third region are arranged at a second angle and do not intersect each other, and the second angle is less than 180°.

In an exemplary embodiment of the present disclosure, the sum of the first width and the width of one of the first sub-electrodes is 7.35 μm; the sum of the second width and the width of one of the second sub-electrodes is 8.8 μm.

According to one aspect of the present disclosure, there is provided an array substrate, comprising:

A plurality of pixel units described in any one of the above arrays;

A plurality of gate lines, in the same pixel unit, the control terminals of each of the first thin film transistors and the control terminals of each of the second thin film transistors are connected to the same gate line;

A plurality of data lines, arranged alternately with the plurality of gate lines, in the same pixel unit, the first end of each of the first thin film transistors and the first end of each of the second thin film transistors are connected to different the data line.

In an exemplary embodiment of the present disclosure, in the same row of the sub-pixels of the same row of the pixel units, each of the first sub-sub-pixels and each of the second sub-sub-pixels are arranged in two rows, in,

Each of the first sub-subpixels is located in the same row, and each of the second sub-subpixels is located in another row; or

Each of the first sub-sub-pixels and each of the second sub-sub-pixels are spaced apart from each other.

According to one aspect of the present disclosure, there is provided an array substrate, comprising:

A plurality of pixel units described in any one of the above arrays;

A plurality of gate lines, in the same pixel unit, the control terminal of each of the first thin film transistors and the control terminal of each of the second thin film transistors are connected to different gate lines;

A plurality of data lines are arranged alternately with the plurality of gate lines, and in the same pixel unit, the first end of each of the first thin film transistors and the first end of each of the second thin film transistors are connected to the same the data line.

In an exemplary embodiment of the present disclosure, in the same row of the sub-pixels of the same row of the pixel units, each of the first sub-sub-pixels and each of the second sub-sub-pixels are arranged in two rows, in,

Each of the first sub-subpixels is located in the same row, and each of the second sub-subpixels is located in another row; or

Each of the first sub-sub-pixels and each of the second sub-sub-pixels are spaced apart from each other.

According to one aspect of the present disclosure, a display device is provided, including the array substrate described in any one of the above.

In the display device, array substrate and pixel unit of the present disclosure, in the same sub-pixel of the same pixel unit, the first pixel electrode of the first sub-sub-pixel has a slit of the first width, and the second pixel of the second sub-sub-pixel The electrode has a slit with a second width; so that the same sub-pixel can have two electrode spacings; at the same time, the first sub-sub-pixel can be controlled by the first thin film transistor, and the second sub-sub-pixel can be controlled by the second thin film transistor; One of the first pixel electrode or the second pixel electrode works alone or both work simultaneously to adjust the transmittance of liquid crystal molecules and the driving voltage, so as to realize the adjustment of brightness and power consumption. In this way, it is convenient to better meet the needs of users according to the actual situation.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description serve to explain the principles of the disclosure. Apparently, the drawings in the following description are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of an embodiment of a pixel unit of the present disclosure.

FIG. 2 is a schematic diagram of the first sub-sub-pixel in FIG. 1 .

FIG. 3 is a schematic diagram of a second sub-sub-pixel in FIG. 1 .

FIG. 4 is a schematic diagram of another embodiment of a pixel unit of the present disclosure.

FIG. 5 is a schematic diagram of a first embodiment of an array substrate of the present disclosure.

FIG. 6 is a schematic diagram of a second embodiment of an array substrate of the present disclosure.

FIG. 7 is a schematic diagram of a third embodiment of an array substrate of the present disclosure.

FIG. 8 is a schematic diagram of a fourth embodiment of an array substrate of the present disclosure.

detailed description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solution of the present disclosure may be practiced without one or more of the specific details, or other components, devices, etc. may be used. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

The terms "a", "an", "the" and "said" are used to indicate the presence of one or more elements/components/etc; means and means that there may be additional elements/components/etc. in addition to the listed elements/components/etc; the terms "first" and "second" etc. Limit; "plurality" means two or more.

pixel unit

An exemplary embodiment of the present disclosure provides a pixel unit, which can be used in a thin film transistor array substrate, as shown in FIGS. 1 to 3 , the pixel unit in this embodiment may include a plurality of sub-pixels 1 , and a sub-pixel is represented in a dotted line box in FIG. 1 1; each sub-pixel 1 can be used to display different colors, for example, when a pixel unit includes three sub-pixels 1, the three sub-pixels 1 can be used to display three colors of red, blue and green respectively; The number of sub-pixels 1 in a pixel unit is specifically limited, which may be three, four or more; each sub-pixel 1 may include a first sub-sub-pixel 11 and a second sub-sub-pixel 12 .

In this embodiment, as shown in FIG. 2 , the first sub-subpixel 11 may include a first pixel electrode 111 and a first thin film transistor 112, wherein:

The first pixel electrode 111 may have a plurality of slits 1111 with a width of the first width d1 and a plurality of _first sub-electrodes 1112 separated by each slit 1111; the numbers of the slits 1111 and the first sub-electrodes 1112 are not limited here. Special limited. Further, the first pixel electrode 111 can be divided into a first area and a second area, and a plurality of first sub-electrodes 1112 are distributed in the first area and the second area; the first sub-electrodes in the first area 1112 may be parallel to each other, the first sub-electrodes 1112 in the second region may be parallel to each other, and the first sub-electrodes 1112 in the first region and the first sub-electrodes 1112 in the second region may be arranged at a first angle and do not intersect to form a double-domain slit electrode; the angle of the first included angle may be less than 180°, such as 60°, 90° or 120°.

The sum of the first width d ₁ and the width d ₂ of any one of the first sub-electrodes 1112 is the electrode spacing D ₁ of the first pixel electrode 111, that is, d ₁ +d ₂ =D ₁ ; the electrode spacing D ₁ can be 7.35 μm , that is, D ₁ =7.35 μm; wherein, the first width d ₁ can be 4.45 μm, and the width d ₂ of the first sub-electrode 1112 can be 2.9 μm; but the above-mentioned values of D ₁ , d ₁ and d ₂ are only exemplary Note that it should not be understood as a limitation on the values. In other embodiments of the present disclosure, the values of D ₁ , d ₁ and d ₂ can also be other values, as long as d ₁ +d ₂ =D ₁ is satisfied , will not be listed here.

The first thin film transistor 112 can have a control terminal, a first terminal and a second terminal, the control terminal can be a gate, can be used to connect to the first gate line; its first terminal can be a source, can be used to connect to the first The data line; its second end can be a drain, which can be used to connect to the first pixel electrode 111 .

In this embodiment, as shown in FIG. 3 , the second sub-subpixel 12 may include a second pixel electrode 121 and a second thin film transistor 122, wherein:

The second pixel electrode 121 may have a plurality of slits 1211 having a width of a second width d ₁ ' and a plurality of second sub-electrodes 1212 separated by each of the slits 1211, and the second width d ₁ ' may be the same as the first _The widths d1 are not equal; the number of the second sub-electrodes 1212 is not specifically limited here. Further, the second pixel electrode 121 can be divided into a third area and a fourth area, and a plurality of second sub-electrodes 1212 are distributed in the third area and the fourth area; the second sub-electrodes in the third area 1212 may be parallel to each other, the second sub-electrodes 1212 in the fourth region may be parallel to each other, and the second sub-electrodes 1212 in the third region and the second sub-electrodes 1212 in the fourth region may be arranged at a second angle and do not intersect to form a double-domain slit electrode; the angle of the second included angle may be less than 180°, such as 60°, 90° or 120°. The second included angle may be the same as or different from the above-mentioned first included angle.

The sum of the second width d ₁ ′ and the width d ₂ ′ of any second sub-electrode 1212 is the electrode spacing D ₂ of the second pixel electrode 121, that is, d ₁ ′+d ₂ ′=D ₂ ; the electrode spacing D ₂ can be 8.8 μm, that is, D ₂ =8.8 μm; wherein, the second width d ₁ ′ can be 5.9 μm, and the width d ₂ ′ of the second sub-electrode 1212 can be 2.9 μm; but the above-mentioned D ₂ , d ₁ ′ and d The value of ₂ ' is only for illustration and should not be understood as a limitation on the value; in other embodiments of the present disclosure, the values of D ₂ , d ₁ ' and d ₂ ' can also be other values, as long as It only needs to satisfy d ₁ ′+d ₂ ′=D ₂ , and D ₂ is not equal to D ₁ , and will not be listed here.

The second thin film transistor 122 can have a control terminal, a first terminal and a second terminal, and its control terminal can be a gate, which can be used to connect to the second gate line; its first terminal can be a source, which can be used to connect to the second gate line. The data line; its second end can be a drain, which can be used to connect to the second pixel electrode 121 .

In this embodiment, both the control terminal of the first thin film transistor 112 and the control terminal of the second thin film transistor 122 can be connected to the same gate line, and the above-mentioned first gate line and the second gate line can be the same gate line; thus, Simultaneously output signals to the first thin film transistor 112 and the second thin film transistor 122 through the same gate line. The two thin film transistors 122 output electrical signals.

The first end of the first thin film transistor 112 and the first end of the second thin film transistor 122 can be respectively connected to different data lines, and the above-mentioned first data line and second data line can be different data lines; The data line controls the first thin film transistor 112 and the second thin film transistor 122, so that one of the first sub-sub-pixel 11 and the second sub-sub-pixel 12 can be controlled to work independently or simultaneously through different data lines.

In other embodiments of the present disclosure, the first end of the first thin film transistor 112 and the first end of the second thin film transistor 122 may be connected to the same data line, and the above-mentioned first data line and second data line may be the same data line. line; so that the same data line can be used to simultaneously output signals to the first thin film transistor 112 and the second thin film transistor 122, for an array substrate with multiple pixel units, the same data line can be used to simultaneously output signals to multiple first thin film transistors 112 and a plurality of second thin film transistors 122 to output signals.

The control terminal of the first thin film transistor 112 and the control terminal of the second thin film transistor 122 can also be respectively connected to different gate lines, the above-mentioned first gate line and second gate line are different gate lines; The lines control the first TFT 112 and the second TFT 122 , so that one of the first sub-subpixel 11 and the second sub-subpixel 12 can be controlled to work independently or simultaneously through different gate lines.

In this embodiment, for the relative positional relationship between the first sub-sub-pixel 11 and the second sub-sub-pixel 12 in the sub-pixel 1, the relative positional relationship between the first thin-film transistor 112 and the first sub-sub-pixel 11, and the second thin film The relative positional relationship between the transistor 122 and the second sub-sub-pixel 12 is not particularly limited, and the above-mentioned relative positional relationship can be changed according to actual conditions. For example, in the same pixel unit, as shown in FIG. 1, each first sub-sub-pixel 11 can be located in the same row, and each second sub-sub-pixel 12 can be located in another row; or, as shown in FIG. 4, the first sub-sub-pixel 11 It is arranged in two rows, and a second sub-sub-pixel 12 is arranged between two adjacent first sub-sub-pixels 11 , that is, the first sub-sub-pixel 11 and the second sub-sub-pixel 12 are arranged at intervals.

The working principle of the pixel unit of the example embodiment of the present disclosure:

When only the first sub-sub-pixel 11 is working, because the first sub-sub-pixel ₁₁ electrode spacing D1 is relatively small, the transmittance of the liquid crystal is relatively high, the power consumption at this time is moderate, and the brightness of display is moderate; When the second sub-sub-pixel 12 is working, because the second sub-sub-pixel 12 has a larger electrode spacing D ₂ , the transmittance of the liquid crystal is lower, the power consumption at this moment is smaller, and the brightness is lower; when the first sub-sub-pixel 11 and When the second sub-sub-pixels 12 work at the same time, the overall transmittance of the liquid crystal is the highest, the power consumption at this time is the highest, and the display brightness is the highest.

Based on the above-mentioned working principle of the pixel unit, the pixel unit in the exemplary embodiment of the present disclosure is convenient for the user to select the brightness and power consumption according to the actual situation, and expands the scope of application.

The first embodiment of the disclosed array substrate

Example embodiments of the present disclosure provide an array substrate, as shown in FIG. 5 , the array substrate in this embodiment may include gate lines 2 , data lines 3 and pixel units.

In this embodiment, the composition of the pixel unit can refer to the pixel unit in the above embodiment of the pixel unit; the number of the pixel units can be multiple, and the multiple pixel units are arranged in an array, that is, the array substrate can have multiple rows and multiple columns of pixel units, the sub-pixels 1 in the pixel units may also be arranged in multiple rows and columns. For example, in the same row of sub-pixels 1 in the same row of pixel units, as shown in Figure 5, each first sub-sub-pixel 11 and each second sub-sub-pixel 12 can be divided into two rows, wherein each first The sub-pixels 11 may all be located in the same row, and each second sub-sub-pixel 12 may be located in another row.

The number of gate lines 2 can be multiple, and multiple gate lines 2 can be distributed in parallel; in the same pixel unit, the control terminals of each first thin film transistor 112 and the control terminals of each second thin film transistor 122 are connected to the same gate Line 2 , that is, the first thin film transistor 112 and the second thin film transistor 122 in the same pixel unit may be separated by one gate line 2 .

The number of data lines 3 can be multiple, and multiple data lines 3 can be arranged alternately with multiple gate lines 2, and each pixel unit can be respectively located in the area enclosed by the multiple data lines 3 and multiple gate lines 2 In the same pixel unit, the first end of each first thin film transistor 112 and the first end of each second thin film transistor 122 can be connected to different data lines 3 ;

The second embodiment of the disclosed array substrate

Example embodiments of the present disclosure provide an array substrate, as shown in FIG. 6 , the array substrate in this embodiment may include gate lines 2 , data lines 3 and pixel units.

In this embodiment, the composition of the pixel unit can refer to the pixel unit in the above-mentioned embodiment of the pixel unit; Relevant content will not be repeated here; in addition, each first sub-sub-pixel 11 and each second sub-sub-pixel 12 can be divided into two rows, and any row is distributed with the first sub-sub-pixel 11 and the second sub-pixel The sub-pixels 12, the first sub-sub-pixels 11 and the second sub-sub-pixels 12 in each row are spaced apart from each other.

The above-mentioned array substrates of the first embodiment and the second embodiment can simultaneously send signals to the first thin film transistor 112 and the second thin film transistor 122 connected to the gate line 2 through the gate line 2 during operation; and then Send signals to the first thin film transistor 112 and the second thin film transistor 122 through different data lines 3, so as to control the first sub-sub-pixel unit 11 and the second sub-sub-pixel unit through the first thin film transistor 112 and the second thin film transistor 122 One of the 12 works alone or at the same time; according to the above-mentioned working principle of the pixel unit, display effects with different brightness and power consumption can be realized, which is convenient for users to choose brightness and power consumption according to the actual situation, and expands the scope of application.

The third embodiment of the disclosed array substrate

Example embodiments of the present disclosure provide an array substrate, as shown in FIG. 7 , the array substrate in this embodiment may include gate lines 2 , data lines 3 and pixel units.

In this embodiment, the composition of the pixel unit can refer to the pixel unit in the above embodiment of the pixel unit; the number of the pixel units can be multiple, and the multiple pixel units are arranged in an array, that is, the array substrate can have multiple rows and multiple columns of pixel units, the sub-pixels 1 in the pixel units may also be arranged in multiple rows and columns. For example, in the same row of sub-pixels 1 in the same row of pixel units, as shown in Figure 7, each first sub-sub-pixel 11 and each second sub-sub-pixel 12 can be divided into two rows, wherein each first The sub-pixels 11 can all be located in the same row, and each second sub-sub-pixel 12 can be located in another row; the number of gate lines 2 can be multiple, and a plurality of gate lines 2 can be distributed in parallel; in the same pixel unit, each second sub-pixel The control terminal of one thin film transistor 112 and the control terminals of each second thin film transistor 122 can be connected to different gate lines 2 .

The number of data lines 3 can be multiple, and multiple data lines 3 can be arranged alternately with multiple gate lines 2, and each pixel unit can be respectively located in the area enclosed by the multiple data lines 3 and multiple gate lines 2 ; In the same pixel unit, the first end of each first thin film transistor 112 and the first end of each second thin film transistor 122 can be connected to the same data line 3; that is, the first thin film transistor 112 and the first end of the same pixel unit The second thin film transistor 122 may be separated by one data line 3 .

Fourth Embodiment of the Disclosed Array Substrate

Example embodiments of the present disclosure provide an array substrate, as shown in FIG. 8 , the array substrate in this embodiment may include gate lines 2 , data lines 3 and pixel units.

In this embodiment, the composition of the pixel unit can refer to the pixel unit in the above-mentioned embodiment of the pixel unit; as shown in Figure 8, the arrangement of the gate line 2 and the data line 3 can refer to the above-mentioned third embodiment of the array substrate. Relevant content will not be repeated here; in addition, as shown in Figure 8, each first sub-sub-pixel 11 and each second sub-sub-pixel 12 can be divided into two rows, and any row is distributed with first sub-sub-pixels 11 and the second sub-sub-pixels 12 , the first sub-sub-pixels 11 and the second sub-sub-pixels 12 in each row are spaced apart from each other.

The above-mentioned array substrates of the third embodiment and the fourth embodiment can simultaneously send signals to the first thin film transistor 112 and the second thin film transistor 122 connected to the data line 3 through the data line 3 during operation; and Signals are respectively sent to the first thin film transistor 112 and the second thin film transistor 122 through different gate lines 2, thereby controlling the first sub-sub-pixel unit 11 and the second sub-sub-pixel unit through the first thin film transistor 112 and the second thin film transistor 122 One of the 12 works alone or at the same time; according to the above-mentioned working principle of the pixel unit, display effects with different brightness and power consumption can be realized, which is convenient for users to choose brightness and power consumption according to the actual situation, and expands the scope of application.

It should be noted that, for the above-mentioned first embodiment, second embodiment, third embodiment and fourth embodiment of the array substrate, the first sub-sub-pixel 11 and the second sub-sub-pixel 12 The distribution method of is not limited to the methods listed above, and other methods can also be used, which will not be listed here.

Exemplary embodiments of the present disclosure provide a display device. The display device in this embodiment may include the array substrate described in any one of the above embodiments, and can solve corresponding technical problems and achieve corresponding technical effects, which will not be repeated here.

Other embodiments of the present disclosure will be readily apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, and these modifications, uses or adaptations follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure . The specification and examples are to be considered exemplary only, with the true scope and spirit of the disclosure indicated by the appended claims.

Claims (10)

1. A pixel unit, comprising a plurality of sub-pixels, wherein each of the sub-pixels includes a first sub-sub-pixel and a second sub-sub-pixel; wherein: The first sub-sub-pixel includes: a first pixel electrode having a plurality of slits of a first width and a plurality of first sub-electrodes separated by each of the slits; a first thin film transistor, the control terminal of the first thin film transistor is connected to the first gate line, the first terminal is connected to the first data line, and the second terminal is connected to the first pixel electrode; The second sub-sub-pixel includes: A second pixel electrode, the second pixel electrode has a plurality of slits with a second width and a plurality of second sub-electrodes separated by each of the slits, and the second width is not equal to the first width ; A second thin film transistor, the control terminal of the second thin film transistor is connected to the second gate line, the first terminal is connected to the second data line, and the second terminal is connected to the second pixel electrode. 2. The pixel unit according to claim 1, wherein the control terminal of the first thin film transistor and the control terminal of the second thin film transistor are connected to the same gate line, and the first gate line and the The second grid line is the same grid line; The first end of the first thin film transistor and the first end of the second thin film transistor are connected to different data lines, and the first data line and the second data line are different data lines. 3. The pixel unit according to claim 1, wherein the control terminal of the first thin film transistor and the control terminal of the second thin film transistor are connected to different gate lines, and the first gate line and the control terminal of the second thin film transistor are connected to different gate lines. The second grid line is a different grid line; The first end of the first thin film transistor and the first end of the second thin film transistor are connected to the same data line, and the first data line and the second data line are the same data line. 4. The pixel unit according to any one of claims 1-3, wherein the first pixel electrode comprises a first region and a second region, and multiple first sub-electrodes, and the first sub-electrodes in the second region and the first sub-electrodes in the first region are arranged at a first angle and do not intersect, and the first angle is less than 180° ; The second pixel electrode includes a third area and a fourth area, a plurality of second sub-electrodes are distributed in the third area and the fourth area, and the second sub-electrodes in the fourth area are connected to the The second sub-electrodes in the third region are arranged at a second angle and do not intersect each other, and the second angle is less than 180°. 5. The pixel unit according to any one of claims 1-3, wherein the sum of the first width and the width of one of the first sub-electrodes is 7.35 μm; the second width and the width of one of the first sub-electrodes The sum of the widths of the second sub-electrodes is 8.8 μm. 6. An array substrate, characterized in that, comprising: A plurality of pixel units according to any one of claims 1 to 5 distributed in an array; A plurality of gate lines, in the same pixel unit, the control terminals of each of the first thin film transistors and the control terminals of each of the second thin film transistors are connected to the same gate line; A plurality of data lines, arranged alternately with the plurality of gate lines, in the same pixel unit, the first end of each of the first thin film transistors and the first end of each of the second thin film transistors are connected to different the data line. 7. The array substrate according to claim 6, characterized in that, in the same row of the sub-pixels of the same row of the pixel units, each of the first sub-sub-pixels is separated from each of the second sub-sub-pixels Two lines of settings, where, Each of the first sub-subpixels is located in the same row, and each of the second sub-subpixels is located in another row; or Each of the first sub-sub-pixels and each of the second sub-sub-pixels are spaced apart from each other. 8. An array substrate, characterized in that it comprises: A plurality of pixel units according to any one of claims 1 to 5 distributed in an array; A plurality of gate lines, in the same pixel unit, the control terminal of each of the first thin film transistors and the control terminal of each of the second thin film transistors are connected to different gate lines; A plurality of data lines are arranged alternately with the plurality of gate lines, and in the same pixel unit, the first end of each of the first thin film transistors and the first end of each of the second thin film transistors are connected to the same the data line. 9. The array substrate according to claim 8, characterized in that, in the same row of the sub-pixels of the same row of the pixel units, each of the first sub-sub-pixels is separated from each of the second sub-sub-pixels Two lines of settings, where, Each of the first sub-subpixels is located in the same row, and each of the second sub-subpixels is located in another row; or Each of the first sub-sub-pixels and each of the second sub-sub-pixels are spaced apart from each other. 10. A display device, characterized in that it comprises: The array substrate of claim 6 or claim 7; or The array substrate according to claim 8 or claim 9.