CN106936736A - Expansible network on mating plate structure and its communication means based on double-deck layout - Google Patents

Abstract

The invention discloses an expandable optical on-chip network structure and a communication method based on a double-layer layout, and mainly solves the problems of large network structure crossover loss and large communication delay overhead in the existing optical on-chip network. The structure includes optical routers, optical waveguides, and intellectual property IP cores. Each six-port optical router is connected to two intellectual property IP cores and four optical waveguides. on the substrate. The communication method is as follows: establishing a coordinate system in the scalable optical on-chip network; determining the transmission path of the signal; configuring the optical router port on the transmission path; sending the optical signal; receiving and processing the optical signal. The invention effectively optimizes the network structure layout on the optical chip, and improves the expansion performance and communication efficiency of the network on the optical chip.

Description

Scalable optical network-on-chip architecture and communication method based on double-layer layout

technical field

The present invention belongs to the technical field of communication, and further relates to a scalable optical network-on-chip network structure and a communication method based on a double-layer layout in the technical field of multi-core node interconnection in Optical Network-on-Chip (ONoC). The present invention is based on an expandable optical on-chip network structure and a communication method based on a double-layer layout, and is used to build an on-chip intellectual property (Intellectual Property, IP) core interconnection network, realize information transmission between IP cores, and improve on-chip network communication efficiency.

Background technique

Compared with traditional on-chip electrical interconnection methods, optical interconnection through optical signals has the advantages of higher bandwidth density, smaller communication delay, lower system power consumption, and smaller network crosstalk. In recent years, the continuous progress of silicon-based optical device technology has promoted the emergence and rapid development of optical on-chip networks. However, since optical storage cannot be effectively integrated and optical logic processing technology is still immature, communication resources need to be pre-allocated. Optical network on chip usually uses optical circuit switching mechanism to realize communication between IP cores.

Xidian University disclosed in its patented technology "Optical On-Chip Network System and Communication Method for Non-blocking Communication" (application date: July 17, 2012, application number: CN 201210245590.5, authorization announcement number: 102780936B) An optical on-chip network system and a communication method for non-blocking communication mainly solve the blocking problem existing in the existing optical on-chip network. The system includes an optical transmission network and an electrical control network. Each node in the optical transmission network includes an IP core, a sending unit, a receiving unit, and an optical switching unit. The sending wavelength of each sending unit is fixed, and the optical switching unit is composed of an optical vertical switch. The internal structure of the unit is the same. However, the shortcomings of this system are: the layout of the waveguide in the optical switching unit is not optimized enough, resulting in large crossover loss of the optical on-chip network, limited expansion capability, and low application value.

Fudan University disclosed in its patent document "A Mesh Topology-Based On-Chip Network Communication Method" (application date: June 18, 2013, application number: CN201310242869.2, publication number: 106254254A) which discloses a method based on On-chip network communication method of Mesh topology. The method is mainly used to improve the transmission efficiency of optical on-chip network data, including the main core according to a certain routing algorithm to transmit data from near to far to each sub-core, and the on-chip network communication adopts the data transmission mode of packet switching. However, the disadvantages of this method are: with the expansion of the integration scale based on the Mesh structure, the diameter of the network increases, and the average number of communication hops increases. Using this communication method, the delay overhead of near-to-far transmission is relatively large.

Xidian University disclosed a method based on microring resonance in its patent document "Communication Method for Three-dimensional Optical Chip Network" (application date: April 22, 2016, application number: 201610255814.9, publication number: CN 105959239A). The optical switching unit of the device mainly solves the problems of low utilization rate of communication links in the existing three-dimensional optical on-chip network, single node blocking affects communication of other nodes, large communication delay and low network throughput. The method retransmits the resource reservation group according to the real-time situation of the network when the resource reservation group is blocked at an intermediate node, and optimizes the retransmission condition of the resource reservation group during the resource reservation group retransmission process. However, the disadvantages of this method are: the blocking problem is solved through the retransmission mechanism, the network flexibility is low, and the method ignores the network communication for specific applications.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned deficiencies in the prior art, and propose a scalable optical network on chip structure and communication method based on a double-layer layout, reduce waveguide crossover in the network, reduce communication loss of the network on chip, and improve the expansion of the optical network on chip performance and communication efficiency.

The specific idea of the present invention is: two kinds of mirror-symmetrical staggered-layer six-port optical routers arranged alternately are connected to the intellectual property IP core and the optical waveguide, and the upper and lower silicon substrates are etched alternately through the optical waveguide to reduce network traffic. cross loss. The transmission path of the optical signal is determined through the horizontal and vertical coordinates of the source intellectual property IP core and the destination intellectual property IP core. Improve the efficiency of network communication on optical chips.

To achieve the above object, the present invention includes a scalable optical network on chip structure based on a double-layer layout and a communication method thereof.

The scalable optical on-chip network structure based on a double-layer layout includes upper and lower silicon substrates and 2N ² six-port optical routers etched on the upper and lower silicon substrates, 4N ² optical waveguides, through six-port optical routers and optical 4N ² intellectual property IP cores connected by waveguide, where N is a positive integer greater than or equal to 3.

2N ² six-port optical routers, which are composed of two kinds of staggered-layer six-port optical routers that are symmetrical to each other. The two local ports in each six-port optical router are respectively connected to two intellectual property IP cores, and the remaining four Each interconnection port is connected to other six-port optical routers through waveguides to realize the reception and forwarding of optical signals in the network.

4N ² optical waveguides are etched alternately on the upper and lower silicon substrates, and each optical waveguide is connected to two six-port optical routers to realize the transmission of optical signals in the network.

4N ² intellectual property IP cores to realize the processing of optical signals in the network.

Based on the scalable on-chip network communication method of the double-layer layout, the scalable on-chip network structure of the double-layer layout is used to transmit the optical signal and complete the communication between the intellectual property IP cores. The specific steps include the following:

(1) Establish a coordinate system in the scalable optical-on-chip network:

(1a) Taking the horizontal symmetry axis in the scalable optical-on-chip network as the positive direction to the right, and the vertical symmetry axis as the positive direction, establish a plane Cartesian coordinate system.

(1b) Taking the center interval of adjacent optical routers in the scalable optical network on chip as the unit length, determine the coordinate value of each optical router in turn, and the coordinate value of each intellectual property IP core is the same as the coordinate value of the optical router connected to it.

(2) Determine the transmission path of the signal:

By calculating the product value and coordinate weight of the horizontal and vertical coordinates of the source intellectual property IP core and the target intellectual property IP core respectively, the relative position of the source intellectual property IP core and the target intellectual property IP core is judged, and the transmission path of the signal is determined.

(3) Configure the optical router port on the transmission path:

(3a) The source intellectual property IP core sends control signals.

(3b) The control signal is transmitted to the target intellectual property IP core along the determined signal transmission path.

(3c) The control signal configures the optical router port on the transmission path.

(3d) The destination intellectual property IP core generates and sends a response signal after receiving the control signal, and the response signal returns to the source intellectual property IP core along the transmission path.

(4) Send optical signal:

The source intellectual property IP core generates and sends an optical signal after receiving the response signal, and the optical signal is transmitted to the destination intellectual property IP core along the transmission path.

(5) Receive optical signal:

(5a) The target intellectual property IP core receives the optical signal.

(5b) The destination intellectual property IP core generates and sends an epilogue signal, and the epilogue signal is transmitted to the source intellectual property IP core, and the configured optical router port is released along the transmission path.

Compared with existing systems, the present invention has the following advantages:

First, because the present invention is based on the double-layer layout of the scalable optical on-chip network structure, 4N ² optical waveguides are etched alternately on the upper and lower silicon substrates, which overcomes the insufficient optimization of the waveguide layout in the optical switching unit in the prior art, The problem of large network crossing loss and limited expansion capability on the optical chip makes the present invention have the advantages of small network loss, high energy utilization rate and strong scalability.

Second, because the optical signal is transmitted along the transmission path in the scalable optical network-on-chip communication method based on the double-layer layout of the present invention, it overcomes the large time delay overhead of the communication method based on the Mesh structure in the prior art from near to far. problem, so that the present invention has the advantages of low delay, high throughput, and high bandwidth.

Third, due to the scalable optical-on-chip network communication method based on the double-layer layout of the present invention, the source knowledge is judged by calculating the product value and coordinate weight of the horizontal and vertical coordinates of the source intellectual property IP core and the target intellectual property IP core respectively. The relative position of the IP core of the property right and the IP core of the target intellectual property determines the transmission path of the signal, which overcomes the problems of low network flexibility and neglect of network communication for specific applications in the prior art, making the present invention have high communication efficiency and application-oriented wide advantages.

Description of drawings

Fig. 1 is two kinds of mirror-symmetrical staggered-layer six-port optical router port layout schematic diagrams in the structure of the present invention;

Fig. 2 is a schematic diagram of a network structure in which the number of six-port optical routers is set to 18, the number of optical waveguides is set to 36, and the number of intellectual property IP cores is set to 36 in the structure of the present invention;

Fig. 3 is a schematic diagram of the network structure in which the number of six-port optical routers is set to 32, the number of optical waveguides is set to 64, and the number of intellectual property IP cores is set to 64 in the structure of the present invention;

Fig. 4 is a schematic diagram of a network structure in which the number of six-port optical routers is set to 50, the number of optical waveguides to 100, and the number of intellectual property IP cores to 100 in the structure of the present invention;

Fig. 5 is a flowchart of the communication method of the present invention;

Fig. 6 is a flow chart of the step of determining the signal transmission path in the communication method of the present invention.

detailed description

The present invention will be described in further detail below in conjunction with the accompanying drawings.

The device of the present invention includes upper and lower silicon substrates and 2N ² six-port optical routers etched on the upper and lower silicon substrates, 4N ² optical waveguides, and 4N ² knowledge points connected through the six-port optical routers and optical waveguides. Property right IP core, where N is a positive integer greater than or equal to 3.

2N ² six-port optical routers, which are composed of two kinds of staggered-layer six-port optical routers that are symmetrical to each other. The two local ports in each six-port optical router are respectively connected to two intellectual property IP cores, and the remaining four Each interconnection port is connected to other six-port optical routers through waveguides to realize the reception and forwarding of optical signals in the network.

There are 2N ² two kinds of staggered-layer six-port optical routers symmetrical to each other, including N ² optical routers arranged in the forward direction and N ² optical routers arranged in the opposite direction, and six ports are uniformly arranged on the periphery of each optical router . The above six ports of the optical router arranged in the forward direction and the lower layer are uniformly arranged in a staggered manner; Layer distribution, the port distribution of optical routers arranged in two ways is mirror symmetrical to each other.

Referring to Fig. 1, the port layout of two kinds of staggered-level six-port optical routers in the structure of the present invention is further described.

Two kinds of staggered-layer six-port optical routers symmetrical to each other include: optical router 1 arranged in forward direction and optical router 2 arranged in reverse direction. Each optical router is in the shape of a regular hexagon, and the upward direction of the center of the optical router is the positive direction when viewed from above. The six ports of the optical router are evenly distributed on the periphery of the optical router structure, and they are located in the positive direction and deflected clockwise by 30°, 90°, 150°, 210°, 270°, 330° positions. The above six ports of the optical router 1 arranged in the forward direction and the lower layer are evenly arranged in a staggered manner, and the six ports are located in the upper layer in sequence lower level Upper, lower, upper, lower. Below the six ports of the optical router 2 arranged in reverse, the upper layer is evenly arranged in a staggered manner, and the six ports are located in the lower layer, the upper layer, the lower layer, the upper layer, the lower layer, and the upper layer in sequence. The port distributions of the optical routers arranged in two ways are mirror symmetrical to each other.

2N of the 2N six ^- port optical routers are distributed on the horizontal axis of symmetry, and the rest of the optical routers are distributed in N-1 rows and N-1 columns at intervals divided by the vertical symmetry axis and the horizontal symmetry axis. within four quadrants. The 2N optical routers on the horizontal axis of symmetry are evenly distributed on both sides of the vertical axis of symmetry, and placed in each quadrant An optical router, the row farthest from the horizontal axis of symmetry is the first row, in the i-th row, where i is a positive integer satisfying 1≤i≤(N-1), starting from close to the vertical axis of symmetry, set m optical routers, the number m of optical routers satisfies m=i, the optical routers in each column are alternately arranged with forwardly arranged optical routers and reversely arranged optical routers, and the optical routers in each quadrant are respectively about the horizontal symmetry axis and The vertical symmetry axes are arranged axisymmetrically.

Below in conjunction with accompanying drawing 2 (in the structure of the present invention, the number of six-port optical routers is set to 18, the number of optical waveguides is set to 36, and the number of intellectual property IP cores is set to a network structure schematic diagram of 36), to 18 six-port optical routers The alternate arrangement is further explained.

18 six-port optical routers, which are composed of two kinds of staggered-layer six-port optical routers that are symmetrical to each other. Two local ports in each six-port optical router are respectively connected to two intellectual property IP cores, and the remaining four The interconnection port is connected with other six-port optical routers through waveguides to realize the reception and forwarding of optical signals in the network.

There are 18 two kinds of staggered-layer six-port optical routers symmetrical to each other, including 9 forward-arranged optical routers and 9 reverse-arranged optical routers, and six ports are evenly arranged on the periphery of each optical router. The above six ports of the optical router arranged in the forward direction and the lower layer are evenly distributed in a staggered manner, and the optical routers arranged in the reverse direction are evenly distributed in a staggered manner below the six ports, which correspond to the six ports of the optical router arranged in the forward direction. Layer distribution, the port distribution of optical routers arranged in two ways is mirror symmetrical to each other.

Six of the 18 six-port optical routers are distributed on the horizontal axis of symmetry 2, and the rest of the optical routers are distributed in four rows divided by the vertical symmetry axis 1 and the horizontal symmetry axis 2 at equal intervals of 2 rows and 2 columns. within the quadrant. The 6 optical routers on the horizontal symmetry axis 2 are evenly distributed on both sides of the vertical symmetry axis 1 . In each quadrant, the row farthest from the horizontal axis of symmetry 2 is the first row. In the first row, an optical router is installed from the position close to the vertical symmetry axis 1. In the second row, from the From the 1st point of the vertical symmetry axis, 2 optical routers are arranged, and a total of 3 optical routers are placed. The optical routers in each column are alternately arranged with the optical routers arranged in the forward direction and the optical routers arranged in the opposite direction. The optical routers in each quadrant are respectively arranged axisymmetrically with respect to the horizontal symmetry axis 2 and the vertical symmetry axis 1 .

Below in conjunction with accompanying drawing 3 (in the structure of the present invention, the number of six-port optical routers is set to 32, the number of optical waveguides is set to 64, and the number of intellectual property IP cores is set to a network structure schematic diagram of 64), to 32 six-port optical routers The alternate arrangement is further explained.

32 six-port optical routers, which are composed of two kinds of staggered-layer six-port optical routers that are symmetrical to each other. Two local ports in each six-port optical router are respectively connected to two intellectual property IP cores, and the remaining four The interconnection port is connected with other six-port optical routers through waveguides to realize the reception and forwarding of optical signals in the network.

There are 32 two kinds of staggered-layer six-port optical routers symmetrical to each other, including 16 forward-arranged optical routers and 16 reverse-arranged optical routers, and six ports are evenly arranged on the periphery of each optical router. The above six ports of the optical router arranged in the forward direction and the lower layer are evenly distributed in a staggered manner, and the optical routers arranged in the reverse direction are evenly distributed in a staggered manner below the six ports, which correspond to the six ports of the optical router arranged in the forward direction. Layer distribution, the port distribution of optical routers arranged in two ways is mirror symmetrical to each other.

Eight optical routers among the 32 six-port optical routers are distributed on the horizontal axis of symmetry 2, and the rest of the optical routers are distributed in four rows divided by the vertical axis of symmetry 1 and the axis of horizontal symmetry 2 at equal intervals of 3 rows and 3 columns. within the quadrant. The eight optical routers on the horizontal axis of symmetry 2 are evenly distributed on both sides of the vertical axis of symmetry 1 . In each quadrant, the row farthest from the horizontal axis of symmetry 2 is the first row, and in the first row, one optical router is set from a position close to the vertical axis of symmetry 1 . In the second row, two optical routers are arranged from the position close to the vertical symmetry axis 1. In the third row, from the position close to the vertical symmetry axis 1, 3 optical routers are arranged, and 6 optical routers are placed in each quadrant. The router is set alternately. The optical routers in each quadrant are respectively arranged axisymmetrically with respect to the horizontal symmetry axis 2 and the vertical symmetry axis 1 .

Below in conjunction with accompanying drawing 4 (in the structure of the present invention, the number of six-port optical routers is set to 50, the number of optical waveguides is set to 100, and the number of intellectual property IP cores is set to a network structure schematic diagram of 100), to 50 six-port optical routers The alternate arrangement is further explained.

50 six-port optical routers are composed of two kinds of mirror-symmetrical staggered-layer six-port optical routers arranged alternately. Two local ports in each six-port optical router are respectively connected to two intellectual property IP cores, and the remaining four The interconnection port is connected with other six-port optical routers through waveguides to realize the reception and forwarding of optical signals in the network.

There are 50 two kinds of staggered-layer six-port optical routers symmetrical to each other, including 25 forward-arranged optical routers and 25 reverse-arranged optical routers, and six ports are evenly arranged on the periphery of each optical router. The above six ports of the optical router arranged in the forward direction and the lower layer are evenly distributed in a staggered manner, and the optical routers arranged in the reverse direction are evenly distributed in a staggered manner below the six ports, which correspond to the six ports of the optical router arranged in the forward direction. Layer distribution, the port distribution of optical routers arranged in two ways is mirror symmetrical to each other.

10 of the 50 six-port optical routers are distributed on the horizontal axis of symmetry 2, and the rest of the optical routers are distributed in four rows divided by the vertical symmetry axis 1 and the horizontal symmetry axis 2 at equal intervals of 4 rows and 4 columns. within the quadrant. The 10 optical routers on the horizontal symmetry axis 2 are evenly distributed on both sides of the vertical symmetry axis 1 . In each quadrant, the row farthest from the horizontal axis of symmetry 2 is the first row, and in the first row, one optical router is set from a position close to the vertical axis of symmetry 1 . In the second row, two optical routers are arranged from the position close to the vertical symmetry axis 1. In the third row, from the position close to the vertical symmetry axis 1, three optical routers are arranged. In the 4th row, 4 optical routers are arranged from the position close to the vertical symmetry axis 1, and 10 optical routers are placed in each quadrant. The router is set alternately. The optical routers in each quadrant are respectively arranged axisymmetrically with respect to the horizontal symmetry axis 2 and the vertical symmetry axis 1 .

4N ² optical waveguides are etched alternately on the upper and lower silicon substrates, and each optical waveguide is connected to two six-port optical routers to realize the transmission of optical signals in the network.

4N ² optical waveguides are etched alternately on the upper and lower silicon substrates:

The 2N ² -2 optical waveguides distributed along the vertical axis of symmetry include 2N ² -2N optical waveguides and 2N-2 optical waveguides. Each of the 2N ² -2N optical waveguides is respectively connected to its adjacent optical router, and each optical waveguide is etched on the upper silicon substrate. Each of the 2N-2 optical waveguides is connected to the optical router at the head and tail of each column respectively, and the 2N-2 optical waveguides are etched alternately on the upper and lower silicon substrates from close to the vertical axis of symmetry outward .

The 4(N-1)+2(N-1) ² optical waveguides distributed along the horizontal axis of symmetry include (2N-3)+2(N-1) ² optical waveguides and 2N-1 optical waveguides , wherein (2N-3)+2(N-1) ² optical waveguides include 2N-3 optical waveguides and 2(N-1) ² optical waveguides. Each of the (2N-3)+2(N-1) ² optical waveguides is connected to its adjacent optical routers except the first row in each quadrant, and the 2N-3 optical waveguides are all It is connected to the adjacent optical router and the connecting line intersects the vertical symmetry axis, and each optical waveguide in the 2N-3 optical waveguides is etched on the upper silicon substrate. 2(N-1) ² optical waveguides are etched alternately on the lower and upper silicon substrates from close to the vertical axis of symmetry outward. Each of the 2N-1 optical waveguides is respectively connected to the optical routers at the head and tail of each row, and each optical waveguide is etched on the lower silicon substrate.

The two optical routers located at the beginning and the end of the horizontal axis of symmetry are respectively connected to the optical routers in the first row in the adjacent quadrant through two optical waveguides. The four optical waveguides form a peripheral loop, and each optical waveguide in the peripheral loop are etched on the upper silicon substrate.

Below in conjunction with accompanying drawing 2 (in the structure of the present invention, the number of six-port optical routers is set to 18, the number of optical waveguides is set to 36, and the number of IP cores of intellectual property rights is set to a network structure schematic diagram of 36), 36 optical waveguides are arranged at the upper and lower sides The staggered etching method on the layered silicon substrate is further described.

The 16 optical waveguides distributed along the direction of the vertical symmetry axis 1 include two types: 12 optical waveguides and 4 optical waveguides. Each of the 12 optical waveguides is respectively connected to its adjacent optical router, and each optical waveguide is etched on the upper silicon substrate. Each of the four optical waveguides is respectively connected to the optical routers at the head and tail of each row, and the four optical waveguides are etched alternately on the upper and lower silicon substrates in sequence from near the vertical symmetry axis 1 outward.

The 16 optical waveguides distributed along the direction of the horizontal symmetry axis 2 include 11 optical waveguides and 5 optical waveguides, and the 11 optical waveguides include 3 optical waveguides and 8 optical waveguides. Each of the 11 optical waveguides is connected to its adjacent optical routers except the first row in each quadrant, and the three optical waveguides are connected to its adjacent optical routers, and the connection lines are symmetrical to the vertical Intersecting axis 1, these optical waveguides are etched into the upper silicon substrate. The eight optical waveguides are etched alternately on the lower and upper silicon substrates in sequence from near the vertical symmetry axis 1 to the outside. Each of the five optical waveguides is respectively connected to the optical routers at the head and tail of each row, and these optical waveguides are all etched on the lower silicon substrate.

The two optical routers located at the beginning and end of the horizontal axis of symmetry 2 are respectively connected to the optical routers in the first row in the adjacent quadrant through two optical waveguides. The four optical waveguides form a peripheral loop, and each optical fiber in the peripheral loop The waveguides are etched on the upper silicon substrate.

Below in conjunction with accompanying drawing 3 (in the structure of the present invention, the number of six-port optical routers is set to 32, the number of optical waveguides is set to 64, and the number of IP cores of intellectual property rights is set to a schematic diagram of the network structure of 64), 64 optical waveguides are arranged at the upper and lower sides. The staggered etching method on the layered silicon substrate is further described.

The 30 optical waveguides distributed along the direction of the vertical symmetry axis 1 include two types: 24 optical waveguides and 6 optical waveguides. Each of the 24 optical waveguides is connected to its adjacent optical router, and each optical waveguide is etched on the upper silicon substrate. Each of the 6 optical waveguides is respectively connected to the optical routers at the head and tail of each row, and the 6 optical waveguides are etched alternately on the upper and lower silicon substrates in sequence from the vertical symmetry axis 1 to the outside.

The 30 optical waveguides distributed along the direction of the horizontal symmetry axis 2 include 23 optical waveguides and 7 optical waveguides, and the 23 optical waveguides include 5 optical waveguides and 18 optical waveguides. Each of the 23 optical waveguides is connected to its adjacent optical routers except the first row in each quadrant, and the five optical waveguides are all connected to its adjacent optical routers and the connection lines are symmetrical to the vertical Intersecting axis 1, these optical waveguides are etched into the upper silicon substrate. The 18 optical waveguides are etched alternately on the lower and upper silicon substrates in sequence from near the vertical symmetry axis 1 to the outside. Each of the seven optical waveguides is respectively connected to the optical routers at the head and tail of each row, and these optical waveguides are all etched on the lower silicon substrate.

The two optical routers located at the beginning and end of the horizontal axis of symmetry 2 are respectively connected to the optical routers in the first row in the adjacent quadrant through two optical waveguides. The four optical waveguides form a peripheral loop, and each optical fiber in the peripheral loop The waveguides are etched on the upper silicon substrate.

Below in conjunction with accompanying drawing 4 (in the structure of the present invention, the number of six-port optical routers is set to 50, the number of optical waveguides is set to 100, and the number of IP cores of intellectual property rights is set to a network structure schematic diagram of 100), to 100 optical waveguides in the upper and lower two The staggered etching method on the layered silicon substrate is further described.

The 48 optical waveguides distributed along the direction of the vertical symmetry axis 1 include two types: 40 optical waveguides and 8 optical waveguides. Each of the 48 optical waveguides is connected to its adjacent optical router, and each optical waveguide is etched on the upper silicon substrate. Each of the eight optical waveguides is respectively connected to the optical routers at the head and tail of each column, and the eight optical waveguides are etched alternately on the upper and lower silicon substrates in sequence from the vertical symmetry axis 1 to the outside.

The 48 optical waveguides distributed along the direction of the horizontal symmetry axis 2 include 39 optical waveguides and 9 optical waveguides, and the 39 optical waveguides include 7 optical waveguides and 32 optical waveguides. Each of the 39 optical waveguides is connected to its adjacent optical routers except the first row in each quadrant, and the 7 optical waveguides are all connected to its adjacent optical routers and the connection lines are symmetrical to the vertical Intersecting axis 1, these optical waveguides are etched into the upper silicon substrate. The 32 optical waveguides are etched alternately on the lower and upper silicon substrates in sequence from close to the vertical symmetry axis 1 to the outside. Each of the nine optical waveguides is respectively connected to the optical routers at the head and tail of each row, and these optical waveguides are all etched on the lower silicon substrate.

The two optical routers located at the beginning and end of the horizontal axis of symmetry 2 are respectively connected to the optical routers in the first row in the adjacent quadrant through two optical waveguides. The four optical waveguides form a peripheral loop, and each optical fiber in the peripheral loop The waveguides are etched on the upper silicon substrate.

4N ² intellectual property IP cores to realize the processing of optical signals in the network.

Figure 2 sets the number of intellectual property IP cores in the structure of the present invention to 36 to realize the processing of optical signals in the network. Figure 3 sets the number of intellectual property IP cores in the structure of the present invention to 64 to realize the processing of optical signals in the network. Figure 4 sets the number of intellectual property IP cores in the structure of the present invention to 100 to realize the processing of optical signals in the network.

Below in conjunction with accompanying drawing 5, the communication method of the present invention is further described, utilize the expandable optical on-chip network structure of double-layer layout to transmit optical signal, complete the communication between intellectual property IP core, concrete steps comprise as follows:

(1) Establish a coordinate system in the scalable optical-on-chip network:

(1a) Taking the horizontal symmetry axis in the scalable optical-on-chip network as the positive direction to the right, and the vertical symmetry axis as the positive direction, establish a plane Cartesian coordinate system.

(1b) Taking the center interval of adjacent optical routers in the scalable optical network on chip as the unit length, determine the coordinate value of each optical router in turn, and the coordinate value of each intellectual property IP core is the same as the coordinate value of the optical router connected to it.

(2) Determine the transmission path of the signal:

By calculating the product value and coordinate weight of the horizontal and vertical coordinates of the source intellectual property IP core and the target intellectual property IP core respectively, the relative position of the source intellectual property IP core and the target intellectual property IP core is judged, and the transmission path of the signal is determined.

The step of determining the signal transmission path in the communication method of the present invention will be further described below with reference to FIG. 6 .

(2a) When the abscissa of the source intellectual property IP core is equal to the abscissa of the target intellectual property IP core, and the ordinate of the source intellectual property IP core is equal to the ordinate of the target intellectual property IP core, the source intellectual property IP core and The target intellectual property IP core is connected to the same optical router, and the optical signal transmission path is inside the optical router.

(2c) When the abscissa of the source intellectual property IP core is not equal to the abscissa of the target intellectual property IP core, or the ordinate of the source intellectual property IP core is not equal to the ordinate of the target intellectual property IP core, the source intellectual property IP The optical router connected to the core and the optical router connected to the target intellectual property IP core are located in the same row or column, and the optical signal is transmitted through the optical router on the row or column.

(2d) When the abscissa of the source intellectual property IP core is not equal to the abscissa of the target intellectual property IP core, and the ordinate of the source intellectual property IP core is not equal to the ordinate of the target intellectual property IP core, calculate the weight G ＝min[|x _s -x _d |-1,|x _s +x _d |+1]+min[|y _s -y _d |-1,|y _s +y _d |+1], where x _s is the abscissa of the source intellectual property IP core, y _s is the ordinate of the source intellectual property IP core, x _d is the abscissa of the destination intellectual property IP core, and y _d is the ordinate of the destination intellectual property IP core, so as to determine the optical Signal transmission path:

If the abscissa reference value x _s × x _d and the ordinate reference value y _s × y _d are positive numbers at the same time, or one of the abscissa reference value and the ordinate reference value is a positive number and the other is 0, the source intellectual property rights The IP core and the target intellectual property IP core are located in the same quadrant. Otherwise, the source intellectual property IP core and the destination intellectual property IP core are located in different quadrants.

When the source intellectual property IP core and the destination intellectual property IP core are located in the same quadrant, if the weight G satisfies G≤N-1, the optical signal is transmitted through X-Y dimensional order routing. If the weight G satisfies G>N-1, the optical signal is first transmitted to the nearest peripheral loop endpoint through an X-Y dimensional order routing, then transmitted to its other endpoint through the peripheral loop, and then transmitted to Purpose intellectual property IP core.

When the source intellectual property IP core and the destination intellectual property IP core are located in different quadrants, if the weight G satisfies G≤N, the optical signal is transmitted through X-Y dimensional order routing. If the weight G satisfies G>N, the optical signal is first transmitted to the nearest peripheral loop endpoint through an X-Y dimensional order routing, then transmitted to its other endpoint through the peripheral loop, and then transmitted to the destination knowledge through an X-Y dimensional sequence routing. Property rights IP core.

(3) Configure the optical router port on the transmission path:

(3a) The source intellectual property IP core sends control signals.

(3b) The control signal is transmitted to the target intellectual property IP core along the determined signal transmission path.

(3c) The control signal configures the optical router port on the transmission path.

(3d) The destination intellectual property IP core generates and sends a response signal after receiving the control signal, and the response signal returns to the source intellectual property IP core along the transmission path.

(4) Send optical signal:

The source intellectual property IP core generates and sends an optical signal after receiving the response signal, and the optical signal is transmitted to the destination intellectual property IP core along the transmission path.

(5) Receive optical signal:

(5a) The target intellectual property IP core receives the optical signal.

(5b) The destination intellectual property IP core generates and sends an epilogue signal, and the epilogue signal is transmitted to the source intellectual property IP core, and the configured optical router port is released along the transmission path.

Claims (4)

1. A scalable optical on-chip network structure based on a double-layer layout, including upper and lower silicon substrates and 2N ² six-port optical routers etched on the upper and lower silicon substrates, 4N ² optical waveguides, through 4N ² intellectual property IP cores connected by a six-port optical router and an optical waveguide, where N is a positive integer greater than or equal to 3, characterized in that: The 2N ² six-port optical routers are composed of two alternately arranged staggered-layer six-port optical routers that are mirror-symmetrical to each other, and the two local ports in each six-port optical router are respectively connected to two intellectual property IP cores. , and the remaining four interconnection ports are connected to other six-port optical routers through waveguides to realize the reception and forwarding of optical signals in the network; The 4N ² optical waveguides are alternately etched on the upper and lower silicon substrates, and each optical waveguide is connected to two six-port optical routers to realize the transmission of optical signals in the network; The 4N ² intellectual property IP cores realize the processing of optical signals in the network. 2. The scalable optical on-chip network structure based on double-layer layout according to claim 1, wherein the two kinds of mirror-symmetrical staggered six-port optical routers are alternately arranged as follows: There are 2N ² two kinds of mirror-symmetrical staggered-layer six-port optical routers, including N ² forwardly arranged optical routers and N ² reversely arranged optical routers; Six ports; above the six ports of the optical router arranged in the forward direction, the lower layer is uniformly arranged in a staggered manner; The ports correspond to the staggered layer distribution in turn, and the port distribution of the optical routers in the two arrangements are mirror symmetrical to each other; The 2N optical routers in the 2N ² six-port optical routers are distributed on the horizontal axis of symmetry, and the rest of the optical routers are respectively distributed in N-1 rows and N-1 columns at equal intervals by the vertical symmetry axis and the horizontal symmetry axis. In the four quadrants divided by the axis; 2N optical routers on the horizontal axis of symmetry are evenly distributed on both sides of the vertical axis of symmetry; each quadrant is placed An optical router, the row farthest from the horizontal axis of symmetry is the first row, in the i-th row, where i is a positive integer satisfying 1≤i≤(N-1), starting from close to the vertical axis of symmetry, set m optical routers, the number m of optical routers satisfies m=i, the optical routers in each column are alternately arranged with forwardly arranged optical routers and reversely arranged optical routers, and the optical routers in each quadrant are respectively about the horizontal symmetry axis and The vertical symmetry axes are arranged axisymmetrically. 3. The scalable optical-on-chip network structure based on a double-layer layout according to claim 1, wherein said 4N ² optical waveguides are etched alternately on the upper and lower silicon substrates: The 2N ² -2 optical waveguides distributed along the vertical axis of symmetry include 2N ² -2N optical waveguides and 2N-2 optical waveguides; each optical waveguide in the 2N ² -2N optical waveguides is associated with the Adjacent optical routers are connected, and each optical waveguide is etched on the upper silicon substrate; each of the 2N-2 optical waveguides is connected to the optical router at the head and tail of each row, and the 2N-2 optical waveguides The waveguide is alternately etched on the upper and lower silicon substrates from close to the vertical symmetry axis to the outside; The 4(N-1)+2(N-1) ² optical waveguides distributed along the horizontal axis of symmetry include (2N-3)+2(N-1) ² optical waveguides and 2N-1 optical waveguides , wherein (2N-3)+2(N-1) ² optical waveguides include 2N-3 optical waveguides and 2(N-1) ² optical waveguides; (2N-3)+2(N -1) Each of the ^two optical waveguides is connected to its adjacent optical routers except the first row in each quadrant, and the 2N-3 optical waveguides are all connected to its adjacent optical routers and connected The line intersects the vertical symmetry axis, and each of the 2N-3 optical waveguides is etched on the upper silicon substrate; 2(N-1) ² optical waveguides are sequentially outward from the vertical symmetry axis Alternate etching on the lower and upper silicon substrates; each of the 2N-1 optical waveguides is connected to the optical router at the head and tail of each row, and each optical waveguide is etched on the lower silicon substrate; The two optical routers located at the beginning and the end of the horizontal axis of symmetry are respectively connected to the optical routers in the first row in the adjacent quadrant through two optical waveguides. The four optical waveguides form a peripheral loop, and each optical waveguide in the peripheral loop are etched on the upper silicon substrate. 4. A scalable optical-on-chip network communication method based on a double-layer layout, using the scalable optical-on-chip network structure of a double-layer layout to transmit optical signals, and completing communication between intellectual property IP cores. The specific steps include the following: (1) Establish a coordinate system in the scalable optical-on-chip network: (1a) Taking the horizontal symmetry axis in the scalable optical-on-chip network as the positive direction to the right and the vertical symmetry axis as the positive direction, establish a plane Cartesian coordinate system; (1b) Taking the center interval of adjacent optical routers in the scalable optical on-chip network as the unit length, determine the coordinate value of each optical router in turn, and the coordinate value of each intellectual property IP core is the same as the coordinate value of the optical router connected to it; (2) Determine the transmission path of the signal: By calculating the product value and coordinate weight of the horizontal and vertical coordinates of the source intellectual property IP core and the target intellectual property IP core respectively, determine the relative position of the source intellectual property IP core and the target intellectual property IP core, and determine the transmission path of the signal; (3) Configure the optical router port on the transmission path: (3a) The source intellectual property IP core sends control signals; (3b) The control signal is transmitted to the target intellectual property IP core along the determined signal transmission path; (3c) control signal configuration optical router ports on the transmission path; (3d) The target intellectual property IP core generates and sends a response signal after receiving the control signal, and the response signal returns to the source intellectual property IP core along the transmission path; (4) Send optical signal: The source intellectual property IP core generates and sends an optical signal after receiving the response signal, and the optical signal is transmitted along the transmission path to the destination intellectual property IP core; (5) Receive optical signal: (5a) The target intellectual property IP core receives the optical signal; (5b) The destination intellectual property IP core generates and sends an epilogue signal, and the epilogue signal is transmitted to the source intellectual property IP core, and the configured optical router port is released along the transmission path.