CN106935168A - Shift register and display device - Google Patents

Abstract

The invention discloses a shift register and a display device. The shift register comprises a pre-charging unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charging unit receives a first input signal and a second input signal, and outputs a pre-charging signal from a first node. The pull-up unit receives the precharge signal, the first clock signal and the second clock signal, and outputs a scan signal from the second node. The first pull-down unit receives the precharge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential. The second pull-down unit receives the precharge signal, the first pull-down control signal and the second pull-down control signal, and controls whether to pull down the scan signal to the reference potential. Therefore, the shift register has high reliability and high stability, and the display device with the shift register can improve the display quality of the display device.

Description

Shift register and display device

technical field

The invention relates to a shift register, and in particular to a shift register capable of improving reliability and a display device with the shift register.

Background technique

With the continuous advancement of thin film transistor (TFT) liquid crystal display technology, the technology of integrating the driving circuit on the display panel, such as system on glass (SOG), has gradually been widely used in today's display on the device product. On the other hand, for high-resolution display devices, the driving time of each pixel is limited. If the driving circuit cannot complete the driving of the corresponding pixel within the driving time, it may cause image display error data or other factors due to poor driving stability. problems caused by good. Therefore, how to design a driving circuit suitable for a high-resolution display device has become one of the goals of the industry.

Contents of the invention

The purpose of the present invention is to provide a shift register and a display device, which have stable performance and are not easily disturbed by other noises, thereby improving the display quality of images.

According to the above object of the present invention, a shift register is proposed. The shift register includes a precharge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charging unit receives the first input signal and the second input signal, and outputs a pre-charging signal from the first node according to the first input signal and the second input signal. The pre-charging unit includes a first transistor and a second transistor. The gate and the first source-drain of the first transistor receive the first input signal, and the second source-drain of the first transistor is coupled to the first node and outputs a pre-charge signal. The gate and the first source-drain of the second transistor receive the second input signal, and the second source-drain of the second transistor is coupled to the second source-drain of the first transistor. The pull-up unit is coupled to the pre-charging unit, which outputs a scan signal from the second node according to the pre-charging signal, the first clock signal and the second clock signal. The pull-up unit includes a third transistor, a capacitor and a fourth transistor. The gate of the third transistor receives the pre-charge signal, the first source-drain of the third transistor receives the first clock signal, and the second source-drain of the third transistor is coupled to the second node and outputs a scanning signal. The first end of the capacitor is coupled to the gate of the third transistor, and the second end of the capacitor is coupled to the second source-drain of the third transistor. The gate of the fourth transistor receives the second clock signal, the first source-drain of the fourth transistor is coupled to the reference potential, and the second source-drain of the fourth transistor is coupled to the gate of the third transistor. The first pull-down unit is coupled to the pre-charge unit and the pull-up unit, which receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal, Control signal to control whether to pull down the scan signal to the reference potential. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, which receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal to control whether to pull down the scan signal to the reference potential.

According to an embodiment of the present invention, the above-mentioned first input signal is a start signal, and the above-mentioned second input signal is a scan signal output by a next-stage shift register corresponding to the shift register.

According to yet another embodiment of the present invention, the above-mentioned first input signal is the scanning signal output by the upper-stage shift register corresponding to the shift register, and the above-mentioned second input signal is the output of the next-stage shift register corresponding to the shift register The output scan signal.

According to yet another embodiment of the present invention, the above-mentioned first input signal is a scan signal output by the upper-stage shift register corresponding to the shift register, and the above-mentioned second input signal is an end signal.

According to yet another embodiment of the present invention, the first clock signal is switched from a high level to a low level at a first time point, and the second clock signal is switched from a low level to a low level at a second time point after the first time point. The bit is switched to a high level, and the second time point is two data writing times different from the first time point.

According to yet another embodiment of the present invention, the first pull-down unit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor. A first pull-down control signal is input to the gate and the first source-drain of the fifth transistor. The gate of the sixth transistor inputs the second pull-down control signal, the first source-drain of the sixth transistor is coupled to the reference potential, and the second source-drain of the sixth transistor is coupled to the second source of the fifth transistor Drain pole. The gate of the seventh transistor is coupled to the first node, the first source-drain of the seventh transistor is coupled to the reference potential, and the second source-drain of the seventh transistor is coupled to the second source-drain of the fifth transistor pole. The gate of the eighth transistor is coupled to the second source-drain of the seventh transistor, the first source-drain of the eighth transistor is coupled to the reference potential, and the second source-drain of the eighth transistor is coupled to the first node. The gate of the ninth transistor is coupled to the second source-drain of the seventh transistor, the first source-drain of the ninth transistor is coupled to the reference potential, and the second source-drain of the ninth transistor is coupled to the second node.

According to yet another embodiment of the present invention, the above-mentioned second pull-down unit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. The gate and the first source-drain of the tenth transistor input the second pull-down control signal. The gate of the eleventh transistor inputs the first pull-down control signal, the first source-drain of the eleventh transistor is coupled to the reference potential, and the second source-drain of the eleventh transistor is coupled to the tenth transistor The second source-sink. The gate of the twelfth transistor is coupled to the first node, the first source-drain of the twelfth transistor is coupled to the reference potential, and the second source-drain of the twelfth transistor is coupled to the first node of the tenth transistor. Two sources and drains. The gate of the thirteenth transistor is coupled to the second source-drain of the twelfth transistor, the first source-drain of the thirteenth transistor is coupled to the reference potential, and the second source-drain of the thirteenth transistor coupled to the first node. The gate of the fourteenth transistor is coupled to the second source-drain of the twelfth transistor, the first source-drain of the fourteenth transistor is coupled to the reference potential, and the second source-drain of the fourteenth transistor coupled to the second node.

According to the above object of the present invention, another display device is proposed. The display device includes a display panel, a plurality of clock signal lines and a shift register device. These clock signal lines are used to provide multiple clock signals. The shift register device is used to drive the display panel, and it includes a plurality of shift registers. Each shift register is coupled to its upper stage shift register or its lower stage shift register, and each shift register includes a precharge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charging unit receives the first input signal and the second input signal, and outputs a pre-charging signal from the first node according to the first input signal and the second input signal. The pre-charging unit includes a first transistor and a second transistor. The gate and the first source-drain of the first transistor receive the first input signal, and the second source-drain of the first transistor is coupled to the first node and outputs a pre-charge signal. The gate and the first source-drain of the second transistor receive the second input signal, and the second source-drain of the second transistor is coupled to the second source-drain of the first transistor. The pull-up unit is coupled to the pre-charging unit, which outputs a scan signal from the second node according to the pre-charging signal, the first clock signal and the second clock signal. The pull-up unit includes a third transistor, a capacitor and a fourth transistor. The gate of the third transistor receives the precharge signal, the first source-drain of the third transistor is coupled to the first clock signal line for providing the first clock signal among the clock signal lines, and the third transistor’s The second source-drain is coupled to the second node and outputs a scan signal. The first end of the capacitor is coupled to the gate of the third transistor, and the second end of the capacitor is coupled to the second source-drain of the third transistor. The gate of the fourth transistor is coupled to the second clock signal line for providing the second clock signal among the clock signal lines, the first source-drain of the fourth transistor is coupled to the reference potential, and the fourth transistor The second source-drain is coupled to the gate of the third transistor. The first pull-down unit is coupled to the pre-charge unit and the pull-up unit, which receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal, Control signal to control whether to pull down the scan signal to the reference potential. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, which receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal to control whether to pull down the scan signal to the reference potential.

According to an embodiment of the present invention, the above-mentioned shift registers are N-stage shift registers, wherein the first input signal and the second input signal in the first-stage shift register are the start signal and the second-stage shift register respectively. The scan signal output by the register, the first input signal and the second input signal in the Nth stage shift register are respectively the scan signal and the end signal output by the (N-1) stage shift register, and the i stage shift register The first input signal and the second input signal in the bit register are respectively the scan signal output by the (i-1) shift register and the scan signal output by the (i+1) shift register, where i is A positive integer greater than 1 and less than N.

According to yet another embodiment of the present invention, the first clock signal is switched from a high level to a low level at a first time point, and the second clock signal is switched from a low level to a low level at a second time point after the first time point. The bit is switched to a high level, and the second time point is two data writing times different from the first time point.

According to the above object of the present invention, another shift register is proposed. The shift register includes a precharge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charging unit receives the first input signal and the second input signal, and outputs a pre-charging signal from the first node according to the first input signal and the second input signal. The pull-up unit is coupled to the pre-charging unit, which outputs a scan signal from the second node according to the pre-charging signal, the first clock signal and the second clock signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, which receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal to control whether to pull down the scan signal to the reference potential. The first input signal is a start signal, and the second input signal is a scan signal output by a next-stage shift register corresponding to the shift register.

According to the above object of the present invention, another shift register is proposed. The shift register includes a precharge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charging unit receives the first input signal and the second input signal, and outputs a pre-charging signal from the first node according to the first input signal and the second input signal. The pull-up unit is coupled to the pre-charging unit, which outputs a scan signal from the second node according to the pre-charging signal, the first clock signal and the second clock signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, which receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal to control whether to pull down the scan signal to the reference potential. The first input signal is a scan signal output by a shift register corresponding to an upper stage of the shift register, and the second input signal is a scan signal output by a shift register corresponding to a lower stage of the shift register.

According to the above object of the present invention, another shift register is proposed. The shift register includes a precharge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charging unit receives the first input signal and the second input signal, and outputs a pre-charging signal from the first node according to the first input signal and the second input signal. The pull-up unit is coupled to the pre-charging unit, which outputs a scan signal from the second node according to the pre-charging signal, the first clock signal and the second clock signal. The second pull-down unit is coupled to the pre-charge unit and the pull-up unit, which receives the pre-charge signal, the first pull-down control signal and the second pull-down control signal, and according to the pre-charge signal, the first pull-down control signal and the second pull-down control signal to control whether to pull down the scan signal to the reference potential. The first input signal is the scan signal output by the upper stage shift register corresponding to the shift register, and the second input signal is the end signal.

The advantage of the present invention is that the shift register has stable driving performance and is not easily disturbed by other noises, and the display device using the shift register can improve its display quality, avoiding water ripples or horizontal lines in the displayed image. It has high reliability and high stability due to problems such as grain.

Description of drawings

For a more complete understanding of the embodiments and advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of a display device according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of a gate driving circuit according to an embodiment of the present invention;

FIG. 3 shows an equivalent circuit diagram of a shift register according to an embodiment of the present invention; and

FIG. 4 is a timing diagram of the gate driving circuit of FIG. 2 .

detailed description

Embodiments of the invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be implemented in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustration only and are not intended to limit the scope of the present invention.

Please refer to FIG. 1 , which shows a schematic diagram of a display device 100 according to an embodiment of the present invention. The display device 100 includes a display panel 110 , a source driver 120 and gate drivers 130A, 130B. The display panel 110 has a plurality of pixels arranged in an array, which are commonly used to display images. The display panel 110 may be, for example, a twisted nematic (TN) type, an in-plane switching (IPS) type, a fringe-field switching (FFS) type, or a vertical alignment (VA) type. Various types of liquid crystal display panels, or organic light-emitting diode (OLED) panels, etc., but not limited thereto. The source driver 120 is electrically connected to the display panel 110 for converting image data into source driving signals and transmitting the source driving signals to the display panel 110 . As shown in FIG. 1 , the gate drivers 130A and 130B are respectively disposed on the left and right sides of the display panel 110 , and are jointly used to transmit gate driving signals to the display panel 110 . In other embodiments, the positions of the gate drivers 130A and 130B can be correspondingly adjusted according to different design requirements. The display panel 110 is driven by the source driving signal and the gate driving signal to display images.

Please refer to FIG. 2 , which is a schematic diagram of a gate driving circuit 200 according to an embodiment of the present invention. The gate driving circuit 200 is applicable to the display device 100 of FIG. 1 or other similar display devices. The following will be described by taking the display device 100 used in FIG. 1 as an example. The gate driving circuit 200 is divided into a first gate driving circuit 200A and a second gate driving circuit 200B, wherein the first gate driving circuit 200A is a part of the gate driver 130A, and the second gate driving circuit 200B is a gate part of the driver 130B.

The first gate drive circuit 200A includes clock signal lines L1-L8, start signal line S, end signal line R, and N-stage first shift registers 210A(1)-210A(N), and the second gate drive circuit 200B includes clock signal lines L1'~L8', start signal line S', end signal line R' and N-stage second shift registers 210B(1)~210B(N), where N is a positive number greater than or equal to 8 integer. In some embodiments, N is a multiple of 8. The clock signal lines L1-L8 are used to respectively provide the clock signals C1-C8 to the corresponding first shift registers 210A(1)-210A(N), and the clock signal lines L1'-L8' are used to respectively provide the clock signal C1' ~C8' to the corresponding second shift registers 210B(1)~210B(N), wherein the period of each clock signal C1~C8, C1'~C8' is the same. In this embodiment, the period of the clock signals C1-C8, C1'-C8' is 16 data write-in times H (each data write-in time H occupies 1/16 clock signal period). The clock signals C1 - C8 are shifted backward by two data writing times H in sequence. In addition, the start signal line S provides a start signal STV to the first shift register 210A (1) of the first stage, and the start signal line S' provides a start signal STV' to the second shift register 210B (1) of the first stage. ), the end signal line R provides the end signal RSTV to the Nth stage first shift register 210A(N), and the end signal line R' provides the end signal RSTV' to the Nth stage second shift register 210B(N).

The first shift registers 210A( 1 )˜ 210A(N) respectively generate scan signals OUT( 1 )˜OUT(N), which are used to drive odd pixel rows (rows) of the display panel 110 at a specific data writing time. The second shift registers 210B(1)˜210B(N) respectively generate scanning signals OUT'(1)˜OUT'(N), which are used to drive the even pixel rows of the display panel 110 at a specific data writing time. The scanning signals OUT(1)~OUT(N) of the same level and the scanning signals OUT'(1)~OUT'(N) differ by a data writing time H. For example, the first-level scan signal OUT(1) lags behind the first-level scan signal OUT'(1) by a data writing time H.

In the gate drive circuit 200 of FIG. 2 , each of the first shift registers 210A(1)-210A(N) and each of the second shift registers 210B(1)-210B(N) are shifted with their upper stage The bit register or its next-stage shift register are coupled to each other, and use the scan signal output by its upper-stage shift register or its next-stage shift register to control the output scan signal level, so the gate drive circuit The 200 can reduce the use of additional control signals, and can reduce the crossover of signal lines in its circuit layout.

FIG. 3 is an equivalent circuit diagram of a shift register 300 according to an embodiment of the present invention. The shift register 300 may be any one of the first shift registers 210A(1)˜210A(N) and the second shift registers 210B(1)˜210B(N) of FIG. 2 . The shift register 300 includes a precharge unit 310 , a pull-up unit 320 , a first pull-down unit 330 and a second pull-down unit 340 .

The pre-charging unit 310 receives input signals IN1, IN2, and outputs a pre-charging signal from node X according to the input signals IN1, IN2. The pre-charging unit 310 includes transistors M1 and M2, wherein the gate and the first source-drain of the transistor M1 receive the input signal IN1, the second source-drain of the transistor M1 is coupled to node X to output a pre-charge signal, and the transistor M2 The gate and the first source-drain of the transistor M2 receive the input signal IN2, and the second source-drain of the transistor M2 is coupled to the second source-drain of the transistor M1.

If the shift register 300 is the first shift register 210A(1) of the first stage or the second shift register 210B(1) of the first stage in FIG. 2, the input signal IN1 is the start signal STV or STV', and The input signal IN2 is the scanning signal OUT(2) output by the first shift register 210A(2) of the second stage or the scanning signal OUT′(2) output by the second shift register 210B(2) of the second stage.

If the shift register 300 is the first shift register 210A(2)-210A(N-1) of the second to (N-1) stages in FIG. 2 and the second shift register of the second to (N-1) stages Any one of 210B(2)～210B(N-1), the input signal IN1 and the input signal IN2 are the scanning signal output by the first shift register of the upper stage and the output of the first shift register of the next stage respectively. The scanning signal, or the scanning signal output by the second shift register of the upper stage and the scanning signal output by the second shift register of the lower stage respectively. Taking the i-th stage first shift register 210A(i) as an example (i is a positive integer greater than 1 and less than N), the input signal IN1 is output by the (i-1)-th stage shift register 210A(i-1) The scan signal OUT(i−1), and the input signal IN2 is the scan signal OUT(i+1) output by the (i+1)th shift register 210A(i+1).

If the shift register 300 is the Nth stage first shift register 210A (N) or the Nth stage second shift register 210B (N) in FIG. 2 , then the input signal IN1 is the first (N-1) stage shift register. The scan signal OUT(N-1) output by the shift register 210A(N-1) or the scan signal OUT'(N-1) output by the second shift register 210B(N-1) of the (N-1)th stage, And the input signal IN2 is the end signal RSTV or RSTV'.

The pull-up unit 320 is coupled to the pre-charging unit 310, which receives the pre-charging signal and the clock signals CN1, CN2, and outputs the scan signal OUT from the node Y according to the pre-charging signal and the clock signals CN1, CN2. The pull-up unit 320 includes transistors M3, M4 and a capacitor Cx. The gate of the transistor M3 receives the pre-charge signal, the first source-drain of the transistor M3 receives the clock signal CN1, and the second source-drain of the transistor M3 is coupled to the node Y and outputs the scanning signal OUT. A first end of the capacitor Cx is coupled to the gate of the transistor M3, and a second end of the capacitor Cx is coupled to the second source and drain of the transistor M3. The gate of the transistor M4 receives the clock signal CN2, the first source-drain of the transistor M4 is coupled to the reference potential VGL, and the second source-drain of the transistor M4 is coupled to the gate of the transistor M3. In this embodiment, transistors M3 and M4 have the same threshold voltage Vt. In other embodiments, transistors M3 and M4 may have different threshold voltages.

The clock signals CN1 and CN2 are different two of the clock signals C1 to C8 or different two of the clock signals C1' to C8', and the difference between the clock signals CN1 and CN2 is 10 data writing time H. In other words, the time point when the clock signal CN1 transitions from the high level to the low level differs from the time point when the clock signal CN2 transitions from the low level to the high level by two data writing time H. For example, when the clock signal CN1 is the clock signal C1, the clock signal CN2 can be the clock signal C6. Referring to FIG. 4 , the clock signal C1 transitions from a low level to a high level at time t2, and the clock signal C6 transitions from a low level to a high level at time t12, where the difference between time t12 and time t2 is 10 Data write time H. In other words, the clock signal C1 has switched from a high level to a low level at the time point t10, and the clock signal C6 has switched from a low level to a high level at the time point t12, wherein the time point t12 is two times different from the time point t10. data write time H.

The first pull-down unit 330 is coupled to the pre-charge unit 310 and the pull-up unit 320, which receives the pre-charge signal and the pull-down control signal GPWL1, GPWL2, and controls whether to output the scan signal OUT according to the pre-charge signal and the pull-down control signal GPWL1, GPWL2. Pull down to reference potential VGL. After the first pull-down unit 330 pulls down the scan signal OUT to the reference potential VGL, the first pull-down unit 330 maintains the scan signal OUT at the reference potential VGL. The first pull-down unit 330 includes transistors M5 - M9 . The transistors M5 - M9 may be amorphous silicon thin film transistors or low temperature polysilicon thin film transistors, etc., but are not limited thereto. The gate and the first source-drain of the transistor M5 input the pull-down control signal GPWL1. The gate of the transistor M6 inputs the pull-down control signal GPWL2 , the first source-drain of the transistor M6 is coupled to the reference potential VGL, and the second source-drain of the transistor M6 is coupled to the second source-drain of the transistor M5 . The gate of the transistor M7 is coupled to the node X, the first source-drain of the transistor M7 is coupled to the reference potential VGL, and the second source-drain of the transistor M7 is coupled to the second source-drain of the transistor M5. The gate of the transistor M8 is coupled to the second source-drain of the transistor M7, the first source-drain of the transistor M8 is coupled to the reference potential VGL, and the second source-drain of the transistor M8 is coupled to the node X. The gate of the transistor M9 is coupled to the second source-drain of the transistor M7, the first source-drain of the transistor M9 is coupled to the reference potential VGL, and the second source-drain of the transistor M9 is coupled to the node Y.

The second pull-down unit 340 is coupled to the pre-charge unit 310 and the pull-up unit 320, it receives the pre-charge signal and the pull-down control signals GPWL1, GPWL2, and controls whether to pull down the scan signal OUT according to the pre-charge signal and the pull-down control signals GPWL1, GPWL2 to the reference potential VGL. After the second pull-down unit 340 pulls down the scan signal OUT to the reference potential VGL, the second pull-down unit 340 maintains the scan signal OUT at the reference potential VGL. The second pull-down unit 340 includes transistors M10 - M14 . The transistors M10 - M14 may be amorphous silicon thin film transistors or low temperature polysilicon thin film transistors, etc., but are not limited thereto. A pull-down control signal GPWL2 is input to the gate and the first source-drain of the transistor M10 . The gate of the transistor M11 inputs the pull-down control signal GPWL1 , the first source-drain of the transistor M11 is coupled to the reference potential VGL, and the second source-drain of the transistor M11 is coupled to the second source-drain of the transistor M10 . The gate of the transistor M12 is coupled to the node X, the first source-drain of the transistor M12 is coupled to the reference potential VGL, and the second source-drain of the transistor M12 is coupled to the second source-drain of the transistor M10 . The gate of the transistor M13 is coupled to the second source-drain of the transistor M12 , the first source-drain of the transistor M13 is coupled to the reference potential VGL, and the second source-drain of the transistor M13 is coupled to the node X. The gate of the transistor M14 is coupled to the second source-drain of the transistor M12, the first source-drain of the transistor M14 is coupled to the reference potential VGL, and the second source-drain of the transistor M14 is coupled to the node Y.

Please refer to FIG. 4 , which shows a timing diagram of the gate driving circuit 200A in FIG. 2 . As shown in Figure 4, the start signal STV rises from a low level to a high level (reference potential VGH) at time point t0, and then clock signals C1-C8 rise to The high level makes the scan signals OUT(1)˜OUT(N) correspondingly rise to the high level in sequence (FIG. 4 only shows the scan signals OUT(1)˜OUT(3)). When the clock signals C1 - C8 drop to the low level (ie, the reference potential VGL) sequentially, the scan signals OUT( 1 ) - OUT( 8 ) correspondingly drop to the low level. The clock signal C2 lags behind the clock signal C1 by two data writing time H, the clock signal C3 lags behind the clock signal C2 by two data writing time H, and so on. The scan signals OUT( 4 )˜OUT(N) (not shown in the figure) are also sequentially raised to a high level and lowered to a low level according to the above description, so as to respectively drive corresponding pixel rows in the display panel 110 .

For each shift register 210A(1)-210A(N) and 210B(1)-210B(N) in FIG. 1)～OUT'(N) is turned on by the input signal IN1 before the two data writing time H when the reference potential VGL rises to the reference potential VGH, so that the potential of node X rises to the reference potential VGH minus The threshold voltage Vt of transistor M1 (ie VGH-Vt).

Then, after two data writing time H, the transistor M3 is turned on by the clock signal CN1, so that the potential of the node X is increased to VGH-Vt+Vc by the coupling effect of the capacitor Cx, and the scanning signal OUT(1)-OUT(N), OUT'(1)-OUT'(N) rise from the reference potential VGL to the reference potential VGH. In this embodiment, the voltage difference Vc is (VGH-VGL)×[C _gs /(C _pl +C _gs )], where C _gs is the parasitic capacitance of transistor M3, and C _pl is the value seen by node X, etc. Effective capacitance.

Then, after 8 data writing time H, the transistor M3 is turned off by the clock signal CN1, so that the potential of the node X is lowered to VGH-Vt, and the scanning signals OUT(1)-OUT(N), OUT'(1)˜OUT'(N) drop from the reference potential VGH to the reference potential VGL.

Finally, after two data writing times H, the transistor M2 is turned off by the input signal IN2, and the transistor M4 is turned on by the clock signal CN2, so that the potential of the node X drops to the reference potential VGL .

Taking the shift register 210A(1) as an example, at the time point t0, the start signal STV rises to the reference potential VGH to turn on the transistor M1, so that the potential of the node X rises to VGH-Vt. At the time point t2, the clock signal C1 rises to the reference potential VGH to turn on the transistor M3, so that the potential of the node X is increased to VGH-Vt+Vc by the coupling effect of the capacitor Cx, and the scanning signal OUT(1 ) rises from the reference potential VGL to the reference potential VGH. At the time point t10, the scan signal OUT(1) drops to the reference potential VGL to turn off the transistor M3, so that the potential of the node X drops to VGH-Vt, and the scan signal OUT(1) drops from the reference potential VGH to Reference potential VGL. At time t12, the scan signal OUT(2) drops to the reference potential VGL to turn off the transistor M2, and the clock signal C6 rises to the reference potential VGH to turn on the transistor M4, so that the potential of the node X drops to Reference potential VGL.

In the timing diagram shown in FIG. 4, when the scanning signals OUT(1)~OUT(N), OUT'(1)~OUT'(N) rise from the reference potential VGL to the reference potential VGH, the potential of the node X rises. High to VGH-Vt, not directly to VGH-Vt+Vc. The potential of the node X does not rise from VGH-Vt to VGH-Vt+Vc until two more data writing times H have elapsed. In addition, when the scanning signals OUT(1)~OUT(N), OUT'(1)~OUT'(N) drop from the reference potential VGH to the reference potential VGL, the potential of the node X drops to VGH-Vt instead of directly dropping Is the reference potential VGL. The potential of the node X drops from VGH-Vt to the reference potential VGL until two more data writing time H have elapsed. The advantage of the circuit diagram shown in FIG. 3 and the timing diagram shown in FIG. 4 is that the potentials of the scanning signals OUT(1)~OUT(N), OUT'(1)~OUT'(N) can be completely controlled by the electric potential. The turn-on and turn-off states of crystal M3 are determined, and can make the potential of node X more stable and less susceptible to interference from other noises, thereby improving the display quality of the display device and avoiding water ripples or horizontal lines in the displayed image. Problems such as streaks are eliminated, so that the display device has high reliability and high stability.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention It shall prevail as defined in the claims.

Claims (13)

1. a kind of shift register, it is characterised in that the shift register is included：

Precharge unit, the precharge unit is used to receive the first input signal and the second input signal, And be pre-charged to be exported by first node according to first input signal and second input signal Signal, wherein the precharge unit is included：

First electric crystal, its gate and its first source drain receive first input signal, and its Second source drain couples the first node and exports the precharging signal；And

Second electric crystal, its gate and its first source drain receive second input signal, and its Second source drain couples the second source drain of first electric crystal；

Pull-up unit, its described precharge unit of coupling, the pull-up unit is used to according to the precharge Signal, the first clock signal and second clock signal and scanning signal is exported by Section Point, wherein described Pull-up unit is included：

3rd electric crystal, its gate receives the precharging signal, and its first source drain receives described First clock signal, and its second source drain couples described Section Point and exports the scanning signal；

Electric capacity, its first end couples the gate of the 3rd electric crystal, and the coupling of its second end is described Second source drain of the 3rd electric crystal；And

4th electric crystal, its gate receives the second clock signal, its first source drain coupling ginseng Current potential is examined, and its second source drain couples the gate of the 3rd electric crystal；

First drop-down unit, its coupling precharge unit and described pull-up unit, described first is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control signal, and To according to the precharging signal, the first drop-down control signal and the second drop-down control signal To control whether for the scanning signal to be pulled down to the reference potential；And

Second drop-down unit, its coupling precharge unit and described pull-up unit, described second is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control Signal, and to according to the precharging signal, the first drop-down control signal and described second drop-down Control signal controls whether for the scanning signal to be pulled down to the reference potential.

2. shift register as claimed in claim 1, it is characterised in that first input signal is Initial signal, and second input signal is the next stage shift register of the correspondence shift register The scanning signal for being exported.

3. shift register as claimed in claim 1, it is characterised in that first input signal is The scanning signal that the upper level shift register of the correspondence shift register is exported, and it is described second defeated Enter the scanning signal that the next stage shift register that signal is the correspondence shift register is exported.

4. shift register as claimed in claim 1, it is characterised in that first input signal is The scanning signal that the upper level shift register of the correspondence shift register is exported, and it is described second defeated It is end signal to enter signal.

5. shift register as claimed in claim 1, it is characterised in that first clock signal exists Changed to low level by high levle during first time point, the second clock signal is in the first time point Changed to high levle by low level during rear the second time point, second time point and the very first time Point two Data writing times of difference.

6. shift register as claimed in claim 1, it is characterised in that the first drop-down unit bag Contain：

5th electric crystal, its gate and its first source drain are input into the first drop-down control signal；

6th electric crystal, its gate is input into the second drop-down control signal, its first source drain coupling institute Reference potential is stated, and its second source drain couples the second source drain of the 5th electric crystal；

7th electric crystal, its gate couples the first node, and its first source drain coupling is described with reference to electricity Position, and its second source drain couples the second source drain of the 5th electric crystal；

8th electric crystal, its gate couples the second source drain of the 7th electric crystal, its first source drain The reference potential is coupled, and its second source drain couples the first node；And

9th electric crystal, its gate couples the second source drain of the 7th electric crystal, its first source drain The reference potential is coupled, and its second source drain couples the Section Point.

7. shift register as claimed in claim 1, it is characterised in that the second drop-down unit bag Contain：

Tenth electric crystal, its gate and its first source drain are input into the second drop-down control signal；

11st electric crystal, its gate is input into the first drop-down control signal, its first source drain coupling The reference potential, and its second source drain couples the second source drain of the tenth electric crystal；

12nd electric crystal, its gate couples the first node, and its first source drain couples the reference Current potential, and its second source drain couples the second source drain of the tenth electric crystal；

13rd electric crystal, its gate couples the second source drain of the 12nd electric crystal, its first source Drain couples the reference potential, and its second source drain couples the first node；And

14th electric crystal, its gate couples the second source drain of the 12nd electric crystal, its first source Drain couples the reference potential, and its second source drain couples the Section Point.

8. a kind of display device, it is characterised in that the display device is included：

Display panel；

Multiple clock cables, it is used to provide multiple clock signals；And

Shift LD device, it is used to drive the display panel, the shift LD device to include multiple Shift register, and each described shift register and its upper level shift register or the displacement of its next stage Register is mutually coupled, and wherein each described shift register is included：

Precharge unit, the precharge unit is used to receive the first input signal and the second input letter Number, and to pre- by first node output according to first input signal and second input signal Charging signals, wherein the precharge unit is included：

First electric crystal, its gate and its first source drain receive first input signal, and its Second source drain exports the precharging signal；And

Second electric crystal, its gate and its first source drain receive second input signal, and its Second source drain couples the second source drain of first electric crystal；

Pull-up unit, its described precharge unit of coupling, the pull-up unit is used to according to the precharge Signal, the first clock signal of the clock signal and second clock signal and by Section Point export scan Signal, wherein the pull-up unit is included：

3rd electric crystal, its gate receives the precharging signal, and its first source drain coupling is described It is used to provide the first clock cable of first clock signal, and its second source drain in clock signal Export the scanning signal；

Electric capacity, its first end couples the gate of the 3rd electric crystal, and the coupling of its second end is described Second source drain of the 3rd electric crystal；And

4th electric crystal, its gate is used to provide the second clock letter in coupling the clock signal Number second clock holding wire, its first source drain coupling reference potential, and its second source drain coupling institute State the gate of the 3rd electric crystal；

First drop-down unit, its coupling precharge unit and described pull-up unit, described first is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control signal, and To according to the precharging signal, the first drop-down control signal and the second drop-down control signal To control whether for the scanning signal to be pulled down to the reference potential；And

Second drop-down unit, its coupling precharge unit and described pull-up unit, described second is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control Signal, and to according to the precharging signal, the first drop-down control signal and described second drop-down Control signal controls whether for the scanning signal to be pulled down to the reference potential.

9. display device as claimed in claim 8, it is characterised in that the shift register is N grades Shift register, first input signal and second input in the 1st grade of shift register Signal is respectively the scanning signal that initial signal and the 2nd grade of shift register are exported, the N First input signal and second input signal in level shift register are respectively (N-1) Institute in scanning signal and end signal, and the i-stage shift register that level shift register is exported It is respectively that (i-1) level shift register is exported to state the first input signal and second input signal Scanning signal and the scanning signal that is exported of (i+1) level shift register, wherein i is greater than 1 And the positive integer less than N.

10. display device as claimed in claim 8, it is characterised in that first clock signal exists Changed to low level by high levle during first time point, the second clock signal is in the first time point Changed to high levle by low level during rear the second time point, second time point and the very first time Point two Data writing times of difference.

11. a kind of shift registers, it is characterised in that the shift register is included：

Precharge unit, the precharge unit is used to receive the first input signal and the second input signal, And be pre-charged to be exported by first node according to first input signal and second input signal Signal；

Pull-up unit, its described precharge unit of coupling, the pull-up unit is used to according to the precharge Signal, the first clock signal and second clock signal and scanning signal is exported by Section Point；

First drop-down unit, its coupling precharge unit and described pull-up unit, described first is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control signal, and To according to the precharging signal, the first drop-down control signal and the second drop-down control signal To control whether for the scanning signal to be pulled down to the reference potential；And

Second drop-down unit, its coupling precharge unit and described pull-up unit, described second is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control Signal, and to according to the precharging signal, the first drop-down control signal and described second drop-down Control signal controls whether for the scanning signal to be pulled down to the reference potential；

Wherein described first input signal is initial signal, and second input signal is the correspondence shifting The scanning signal that the next stage shift register of bit register is exported.

12. a kind of shift registers, it is characterised in that the shift register is included：

Precharge unit, the precharge unit is used to receive the first input signal and the second input signal, And be pre-charged to be exported by first node according to first input signal and second input signal Signal；

Pull-up unit, its described precharge unit of coupling, the pull-up unit is used to according to the precharge Signal, the first clock signal and second clock signal and scanning signal is exported by Section Point；

First drop-down unit, its coupling precharge unit and described pull-up unit, described first is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control signal, and To according to the precharging signal, the first drop-down control signal and the second drop-down control signal To control whether for the scanning signal to be pulled down to the reference potential；And

Second drop-down unit, its coupling precharge unit and described pull-up unit, described second is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control Signal, and to according to the precharging signal, the first drop-down control signal and described second drop-down Control signal controls whether for the scanning signal to be pulled down to the reference potential；

Wherein described first input signal is that the upper level shift register institute of the correspondence shift register is defeated The scanning signal for going out, and second input signal is that the next stage displacement for corresponding to the shift register is posted The scanning signal that storage is exported.

13. a kind of shift registers, it is characterised in that the shift register is included：

Precharge unit, the precharge unit is used to receive the first input signal and the second input signal, And be pre-charged to be exported by first node according to first input signal and second input signal Signal；

Pull-up unit, its described precharge unit of coupling, the pull-up unit is used to according to the precharge Signal, the first clock signal and second clock signal and scanning signal is exported by Section Point；

First drop-down unit, its coupling precharge unit and described pull-up unit, described first is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control signal, and To according to the precharging signal, the first drop-down control signal and the second drop-down control signal To control whether for the scanning signal to be pulled down to the reference potential；And

Second drop-down unit, its coupling precharge unit and described pull-up unit, described second is drop-down Unit is used to receive the precharging signal, the first drop-down control signal and the second drop-down control Signal, and to according to the precharging signal, the first drop-down control signal and described second drop-down Control signal controls whether for the scanning signal to be pulled down to the reference potential；

Wherein described first input signal is that the upper level shift register institute of the correspondence shift register is defeated The scanning signal for going out, and second input signal is end signal.