CN106899300A - A kind of redundant cyclic averaging method for gradually-appoximant analog-digital converter - Google Patents

Abstract

The invention discloses a redundant cyclic averaging method for improving the SFDR of a resistance-capacitance successive approximation analog-to-digital converter, which relates to the fields of microelectronics and solid electronics, especially in the field of resistance-capacitance successive approximation analog-to-digital converters. Capacitor setting method. The research on capacitance mismatch correction technology first considers that it is easy to realize on-chip. The correction scheme based on LMS algorithm has high precision and good calibration effect. The correction technology of traditional auxiliary DAC is the easiest to implement on-chip and has the highest success rate, but it is not easy to achieve ultra-high precision. To solve the above problems, a capacitor redundant cycle averaging method that can improve the linearity of the successive approximation analog-to-digital converter is proposed. Through Capacitance splitting and redundant dynamic averaging have the effect of correcting capacitance mismatch.

Description

A Redundant Cyclic Averaging Method for Successive Approximation Analog-to-Digital Converters

technical field

The invention relates to the fields of microelectronics and solid electronics, in particular to a method for setting capacitance in a resistance-capacitance successive approximation analog-to-digital converter in the field.

Background technique

ADC is the "bridge" between analog system and digital signal processing (DSP). ADCs are generally divided into full parallel analog-to-digital converters (Flash ADC), pipelined analog-to-digital converters (Pipeline ADC), oversampling analog-to-digital converters (ΣΔADC) and successive approximation analog-to-digital converters (SAR ADC). Compared with several types of ADCs such as pipeline, oversampling, and Flash, SAR ADC has the advantages of simple structure, small area, and easy on-chip integration. However, due to the limitations of the current process conditions, the capacitor can only meet the matching accuracy of 10 bits, and it is not easy to achieve high precision. Therefore, it is essential to use correction technology to overcome process defects in the design of high-precision ADCs. How to implement an efficient capacitor mismatch correction technology on-chip is a difficult problem that must be faced in the design of ultra-high-precision ADCs. Capacitance mismatch correction technology usually adopts the following three design schemes: scheme 1 is an auxiliary DAC foreground correction method, including the literature ATNguyen, J.Xu and Z.Yang, "A 14-bit 0.17mm ² SAR ADC in 0.13μm CMOS for high precision nerve recording”, in Proc.Of IEEE CICC, pp.1–4, 2015. This method adopts the DAC foreground correction technology to correct the capacitor mismatch error by correcting the DAC. After correction, the performance will be significantly improved, but the correction of the DAC is not only power consumption And the area is larger, and the normal work of the analog-to-digital converter needs to be interrupted. Nevertheless, the DAC-based correction scheme is currently the most mature, most stable, highest success rate and easiest to implement on-chip. Scheme 2 is a slow and precise auxiliary ADC correction method, including literature S.Chen, R.Brodersen, "A 6-bit 600-MS/s 5.3-mWAsynchronous ADC in 0.13μm CMOS," IEEE Journal of Solid-State Circuits, 2006,41(12):2669–2680. The slow and accurate auxiliary ADC correction method uses a slow and accurate auxiliary ADC to convert the input voltage together with the main ADC, and the output of the auxiliary ADC is used as a reference for the output of the main ADC, " The minimum mean square error algorithm adjusts the parameters to be corrected of the main ADC according to the output value of the auxiliary ADC, so that the difference between the two ADC outputs becomes smaller and smaller, and finally converges. The auxiliary ADC correction technology has high precision and is easy to integrate on-chip. However, in addition to the design of the main ADC, this correction method also needs to design another more accurate auxiliary ADC, which increases the complexity of the design and increases the power consumption and power consumption of the chip. area. Scheme 3 is a correction method for inserting a pseudo-random (PN) sequence, which is documented in Y.Zhou, B.Xu, Y.Chiu, "A 12bit 160MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time -DomainProximity Detector,"IEEE Journal of Solid-State Circuits,2015,50(4):920–931. This method sends the input signal to the analog-to-digital converter through the pseudo-random sequence, and the analog-to-digital converter through the pseudo-random sequence In the transmission, information such as capacitance error is carried on the amplitude of the pseudo-random sequence, and the digital output of the analog-to-digital converter is processed in the digital domain, the error estimation module is used to extract the circuit error information carried on the pseudo-random sequence, and the error correction module is used The digital output is corrected according to the estimated value of the circuit error, and finally the inserted pseudo-random sequence is eliminated in the digital output to obtain a correct digital output. Although the correction algorithm of inserting a pseudo-random (PN) sequence has high precision, it is not easy to converge, and it is not easy to implement on-chip.

There are many different types of successive approximation analog-to-digital converters. Under a specific process, selecting an appropriate circuit structure and size of passive components to meet the matching requirements is one of the key technologies in SAR ADC design. According to different quantization methods, SAR ADCs are mainly divided into charge redistribution type and mixed resistor-capacitor type. For the charge redistribution type, the number of internal capacitors increases exponentially with the number of digits, and the area is large. Therefore, high-precision successive approximation analog-to-digital converters often use a mixed resistor-capacitor structure. In the mixed resistor-capacitor structure, Resistors and capacitors are used. The high-order DAC and the low-order DAC are respectively composed of a binary capacitor array and a resistor string. Therefore, the total capacitance value is smaller than the binary capacitor structure with the same precision, which effectively reduces the area of the capacitor array, and the area becomes smaller. speed up. The advantage of the hybrid resistor-capacitor type is that there are no floating nodes, good linearity, and can improve the static characteristics of the analog-to-digital converter. Therefore, the hybrid resistor-capacitor structure is often used in high-precision successive approximation analog-to-digital converters with more than 14 bits. Taking the 14-bit mixed resistor-capacitor successive approximation analog-to-digital converter as an example, as shown in Fig. The bit capacitor DAC contains a total of 64 unit capacitors.

Contents of the invention

The research on capacitance mismatch correction technology first considers that it is easy to realize on-chip. The correction scheme based on LMS algorithm has high precision and good calibration effect. The correction technology of traditional auxiliary DAC is the easiest to implement on-chip and has the highest success rate, but it is not easy to achieve ultra-high precision. To solve the above problems, a capacitor redundant cycle averaging method that can improve the linearity of the successive approximation analog-to-digital converter is proposed. Through The capacitance is split and redundant dynamic average, so as to achieve the purpose of correcting capacitance mismatch.

The technical scheme of the present invention is a kind of redundant cycle average method that improves resistance-capacitance type successive approximation analog-to-digital converter SFDR, and this method comprises:

Step 1: Set 80 unit capacitors at the positive capacitor array and the negative capacitor array of the hybrid resistor-capacitor-type successive approximation analog-to-digital converter, and divide the unit capacitors of the positive capacitor array and the negative capacitor array into one group, with a total of 80 Group unit capacitors are numbered C1, C2, C3...C80 from left to right, and then the first 32 groups of unit capacitors C1-C32 are divided into 32C capacitor groups, C33-C48 are divided into 16C capacitor groups, and C49-C64 are divided into For redundant 16C capacitor groups, divide C65-C72 into 8C capacitor groups, divide C73-C76 into 4C capacitor groups, divide C77-C78 into 2C capacitor groups, and the last two are 1C capacitor groups;

Step 2: According to the binary search algorithm, the i-th input voltage is successively approximated to the bit cycle of the analog-to-digital converter to obtain the conversion result, and the cyclic displacement of the second sampling is determined according to the input result;

Step 3: Carry out cyclic displacement of 80 groups of unit capacitors according to the cyclic displacement obtained in step 2, and re-determine the unit capacitances in the 32C, 16C, redundant 16C, 8C, 4C, 2C, 1C, and 1C capacitor groups;

Step 4: Under the method of dividing the capacitor bank in step 3, perform a traditional successive approximation analog-to-digital converter bit cycle on the ith input voltage according to the binary search algorithm to obtain the conversion result;

Step 5: Calculate the average of the conversion results of Step 2 and Step 4, and the average value is the conversion result of the i-th input voltage.

The present invention proposes a redundant cyclic averaging technique that can improve the linearity of successive approximation analog-to-digital converters. It is characterized in that it does not need to introduce the minimum mean square error algorithm, only needs to split the capacitor into unit capacitors, add redundant bits and Using dynamic cycle and averaging technology, the capacitance mismatch error can be dynamically offset. The capacitance redundancy cyclic averaging method proposed by the present invention can avoid the continuous accumulation of capacitance mismatch errors. Therefore, compared with the traditional correction method that relies on correction algorithms to improve linearity, it has simpler structure, smaller chip area, and is easier to use in effect achieved on-chip.

Description of drawings

Figure 1 is a traditional 14-bit resistor-capacitor successive approximation analog-to-digital converter.

FIG. 2 is a 14-bit resistor-capacitor successive approximation analog-to-digital converter proposed by the present invention.

FIG. 3 is a schematic diagram of the capacitance redundancy and cyclic average method proposed by the present invention for positive capacitance arrays.

Fig. 4 is a comparison of the spurious-free dynamic range SFDR Monte Carlo simulation results between the traditional 14-bit RCC SAC and the 14-bit RCC SAC ADC proposed by the present invention.

detailed description

The present invention proposes a capacitance redundant cycle averaging method that can improve the linearity of the resistance-capacitance successive approximation analog-to-digital converter. After adding redundant bits, the capacitance is split into unit capacitance, and the input voltage is sampled and then converted. The same input The voltage is converted twice, and different capacitor arrays are used for the two conversions, so as to achieve the purpose of improving linearity. The 14-bit resistor-capacitor successive approximation analog-to-digital converter is taken as an example to describe in detail below. The system structure of the 14-bit resistance-capacitance type successive approximation analog-to-digital converter proposed by the present invention is shown in Figure 2, and it is jointly made up of high 6-bit capacitance DAC and low 8-bit resistance DAC and comparator, and traditional difference is that, The traditional high 6-bit capacitor DAC contains 64 unit capacitors, but in the 14-bit resistor-capacitor SAC ADC proposed by the present invention, the high 6-bit capacitor DAC contains 80 unit capacitors.

Fig. 3 is the capacitance redundancy and cycle averaging method proposed by the present invention. On the basis of the traditional binary capacitor array Figure 3(a), insert redundant capacitor 16C (Figure 3(b)), and then split the binary capacitor array into unit capacitor arrays, which are numbered C1, C2...C80 from left to right , that is, 32C is composed of the first 32 unit capacitors C1-C32, 16C is composed of C33-C48, redundant 16C is composed of C49-C64, and so on, after sampling the input voltage, it is converted, assuming the i-th input voltage Vin( i)=0.0391, according to the result of the traditional successive approximation analog-to-digital converter bit cycle, 32C, 8C and C are connected to VREFP, and the remaining capacitors are connected to VREFN, that is, a total of 41 unit capacitors are connected to VREFP, and the displacement of the capacitor cycle is 41, followed by , the i-th input voltage is still converted, but the capacitor array is cyclically shifted, and the displacement is 41, that is, 32C is composed of C42-C73, and 16C is composed of the last 7 capacitors C74-C80 and the first 9 capacitors C1-C9 Composed together, the redundant 16C is composed of C10-C25, and so on. After the reordering, the capacitors are bit-circulated according to the traditional successive approximation analog-to-digital converter binary search algorithm. Assuming that after the conversion is completed, 41 unit capacitors are still connected to VREFP, then The displacement is still 41, that is, in the next conversion, 32C is composed of C3-C34, 16C is composed of C35-C50, and so on, and the digital codes of the two conversions are averaged to obtain the final digital code corresponding to Vin(i). After the conversion of the i-th input voltage Vin(i) is completed, the next conversion is performed. Assuming that the next input voltage Vin(j)=0.0031, according to the result of the traditional successive approximation analog-to-digital converter bit cycle, 32C and 8C are connected to VREFP, and the remaining The capacitor is connected to VREFN, that is, a total of 40 unit capacitors are connected to VREFP, and the capacitance cycle displacement is 40, that is, in the next conversion, 32C is composed of C43-C74, and 16C is composed of the last 6 capacitors C75-C80 and the first 10 capacitors C1 -C10 together form, and so on.

The feature of the present invention is that only the binary capacitor array needs to be split into unit capacitors in the analog domain to perform redundant dynamic circulation, which is very beneficial for circuit realization. The invention proposes a new simple and easy-to-implement capacitance redundant cycle averaging technology. Compared with other capacitance error calibration methods, the method has the advantages of simple calibration circuit, no influence on the working speed of the circuit, and insensitivity to changes in the working environment.

Carry out matlab simulation to the traditional and the 14-bit resistor-capacitor type successive approximation analog-to-digital converter of the present invention, the spurious-free dynamic range SFDR simulation result is shown in Figure 4, the value of the unit capacitance is 100f, and the unit capacitance mismatch error They are 0.001 and 0.002 respectively, and the number of Monte Carlo simulations is 500 times.

Table 1 summarizes the performance comparison of the SFDR Monte Carlo simulation of the traditional resistor-capacitor successive approximation analog-to-digital converter and the resistor-capacitor successive approximation analog-digital converter proposed by the present invention. Table 1 shows that: compared with the traditional resistor-capacitor successive approximation analog-to-digital converter, when the unit capacitance mismatch error When the value is 0.001, the present invention improves the average value of SFDR by 21.7dB, when the unit capacitance mismatch error When the value is 0.002, the present invention increases the average value of SFDR by 22.2dB.

The present invention proposes a new capacitor redundant cycle averaging technology for traditional resistor-capacitor successive approximation analog-to-digital converters. It only needs to split the capacitor into unit capacitors and perform redundant cycles to achieve linearity optimization. The control logic is simple, and the hardware overhead is small. Compared with the traditional method of using noise shaping technology or correction algorithm to improve linearity, the present invention has the characteristics of simple calibration circuit, no influence on analog-to-digital conversion speed, and insensitivity to changes in the working environment.

Table 1: SFDR simulation comparison of traditional 14-bit SAR ADC and 14-bit SAR ADC proposed by the present invention

Claims (1)

1. A kind of redundant cycle mean method that improves resistance-capacitance type successive approximation analog-to-digital converter SFDR, this method comprises: Step 1: Set 80 unit capacitors at the positive capacitor array and the negative capacitor array of the hybrid resistor-capacitor-type successive approximation analog-to-digital converter, and divide the unit capacitors of the positive capacitor array and the negative capacitor array into one group, with a total of 80 Group unit capacitors are numbered C1, C2, C3...C80 from left to right, and then the first 32 groups of unit capacitors C1-C32 are divided into 32C capacitor groups, C33-C48 are divided into 16C capacitor groups, and C49-C64 are divided into For redundant 16C capacitor groups, divide C65-C72 into 8C capacitor groups, divide C73-C76 into 4C capacitor groups, divide C77-C78 into 2C capacitor groups, and the last two are 1C capacitor groups; Step 2: According to the binary search algorithm, the i-th input voltage is successively approximated to the bit cycle of the analog-to-digital converter to obtain the conversion result, and the cyclic displacement of the second sampling is determined according to the input result; Step 3: Carry out cyclic displacement of 80 groups of unit capacitors according to the cyclic displacement obtained in step 2, and re-determine the unit capacitances in the 32C, 16C, redundant 16C, 8C, 4C, 2C, 1C, and 1C capacitor groups; Step 4: Under the method of dividing the capacitor bank in step 3, perform a traditional successive approximation analog-to-digital converter bit cycle on the ith input voltage according to the binary search algorithm to obtain the conversion result; Step 5: Calculate the average of the conversion results of Step 2 and Step 4, and the average value is the conversion result of the i-th input voltage.