CN106877879A - The method and encoder of data processing - Google Patents
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- H—ELECTRICITY
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
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Abstract
This disclosure relates to the method and encoder of a kind of data processing, the encoder is configured with the encoder matrix for carrying out encoding operation to target data to be encoded, and the encoder matrix includes the first matrix and the second matrix and the 3rd matrix, and the encoder includes：Buffer and register, and the arithmetic unit being connected with the buffer and the register respectively, wherein, the buffer, for caching first matrix and the second matrix；The register, for storing the 3rd matrix；The arithmetic unit, for obtaining first matrix and the second matrix from the buffer, and obtains the 3rd matrix, and according to first matrix and second matrix and the 3rd matrix for obtaining, the target data encode to obtain check code from the register.
Description
Technical field
This disclosure relates to data processing field, in particular it relates to the method and encoder of a kind of data processing.
Background technology
, it is necessary to complete the coding of data, existing coding square by encoder matrix during being encoded to data
Matrix data in battle array is stored in the different memory space of encoder (such as different buffers), so, to be encoded
Target data when being encoded, it is necessary to obtain corresponding matrix data from different memory spaces, so as to to be encoded
Target data carries out encoding operation.
But, because matrix data storage is in different memory spaces, therefore when encoding operation is carried out, it is necessary to never
Matrix data is obtained in same memory space, so as to increased the complexity of encoding operation, causes code efficiency relatively low.
The content of the invention
The purpose of the disclosure is to provide the method and encoder of a kind of data processing, it is possible to increase the effect of data encoding
Rate.
To achieve these goals, the disclosure provides a kind of encoder, and the encoder is configured with for to be encoded
Target data carries out the encoder matrix of encoding operation, and the encoder matrix includes the first matrix and the second matrix and the 3rd square
Battle array, the encoder includes：Buffer and register, and the computing being connected with the buffer and the register respectively
Device, wherein, the buffer, for caching first matrix and the second matrix；The register, for storing the described 3rd
Matrix；The arithmetic unit, for obtaining first matrix and the second matrix from the buffer, and obtains from the register
3rd matrix, and according to first matrix and second matrix and the 3rd matrix for obtaining, to the mesh
Mark data encode obtaining check code.
Alternatively, the buffer, for caching first matrix and the 4th matrix, the 4th matrix is described the
The matrix obtained after two matrix-splits.
Alternatively, the arithmetic unit includes the first arithmetic device that is connected with the buffer and is connected with the register
Second arithmetic device, the first arithmetic device is connected with the second arithmetic device, and the encoder also includes respectively with described first
Arithmetic unit and the temporary storage of second arithmetic device connection；The first arithmetic device, for obtaining the target data, and
First matrix and the second matrix are obtained from the buffer, and is encoded according to first matrix and the second matrix
Treatment, and export the first result to the temporary storage；The second arithmetic device, for being obtained from the register
3rd matrix, and coded treatment is carried out according to the 3rd matrix, and export second processing knot to the temporary storage
Really；The temporary storage, the check code is obtained for storing first result and the second processing result.
Alternatively, first matrix include the first submatrix and the second submatrix, the width of first submatrix with
The data length of the target data is identical；The first arithmetic device, for obtaining the described first sub- square from the buffer
Battle array, and encoding operation is carried out according to first submatrix obtain the first operation result, and will first operation result transmission
To the second arithmetic device；The second arithmetic device, for obtaining the 3rd matrix from the register, and according to described
3rd matrix and the first operation result for receiving carry out encoding operation and obtain second processing result, and by the second processing result
Store to the temporary storage, and the second processing result is sent to the first arithmetic device；The first arithmetic device,
It is additionally operable to obtain second submatrix and the second matrix from the buffer, according to first operation result and acquisition
Second submatrix carries out encoding operation and obtains the second operation result, and according to second operation result and the second processing knot
Fruit and second matrix carry out encoding operation and obtain the first result, and first result is stored to described
Temporary storage；The temporary storage, obtains described for storing first result and the second processing result
Check code.
The disclosure also provides a kind of method of data processing, including：Obtain the first matrix in the first memory space and
Two matrixes；Obtain the 3rd matrix in the second memory space；According to obtain first matrix and second matrix and
3rd matrix, the target data to obtaining encode obtaining check code.
Alternatively, first matrix and the second matrix obtained in the first memory space includes：From the described first storage
Obtain first matrix and the 4th matrix in space, the 4th matrix is the matrix obtained after second matrix-split.
Alternatively, it is described according to first matrix and second matrix and the 3rd matrix that obtain, to institute
State target data and encode and obtain check code and include：The target data is obtained, and is obtained from first memory space
First matrix and the second matrix；Coded treatment is carried out according to first matrix and the second matrix, and to temporary storage
Export the first result；The 3rd matrix is obtained from second memory space, and is carried out according to the 3rd matrix
Coded treatment, and export second processing result to the temporary storage；Store at first result and described second
Reason result obtains the check code.
Alternatively, first matrix include the first submatrix and the second submatrix, the width of first submatrix with
The data length of the target data is identical；It is described according to first matrix for obtaining and second matrix and described the
Three matrixes, to the target data encode and obtain check code and include：Described first is obtained from first memory space
Submatrix, and encoding operation is carried out according to first submatrix obtain the first operation result；From second memory space
The 3rd matrix is obtained, and is carried out encoding operation and is obtained at second according to the 3rd matrix and the first operation result for receiving
Reason result；Second submatrix and the second matrix are obtained from first memory space, according to first operation result
Encoding operation is carried out with the second submatrix for obtaining obtain the second operation result, and according to second operation result and described the
Two results and second matrix carry out encoding operation and obtain the first result；By first result and institute
State second processing result and store to the temporary storage and obtain check code.
The disclosure provides a kind of encoder, and the encoder is configured with for carrying out coding fortune to target data to be encoded
The encoder matrix of calculation, the encoder matrix includes the first matrix and the second matrix and the 3rd matrix, and the encoder includes：Buffer
And register, and the arithmetic unit being connected with the buffer and the register respectively, wherein, the buffer, for cache this
One matrix and the second matrix；The register, for storing the 3rd matrix；The arithmetic unit, for from the buffer obtain this
One matrix and the second matrix, and the 3rd matrix is obtained from the register, and according to first matrix and second square for obtaining
Battle array and the 3rd matrix, to the target data encode obtaining check code.So, because the disclosure is by the first matrix and
Two matrixes are stored in same memory space, therefore when encoding operation is carried out, it is only necessary to obtain square from same memory space
Battle array, without obtaining corresponding matrix from different memory spaces, so as to reduce the complexity of encoding operation, improves
Code efficiency.Further, since first matrix and the second matrix of the disclosure are centrally stored in same memory space, it is to avoid
By different memory space storage matrix, this improves the utilization rate of memory space.
Other feature and advantage of the disclosure will be described in detail in subsequent specific embodiment part.
Brief description of the drawings
Accompanying drawing is, for providing further understanding of the disclosure, and to constitute the part of specification, with following tool
Body implementation method is used to explain the disclosure together, but does not constitute limitation of this disclosure.In the accompanying drawings：
Fig. 1 is a kind of structural representation of encoder that the embodiment of the present disclosure is provided；
Fig. 2 is the structural representation of another encoder that the embodiment of the present disclosure is provided；
Fig. 3 is a kind of schematic flow sheet of the method for data processing that the embodiment of the present disclosure is provided.
Specific embodiment
It is described in detail below in conjunction with accompanying drawing specific embodiment of this disclosure.It should be appreciated that this place is retouched
The specific embodiment stated is merely to illustrate and explains the disclosure, is not limited to the disclosure.
A kind of encoder that Fig. 1 is provided for the embodiment of the present disclosure, as shown in figure 1, the encoder 100 is configured with for treating
The target data of coding carries out the encoder matrix of encoding operation, and the encoder matrix includes the first matrix and the second matrix and the 3rd
Matrix, the encoder includes：Buffer 101 and register 102, and be connected with the buffer 101 and the register 102 respectively
Arithmetic unit 103, wherein,
The buffer 101, for caching first matrix and the second matrix；
The register 102, for storing the 3rd matrix；
The arithmetic unit 103, for obtaining first matrix and the second matrix from the buffer 101, and from the register 102
The 3rd matrix is obtained, and according to first matrix and second matrix and the 3rd matrix for obtaining, to the target data
Encode obtaining check code.
Wherein, the encoder matrix can be H-matrix, and the H-matrix is a check matrix, in a kind of possible implementation
In, the H-matrix is made up of the first matrix and the second matrix and the 3rd matrix, and illustratively, the distribution of the H-matrix can be：
Wherein, A, B, C, D, E, T are respectively the submatrix for constituting the H-matrix, the matrix and B and E compositions of A and C compositions
Matrix be the first matrix, T is the second matrix, and D is the 3rd matrix, in the present embodiment, first matrix and the second matrix
All it is circulation sparse matrix (being designated as first circulation sparse matrix and second circulation sparse matrix respectively), and the first circulation is sparse
Every a line of matrix includes one 1, and every a line of the second circulation sparse matrix includes at least two 1, and the 3rd matrix is to follow
Ring dense matrix, because the memory space that the 3rd matrix takes is larger, therefore, being stored by the bigger register of memory space should
3rd matrix.
It should be noted that above-mentioned circulation sparse matrix is the feature for not only having met circular matrix but also the spy for meeting sparse matrix
The matrix levied, similarly, above-mentioned circulation dense matrix is the feature for not only having met circular matrix but also the feature for meeting dense matrix
Matrix.
So, stored in same buffer by by the first matrix and the second matrix, memory space has been saved, so as to carry
The utilization rate of memory space high.
The memory space that storage in view of the first matrix takes is smaller, therefore, in order to further save memory space
Utilization rate, in another embodiment of the disclosure, the buffer can be used for caching first matrix and the 4th matrix, the 4th
Matrix is the matrix obtained after second matrix-split, and every a line of the 4th matrix only includes one 1, so, due to tearing open
The memory space that multiple matrixes after point take is less than the memory space shared by the second matrix not split, therefore, reach
Save the purpose of memory space.
In addition, in a kind of possible implementation, can be encoded to data to be encoded by an arithmetic unit
Computing, so, it is only necessary to encoding operation is completed by designing an arithmetic unit, so as to save the hardware area of encoder.
But, it is more in data, in the case that data processing pressure is larger, coding is likely to result in using an arithmetic unit
Device to the heavy load of data processing, therefore, in order to mitigate the burden of the data processing of encoder, in alternatively possible realization
In mode, as shown in Fig. 2 the arithmetic unit 103 include the first arithmetic device 1031 that is connected with the buffer 101 and with the register
The second arithmetic device 1032 of 102 connections, the first arithmetic device 1031 is connected with the second arithmetic device 1032, and the encoder 100 is also
Including the temporary storage 104 being connected with the first arithmetic device 1031 and the second arithmetic device 1032 respectively；
The first arithmetic device 1031, for obtaining the target data, and obtained from the buffer 101 first matrix and
Second matrix, and coded treatment is carried out according to first matrix and the second matrix, and exported at first to the temporary storage 104
Reason result；
The second arithmetic device 1032, for obtaining the 3rd matrix from the register 102, and enters according to the 3rd matrix
Row coded treatment, and export second processing result to the temporary storage 104；
The temporary storage 104, the check code is obtained for storing first result and the second processing result.
Illustratively, first matrix can include the first submatrix and the second submatrix, and first submatrix width
Data length with the target data is identical, such as above-mentioned H-matrix, and the first matrix of the H-matrix can include the first submatrix (i.e.
The matrix of A and C compositions) and the second submatrix (i.e. the matrix of B and E compositions), wherein, the width of first submatrix and the target
The data length of data is identical.
Because in the prior art, first submatrix and the second submatrix are also to be respectively stored in different buffers
, and the disclosure is then stored into same buffer first submatrix and the second submatrix and the second matrix, so that phase
Than having saved memory space in prior art.
In the case where the first submatrix and the second submatrix and the second matrix are stored to same buffer, can in one kind
In the encoding operation mode of energy, the first arithmetic device 1031, for obtaining first submatrix, and root from the buffer 101
Encoding operation is carried out according to first submatrix and obtain the first operation result, and first operation result is sent to second computing
Device 1032；
The second arithmetic device 1032, for obtaining the 3rd matrix from the register 102, and according to the 3rd matrix and
The first operation result for receiving carries out encoding operation and obtains second processing result, and the second processing result is stored into interim to this
Memory 104, and the second processing result is sent to the first arithmetic device 1031；
The first arithmetic device 1031, is additionally operable to obtain second submatrix and the second matrix from the buffer 101, according to
First operation result and the second submatrix for obtaining carry out encoding operation and obtain the second operation result, and according to second computing
Result and the second processing result and second matrix carry out encoding operation and obtain the first result, and by first treatment
Result is stored to the temporary storage 104.
The temporary storage 104, the check code is obtained for storing first result and the second processing result.
After check code is obtained, then the data length of the check code is final output plus the data length of target data
Code word length.
So, because the disclosure stores in same memory space the first matrix and the second matrix, therefore compiled
During code computing, it is only necessary to matrix is obtained from same memory space, without obtaining corresponding from different memory spaces
Matrix, so as to reduce the complexity of encoding operation, improves code efficiency.Further, since the first matrix of the disclosure and
Two matrixes are centrally stored in same memory space, it is to avoid by different memory space storage matrix, this improves
The utilization rate of memory space.
The method of a kind of data processing that Fig. 3 is provided for the embodiment of the present disclosure, as shown in figure 3, the embodiment of the present disclosure can be with
Data encoding is applied to, the method includes：
S301, the first matrix and the second matrix obtained in the first memory space.
Wherein, first memory space can be buffer.
In a kind of possible implementation, it is contemplated that the memory space that the storage of the first matrix takes is smaller, therefore, it is
The further utilization rate for saving memory space, can be the 4th by second matrix-split in another embodiment of the disclosure
Matrix, obtains first matrix and the 4th matrix from first memory space, so, due to fractionation after multiple matrixes take
Memory space be less than memory space shared by the second matrix for not splitting, therefore, it is possible to save memory space.
S302, the 3rd matrix obtained in the second memory space.
Second memory space can be register.
S303, first matrix and second matrix and the 3rd matrix according to acquisition, to the target data for obtaining
Encode obtaining check code.
In this step, the target data can be obtained, and first matrix and is obtained from first memory space
Two matrixes；Coded treatment is carried out according to first matrix and the second matrix, and the first result is exported to temporary storage；From
The 3rd matrix is obtained in second memory space, and coded treatment is carried out according to the 3rd matrix, and to the temporary storage
Output second processing result；Store first result and the second processing result obtains the check code.
Illustratively, due to first matrix include the first submatrix and the second submatrix, and first submatrix width
Data length with the target data is identical；Therefore, in the alternatively possible implementation of this step, first can be deposited from this
Storage obtains first submatrix in space, and carries out encoding operation according to first submatrix and obtain the first operation result；From this
The 3rd matrix is obtained in second memory space, and encoding operation is carried out according to the 3rd matrix and the first operation result for receiving
Obtain second processing result；Second submatrix and the second matrix are obtained from first memory space, according to first computing
Result and the second submatrix for obtaining carry out encoding operation and obtain the second operation result, and according to second operation result and this
Two results and second matrix carry out encoding operation and obtain the first result；By first result and this second
Result is stored to the temporary storage and obtains check code.
Using the above method, when encoding operation is carried out, it is only necessary to matrix is obtained from same memory space, without
Corresponding matrix is obtained from different memory spaces, so as to reduce the complexity of encoding operation, code efficiency is improve.
Describe the preferred embodiment of the disclosure in detail above in association with accompanying drawing, but, the disclosure is not limited to above-mentioned reality
The detail in mode is applied, in the range of the technology design of the disclosure, various letters can be carried out with technical scheme of this disclosure
Monotropic type, these simple variants belong to the protection domain of the disclosure.
It is further to note that each particular technique feature described in above-mentioned specific embodiment, in not lance
In the case of shield, can be combined by any suitable means, in order to avoid unnecessary repetition, the disclosure to it is various can
The combination of energy is no longer separately illustrated.
Additionally, can also be combined between a variety of implementation methods of the disclosure, as long as it is without prejudice to originally
Disclosed thought, it should equally be considered as disclosure disclosure of that.
Claims (8)
1. a kind of encoder, the encoder is configured with the coding square for carrying out encoding operation to target data to be encoded
Battle array, the encoder matrix includes the first matrix and the second matrix and the 3rd matrix, it is characterised in that the encoder includes：
Buffer and register, and the arithmetic unit being connected with the buffer and the register respectively, wherein,
The buffer, for caching first matrix and the second matrix；
The register, for storing the 3rd matrix；
The arithmetic unit, for obtaining first matrix and the second matrix from the buffer, and obtains from the register
3rd matrix, and according to first matrix and second matrix and the 3rd matrix for obtaining, to the mesh
Mark data encode obtaining check code.
2. encoder according to claim 1, it is characterised in that the buffer, for cache first matrix and
4th matrix, the 4th matrix is the matrix obtained after second matrix-split.
3. encoder according to claim 1, it is characterised in that the arithmetic unit include being connected with the buffer the
One arithmetic unit and the second arithmetic device being connected with the register, the first arithmetic device are connected with the second arithmetic device, institute
Stating encoder also includes the temporary storage being connected with the first arithmetic device and the second arithmetic device respectively；
The first arithmetic device, for obtaining the target data, and obtains first matrix and from the buffer
Two matrixes, and coded treatment is carried out according to first matrix and the second matrix, and exported at first to the temporary storage
Reason result；
The second arithmetic device, for obtaining the 3rd matrix from the register, and is carried out according to the 3rd matrix
Coded treatment, and export second processing result to the temporary storage；
The temporary storage, the check code is obtained for storing first result and the second processing result.
4. encoder according to claim 3, it is characterised in that first matrix includes the first submatrix and the second son
Matrix, the width of first submatrix is identical with the data length of the target data；
The first arithmetic device, for obtaining first submatrix from the buffer, and according to first submatrix
Carry out encoding operation and obtain the first operation result, and first operation result is sent to the second arithmetic device；
The second arithmetic device, for obtaining the 3rd matrix from the register, and according to the 3rd matrix and connects
The first operation result received carries out encoding operation and obtains second processing result, and the second processing result is stored to described faces
When memory, and the second processing result is sent to the first arithmetic device；
The first arithmetic device, is additionally operable to obtain second submatrix and the second matrix from the buffer, according to described
First operation result and the second submatrix for obtaining carry out encoding operation and obtain the second operation result, and according to second computing
Result and the second processing result and second matrix carry out encoding operation and obtain the first result, and by described
One result is stored to the temporary storage；
The temporary storage, the check code is obtained for storing first result and the second processing result.
5. a kind of data processing method, it is characterised in that including：
Obtain the first matrix and the second matrix in the first memory space；
Obtain the 3rd matrix in the second memory space；
According to first matrix and second matrix and the 3rd matrix that obtain, the target data to obtaining is carried out
Coding obtains check code.
6. method according to claim 5, it is characterised in that the first matrix in the memory space of the acquisition first and
Two matrixes include：
First matrix and the 4th matrix are obtained from first memory space, the 4th matrix is second matrix
The matrix obtained after fractionation.
7. method according to claim 5, it is characterised in that described according to first matrix and described second for obtaining
Matrix and the 3rd matrix, to the target data encode and obtain check code and include：
The target data is obtained, and first matrix and the second matrix are obtained from first memory space；
Coded treatment is carried out according to first matrix and the second matrix, and the first result is exported to temporary storage；
Obtain the 3rd matrix from second memory space, and coded treatment is carried out according to the 3rd matrix, and to
The temporary storage exports second processing result；
Store first result and the second processing result obtains the check code.
8. method according to claim 7, it is characterised in that first matrix includes the first submatrix and the second sub- square
Battle array, the width of first submatrix is identical with the data length of the target data；First square according to acquisition
Battle array and second matrix and the 3rd matrix, to the target data encode and obtain check code and include：
First submatrix is obtained from first memory space, and encoding operation is carried out according to first submatrix and obtained
To the first operation result；
The 3rd matrix is obtained from second memory space, and according to the 3rd matrix and the first computing knot for receiving
Fruit carries out encoding operation and obtains second processing result；
Second submatrix and the second matrix are obtained from first memory space, according to first operation result and obtaining
The second submatrix for taking carries out encoding operation and obtains the second operation result, and according to second operation result and described second at
Reason result and second matrix carry out encoding operation and obtain the first result；
First result and the second processing result are stored to the temporary storage and obtain check code.
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| CN102843147A (en) * | 2012-09-27 | 2012-12-26 | 苏州威士达信息科技有限公司 | LDPC (Low-Density Parity-Check) encoder and encoding method in DTMB (Digital Terrestrial Multimedia Broadcasting) based on cycle right shift accumulation |
| US20160380722A1 (en) * | 2015-06-25 | 2016-12-29 | Mohamed K. Hassanin | Access point (ap), user station (sta) and methods for variable length encoding and for iterative decoding |
| CN106209115A (en) * | 2016-06-29 | 2016-12-07 | 联想(北京)有限公司 | A kind of data processing method and electronic equipment |
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| CN110321294A (en) * | 2018-03-31 | 2019-10-11 | 深圳忆联信息系统有限公司 | The method and encoder of data processing |
| CN111930506A (en) * | 2020-08-13 | 2020-11-13 | 山东云海国创云计算装备产业创新中心有限公司 | Matrix scheduling method and related device |
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