CN106876367A - Three-dimensional storage test structure and preparation method thereof, method of testing - Google Patents

Abstract

The embodiment of the present invention discloses a three-dimensional memory test structure and its manufacturing method and test method. The three-dimensional memory test structure exposes a part of the metal gate of the Mth layer, so that in the development process, the test method can be used to pass Directly use the probe to test the resistance of the metal gate of the Mth layer to obtain the filling performance of the metal gate in the three-dimensional memory test structure, so as to compare the filling performance of the metal gate under different processes without waiting for the post-processing of the entire three-dimensional memory. After the terminal process is completed, the filling performance of the metal gate is tested, which shortens the development cycle and reduces the development cost.

Description

Three-dimensional memory test structure, manufacturing method and test method thereof

technical field

The invention relates to the technical field of three-dimensional memory, in particular to a three-dimensional memory test structure, a manufacturing method and a test method thereof.

Background technique

With the continuous development of planar memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar memory and pursue lower production costs per unit storage unit, the structure of three-dimensional memory emerged as the times require. At present, the technology research and development of three-dimensional memory has become the mainstream of international research and development.

However, in the process of developing a three-dimensional memory in the prior art, the resistance of the grid in the three-dimensional memory is usually tested after the three-dimensional memory is manufactured, so as to judge the filling performance of the gate in the three-dimensional memory, the cycle is long, and the cost higher.

Contents of the invention

In order to solve the above-mentioned technical problems, embodiments of the present invention provide a three-dimensional memory test structure and its manufacturing method and testing method, so as to shorten the time to know the gate filling performance in the three-dimensional memory, shorten the development period, and reduce the development cost.

In order to solve the above problems, the embodiments of the present invention provide the following technical solutions:

A three-dimensional memory test structure comprising:

base;

A stacked structure located on the surface of the substrate, the stacked structure includes N-layer metal gates arranged in steps along a predetermined direction, and an oxide layer located between two adjacent layers of metal gates, where N is greater than 1 positive integer;

A plurality of channel holes formed in the first region and the second region of the stacked structure, wherein the second region is located at the periphery of the first region, and the density of the channel holes in the second region is less than the The density of channel holes in the first region;

a memory structure formed within the channel hole;

Each metal gate and oxide layer formed above the Mth metal gate in the N-layer metal gate corresponds to the exposure structure in the predetermined area in the second area, and the exposure structure exposes the Mth layer In the partial area of the metal gate, M is a positive integer greater than zero and not greater than N.

Optionally, the exposed structure is a groove or a through hole.

Optionally, the first area is a storage area, and the second area is an electrode connection area.

Optionally, the preset area is a blank area between the channel holes in the second area.

Optionally, the thickness of the metal gate is not less than 10 nm and not greater than 80 nm.

Optionally, the channel hole structure includes: a tunneling layer, a storage layer, a barrier layer and a polysilicon layer sequentially formed on the sidewall of the channel hole.

Optionally, the metal gate includes a stacked titanium nitride metal layer and a tungsten metal layer.

Optionally, the thickness of the titanium nitride metal layer is not less than 1 nm and not more than 10 nm; the thickness of the tungsten metal layer is not less than 10 nm and not more than 100 nm.

A method for manufacturing a three-dimensional memory test structure, the method comprising:

provide the basis;

A stacked structure is formed on the surface of the substrate, the stacked structure includes N layers of oxide layers and N layers of nitride layers stacked alternately, where N is a positive integer greater than 1;

A plurality of channel holes are formed in the first region and the second region of the stack structure, the second region is located at the periphery of the first region, and the density of the channel holes in the first region is greater than that of the second region. The density of channel holes in the area;

forming a memory structure in the channel hole;

removing the nitride layer in the stacked structure to form a trench;

Filling the trench with metal to form N-layer metal gates arranged in steps along a preset direction;

Removing the part of each layer of metal gate and oxide layer located in the predetermined area in the second area above the Mth metal gate in the N layer metal gate, exposing the Mth layer metal gate part area, M It is a positive integer greater than zero and not greater than N.

Optionally, removing the metal gates of the N-layer metal gate above the M-th layer metal gate and the part of the oxide layer located in the preset area in the second region, exposing the M-th layer metal gate Some areas include:

Using a plasma focused beam to remove the metal gates of the N-layer metal gate above the M-th metal gate and the part of the oxide layer located in the preset area in the second region, exposing the M-th layer of metal gate partial area.

A method for testing a three-dimensional memory test structure, the method comprising:

Using a probe to contact the exposed area of the metal gate of the Mth layer in the three-dimensional memory test structure described in any one of the above;

According to the detection result of the probe, the filling performance of the metal gate in the three-dimensional memory test structure is obtained.

Compared with the prior art, the above-mentioned technical solution has the following advantages:

In the three-dimensional memory test structure and its test method provided by the embodiments of the present invention, the three-dimensional memory test structure exposes a part of the metal gate of the Mth layer, so that in the research and development process, the test method can be directly used to detect Test the resistance of the metal gate of the Mth layer to obtain the filling performance of the metal gate in the three-dimensional memory test structure, so as to compare the filling performance of the metal gate under different processes without waiting for the back-end process of the entire three-dimensional memory. After the completion, the filling performance of the metal gate is tested, which shortens the development cycle and reduces the development cost.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a three-dimensional memory test structure provided by an embodiment of the present invention;

FIG. 2 is a top view of a three-dimensional memory test structure provided by an embodiment of the present invention;

FIG. 3 is a flowchart of a manufacturing method of a three-dimensional memory test structure provided by an embodiment of the present invention;

FIG. 4 is a flowchart of a testing method for a three-dimensional memory testing structure provided by an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

The embodiment of the present invention provides a test structure of a three-dimensional memory, as shown in Figure 1, the test structure includes:

base1;

A stacked structure located on the surface of the substrate, the stacked structure includes N-layer metal gates 2 arranged in steps along a predetermined direction, and an oxide layer 3 located between two adjacent layers of metal gates 2, N is A positive integer greater than 1;

As shown in FIG. 2, a plurality of channel holes 4 are formed in the first region A and the second region B of the stack structure, wherein the second region B is located on the periphery of the first region A, and the The density of the channel holes 4 in the second region B is less than the density of the channel holes 4 in the first region A;

a storage structure 5 formed in the channel hole 4;

Each layer of metal gate and oxide layer formed above the Mth metal gate 21 in the N-layer metal gate 4 corresponds to the exposure structure in the predetermined area in the second area, and the exposure structure exposes the first M layers of metal gates 21 are at least part of the area, and M is a positive integer greater than zero and not greater than N.

Optionally, the exposed structure is a groove or a through hole, which is not limited in the present invention, as long as it is ensured that the exposed structure can expose at least a partial area of the Mth layer metal gate.

It should be noted that, in the embodiment of the present invention, when the test structure is specifically used for testing, M can be any value in 1-N, including 1 and N, and can also be any value in N-1 in sequence, The present invention is not limited to this, and it depends on the circumstances.

Based on the above embodiments, in an embodiment of the present invention, the first area is a storage area, and the second area is an electrode connection area. Optionally, the preset area is a blank area between the channel holes in the second area. However, the present invention is not limited thereto, as long as the existence of the preset area does not affect the normal function of the three-dimensional memory.

On the basis of any of the above embodiments, in one embodiment of the present invention, the thickness of the metal gate is not less than 10nm and not greater than 80nm; the thickness of the oxidized layer is not less than 10nm and not greater than 80nm, but The present invention is not limited to this, and it depends on the circumstances. Optionally, the total thickness of the stacked structure is greater than 1 micron, but this is not limited in the present invention, and it depends on specific circumstances.

On the basis of any of the above embodiments, in one embodiment of the present invention, as shown in FIG. 1 , the channel hole structure 5 includes: a tunneling layer sequentially formed on the side wall of the channel hole 4 51 , storage layer 52 , barrier layer 53 and polysilicon layer 54 . Wherein, the tunneling layer 52 is used to generate charges, the storage layer 52 is used to store charges, the blocking layer 53 is used to block the outflow of charges in the storage layer, and the polysilicon layer 54 is the three-dimensional memory channel structure for charge transfer.

On the basis of any of the above embodiments, in an embodiment of the present invention, the metal gate includes a stacked titanium nitride metal layer and a tungsten metal layer, wherein the titanium nitride metal layer is the tungsten metal layer The metal layer is a seed layer to facilitate the formation of the tungsten metal layer.

Based on the above embodiments, in one embodiment of the present invention, the thickness of the titanium nitride metal layer is not less than 1 nm and not more than 10 nm; the thickness of the tungsten metal layer is not less than 10 nm and not more than 100 nm. However, the present invention is not limited thereto, and it depends on the circumstances.

Correspondingly, the embodiment of the present invention also provides a method for manufacturing a three-dimensional memory test structure, as shown in FIG. 3 , the method includes:

S1: providing a substrate, optionally, the substrate is a silicon wafer.

S2: forming a stacked structure on the surface of the substrate, the stacked structure includes N oxide layers and N nitride layers stacked alternately, where N is a positive integer greater than 1.

Specifically, in one embodiment of the present invention, forming a stacked structure on the surface of the substrate includes: alternately depositing an oxide film and a nitride film on the surface of the substrate.

S3: Form a plurality of channel holes in the first region and the second region of the stack structure, the second region is located on the periphery of the first region, and the density of the channel holes in the first region is greater than the density of the channel holes in the first region The density of channel holes in the second region.

Specifically, in an embodiment of the present invention, forming a plurality of channel holes in the first region and the second region of the stack structure includes:

Etching the part of the stack structure corresponding to the first region and the second region, forming a plurality of penetrating through the stack structure at the part of the stack structure corresponding to the first region and the second region channel holes.

S4: forming a storage structure in the channel hole.

Specifically, in an embodiment of the present invention, forming the storage structure in the channel hole includes:

forming a tunneling layer on sidewalls of the channel hole;

forming a storage layer on the side surface of the tunneling layer away from the sidewall of the channel hole;

forming a barrier layer on the surface of the storage layer away from the tunneling layer;

A polysilicon layer is formed on the surface of the barrier layer away from the storage layer and the bottom of the channel hole.

S5: removing the nitride layer in the stacked structure to form a trench.

Specifically, in an embodiment of the present invention, removing the nitride layer in the stacked structure and forming the trench includes:

Etching the nitride layer in the stack structure to remove the nitride layer in the stack structure to form multiple trenches;

Cleaning the trench, optionally, cleaning the trench includes rinsing the trench with phosphoric acid, wherein the temperature of the phosphoric acid is not less than 100°C and not greater than 200°C, and the rinsing time is not less than 10 minutes, but not more than 100 minutes.

S6: Filling the trench with metal to form N-layer metal gates arranged in steps along a predetermined direction.

Specifically, in one embodiment of the present invention, filling the trench with metal to form N-layer metal gates arranged in steps along a preset direction includes:

Depositing a titanium nitride metal layer in the trench, optionally, the thickness of the titanium nitride metal layer is not less than 1 nm and not greater than 10 nm;

Depositing a tungsten metal layer on the surface of the titanium nitride metal layer, optionally, the thickness of the tungsten metal layer is not less than 10nm and not greater than 100nm;

The electrical connection part of the tungsten metal layer in the adjacent trenches is removed to form N-layer metal gates that are electrically insulated from each other and arranged in a ladder shape along a predetermined direction.

S7: removing the part of each layer of the metal gate above the Mth metal gate in the N layer metal gate and the part of the oxide layer located in the predetermined area in the second area, exposing a part of the Mth layer metal gate area , M is a positive integer greater than zero and not greater than N.

Specifically, in one embodiment of the present invention, the parts of the metal gates and oxide layers above the Mth metal gate in the N-layer metal gate that are located in the predetermined area in the second region are removed, exposing The partial region of the Mth layer metal gate includes:

Using a plasma focused beam to remove the metal gates of the N-layer metal gate above the M-th metal gate and the part of the oxide layer located in the preset area in the second region, exposing the M-th layer of metal gate partial area.

It should be noted that, after removing the metal gates of the N-layer metal gates above the M-th layer metal gates and the part of the oxide layer located in the preset area in the second region, the M-th layer of metal gates is exposed. In the gate part area, the metal gates of each layer above the metal gate of the Mth layer located on both sides of the stack structure and the part of the oxide layer located in the predetermined area in the second area are all removed, and the number of removed layers is the same.

In addition, an embodiment of the present invention also provides a test method for a three-dimensional memory test structure, as shown in FIG. 4 , the method includes:

S11: Use a probe to contact the exposed area of the metal gate of the Mth layer in the three-dimensional memory test structure provided by any one of the above-mentioned embodiments of the present invention;

S12: Obtain the filling performance of the metal gate in the three-dimensional memory test structure according to the detection result of the probe.

Optionally, in one embodiment of the present invention, the test method obtains the resistance of the Mth layer metal gate by probing the tungsten metal layer that contacts the exposed area of the Mth layer metal gate in the three-dimensional memory test structure. , so that according to the resistance of the metal gate of the Mth layer, the filling performance of the metal gate in the three-dimensional memory test structure is obtained

It can be seen from the above that in the three-dimensional memory test structure and its test method provided by the embodiments of the present invention, the three-dimensional memory test structure exposes a part of the Mth layer metal gate, so that the test method can be used in the development process The filling performance of the metal gate in the three-dimensional memory test structure is obtained by directly using the probe to test the resistance of the metal gate of the Mth layer, so as to compare the filling performance of the metal gate under different processes without waiting for the entire three-dimensional memory. After the back-end process is completed, the filling performance of the metal gate is tested, which shortens the development cycle and reduces the development cost.

Each part in this manual is described in a progressive manner, and each part focuses on the difference from other parts, and the same and similar parts of each part can be referred to each other.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A three-dimensional memory test structure, characterized in that, comprising: base; A stacked structure located on the surface of the substrate, the stacked structure includes N-layer metal gates arranged in steps along a predetermined direction, and an oxide layer located between two adjacent layers of metal gates, where N is greater than 1 positive integer; A plurality of channel holes formed in the first region and the second region of the stacked structure, wherein the second region is located at the periphery of the first region, and the density of the channel holes in the second region is less than the The density of channel holes in the first region; a memory structure formed within the channel hole; Each metal gate and oxide layer formed above the Mth metal gate in the N-layer metal gate corresponds to the exposure structure in the predetermined area in the second area, and the exposure structure exposes the Mth layer In the partial area of the metal gate, M is a positive integer greater than zero and not greater than N. 2. The test structure according to claim 1, wherein the first area is a storage area, and the second area is an electrode connection area. 3. The test structure according to claim 1, wherein the preset area is a blank area between the channel holes in the second area. 4. The test structure according to claim 1, wherein the thickness of the metal gate is not less than 10 nm and not greater than 80 nm. 5 . The test structure according to claim 1 , wherein the channel hole structure comprises: a tunneling layer, a storage layer, a barrier layer and a polysilicon layer sequentially formed on the sidewall of the channel hole. 6. The test structure according to claim 1, wherein the metal gate comprises a stacked titanium nitride metal layer and a tungsten metal layer. 7. The test structure according to claim 6, wherein the thickness of the titanium nitride metal layer is not less than 1 nm and not more than 10 nm; the thickness of the tungsten metal layer is not less than 10 nm and not more than 100 nm. 8. A method for manufacturing a three-dimensional memory test structure, characterized in that the method comprises: provide the basis; A stacked structure is formed on the surface of the substrate, the stacked structure includes N layers of oxide layers and N layers of nitride layers stacked alternately, where N is a positive integer greater than 1; A plurality of channel holes are formed in the first region and the second region of the stack structure, the second region is located at the periphery of the first region, and the density of the channel holes in the first region is greater than that of the second region. The density of channel holes in the area; forming a memory structure in the channel hole; removing the nitride layer in the stacked structure to form a trench; Filling the trench with metal to form N-layer metal gates arranged in steps along a preset direction; Removing the part of each layer of metal gate above the Mth metal gate in the N layer metal gate and the oxide layer located in the predetermined area in the second area, exposing the Mth layer metal gate part area, M It is a positive integer greater than zero and not greater than N. 9. The manufacturing method according to claim 8, characterized in that, removing the metal gates and the oxide layer of each layer above the M-th metal gate in the N-layer metal gate are located in the preset area in the second region The part that exposes the Mth layer metal gate region includes: Using a plasma focused beam to remove the metal gates of the N-layer metal gate above the M-th layer metal gate and the part of the oxide layer located in the preset area in the second region, exposing the M-layer metal gate partial area. 10. A method for testing a three-dimensional memory test structure, characterized in that the method comprises: Using a probe to contact the exposed area of the metal gate of the Mth layer in the three-dimensional memory test structure described in any one of claims 1-7; According to the detection result of the probe, the filling performance of the metal gate in the three-dimensional memory test structure is obtained.