CN106856098A - A kind of devices and methods therefor refreshed for DRAM or eDRAM - Google Patents
A kind of devices and methods therefor refreshed for DRAM or eDRAM Download PDFInfo
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
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Abstract
本发明公开了一种用于DRAM或eDRAM刷新的装置及其方法，DRAM或eDRAM设置有存储单元，该装置包括：存储控制装置、刷新控制装置；所述存储控制装置，用于接收读写请求，并根据所述刷新控制装置的输出决定向存储单元发送读写请求或刷新请求；所述刷新控制装置，用于控制生成刷新信号，并根据所述存储控制装置的输出来记录刷新是否被延迟和读写的行地址。本发明能够减少读写与刷新之间的冲突，达到增加DRAM或者eDRAM性能的效果。
The invention discloses a device and method for refreshing a DRAM or eDRAM. The DRAM or eDRAM is provided with a storage unit, and the device includes: a storage control device and a refresh control device; the storage control device is used for receiving read and write requests , and decide to send a read-write request or a refresh request to the storage unit according to the output of the refresh control device; the refresh control device is used to control the generation of a refresh signal, and record whether the refresh is delayed according to the output of the storage control device and the row address for reading and writing. The invention can reduce the conflict between read-write and refresh, and achieve the effect of increasing the performance of DRAM or eDRAM.
Description
技术领域technical field
本发明涉及刷新技术，特别是涉及一种用于DRAM或eDRAM刷新的装置及其方法。The invention relates to refreshing technology, in particular to a device and method for refreshing DRAM or eDRAM.
背景技术Background technique
在传统的刷新方式中，在每个刷新周期内都会有段时间用于刷新，如图1所示，在每个刷新周期内，时间轴被分成两个部分，一部分时间用于读写，另一部分时间用于刷新。In the traditional refresh method, there will be a period of time for refresh in each refresh cycle. As shown in Figure 1, in each refresh cycle, the time axis is divided into two parts, one part of the time is used for reading and writing, and the other is for reading and writing. A portion of the time is spent refreshing.
现有刷新方式当DRAM在进行刷新时，无法进行读写操作，被称作死区时间，降低了DRAM吞吐量，并且读写的延迟会变得很高。In the existing refresh method, when DRAM is being refreshed, read and write operations cannot be performed, which is called dead time, which reduces the throughput of DRAM, and the delay of reading and writing will become very high.
发明内容Contents of the invention
本发明的目的在于提供一种用于DRAM或eDRAM刷新的装置及其方法，用于减少刷新和读写之间的冲突问题，达到增加DRAM或者eDRAM性能的效果。The object of the present invention is to provide a device and method for refreshing DRAM or eDRAM, which are used to reduce conflicts between refreshing and reading and writing, and achieve the effect of increasing the performance of DRAM or eDRAM.
为了实现上述目的，本发明提供一种用于DRAM或eDRAM刷新的装置，DRAM或eDRAM设置有存储单元，该装置包括：存储控制装置、刷新控制装置；In order to achieve the above object, the present invention provides a device for refreshing DRAM or eDRAM. DRAM or eDRAM is provided with a storage unit, and the device includes: a storage control device and a refresh control device;
所述存储控制装置，用于接收读写请求，并根据所述刷新控制装置的输出决定向存储单元发送读写请求或刷新请求；The storage control device is configured to receive a read-write request, and decide to send a read-write request or a refresh request to the storage unit according to the output of the refresh control device;
所述刷新控制装置，用于控制生成刷新信号，并根据所述存储控制装置的输出来记录刷新是否被延迟和读写的行地址。The refresh control device is used to control the generation of a refresh signal, and record whether the refresh is delayed and the row address for reading and writing according to the output of the storage control device.
所述的用于DRAM或eDRAM刷新的装置，其中，所述存储控制装置包括：The device for refreshing DRAM or eDRAM, wherein the storage control device includes:
读缓存，用于缓存从存储单元中读出的数据；Read cache, for caching data read from the storage unit;
写缓存，用于缓存要写入到存储单元的数据；Write cache, for caching data to be written to the storage unit;
控制逻辑单元，用于接收读写请求；a control logic unit, configured to receive read and write requests;
存储控制信号发生器，用于接收所述控制逻辑单元发送的命令，并将该命令译码成存储单元可识别的命令。The storage control signal generator is used for receiving the command sent by the control logic unit, and decoding the command into a command recognizable by the storage unit.
所述的用于DRAM或eDRAM刷新的装置，其中，所述刷新控制装置包括：The device for refreshing DRAM or eDRAM, wherein the refresh control device includes:
刷新周期寄存器，用于存储刷新周期；The refresh cycle register is used to store the refresh cycle;
刷新延迟计数器，用于存储当前刷新被延迟的时间；The refresh delay counter is used to store the time when the current refresh is delayed;
刷新周期计数器，用于对每个刷新周期计时；A refresh cycle counter for timing each refresh cycle;
刷新行数计数器，用于记录当前刷新的行数；Refresh the number of rows counter, used to record the number of rows currently refreshed;
刷新逻辑单元，用于判断寄存器当前的被读写状态，并向所述控制逻辑单元发送刷新的状态；Refresh logic unit, for judging the current reading and writing state of the register, and sending the refresh state to the control logic unit;
总行数寄存器，用于存储总的行数；The total number of rows register is used to store the total number of rows;
刷新延迟寄存器，用于存储刷新总的可被延迟的时间；The refresh delay register is used to store the total refresh delay time;
读写标志寄存器，用于存储在可延迟刷新阶段内读写过的行地址。The read and write flag register is used to store the row address read and written in the deferrable refresh phase.
所述的用于DRAM或eDRAM刷新的装置，其中，所述刷新逻辑单元当接收到读写请求时，停止刷新，控制所述刷新延迟计数器开始计数，同时在所述读写标志寄存器中记录读写的行地址，并发送当前刷新是否可被打断的信号至所述控制逻辑单元。The device for refreshing DRAM or eDRAM, wherein, when the refresh logic unit receives a read/write request, it stops refreshing, controls the refresh delay counter to start counting, and records the read/write flag in the read/write flag register. Write the row address, and send a signal whether the current refresh can be interrupted to the control logic unit.
所述的用于DRAM或eDRAM刷新的装置，其中，所述刷新逻辑单元在当前刷新未完成，且当所述刷新延迟计数器中的时间等于所述刷新延迟寄存器中的时间时，返回一当前刷新不可被打断的信号至所述控制逻辑单元，控制所述控制逻辑单元继续刷新；或在当前刷新已完成或所述刷新延迟寄存器与所述刷新延迟计数器中的时间差值大于所述总行数寄存器与所述刷新行数计数器中的行数差值与每行刷新时间的乘积时，返回一可被读写的信号至所述控制逻辑单元。The device for refreshing DRAM or eDRAM, wherein the refresh logic unit is not completed in the current refresh, and when the time in the refresh delay counter is equal to the time in the refresh delay register, return a current refresh A signal that cannot be interrupted is sent to the control logic unit to control the control logic unit to continue refreshing; or when the current refresh is completed or the time difference between the refresh delay register and the refresh delay counter is greater than the total number of rows When the difference between the number of rows in the register and the refresh row counter is multiplied by the refresh time of each row, a signal that can be read and written is returned to the control logic unit.
所述的用于DRAM或eDRAM刷新的装置，其中，当刷新周期计数器中的时间等于所述刷新周期寄存器中的时间时，所述刷新周期计数器、所述刷新行数计数器、所述刷新延迟计数器归零，所述读写标志寄存器重置。The device for refreshing DRAM or eDRAM, wherein, when the time in the refresh cycle counter is equal to the time in the refresh cycle register, the refresh cycle counter, the refresh row number counter, and the refresh delay counter to zero, the read and write flags register is reset.
所述的用于DRAM或eDRAM刷新的装置，其中，所述刷新周期寄存器的刷新周期与所述刷新延迟计数器的已被延迟的时间之和小于数据保持时间。In the device for refreshing DRAM or eDRAM, the sum of the refresh period of the refresh period register and the delayed time of the refresh delay counter is less than the data retention time.
所述的用于DRAM或eDRAM刷新的装置，其中，当前待刷新的行在所述读写标志寄存器中被标记为读写过时，则跳过此行的刷新。In the device for refreshing DRAM or eDRAM, if the row to be refreshed is marked as read-write obsolete in the read/write flag register, the refresh of this row is skipped.
所述的用于DRAM或eDRAM刷新的装置，其中，所述刷新控制装置为一个或多个，各所述刷新控制装置之间的刷新相互独立。In the device for refreshing DRAM or eDRAM, there are one or more refresh control devices, and the refresh between the refresh control devices is independent of each other.
为了实现上述目的，本发明还提供一种用于DRAM或eDRAM刷新的方法，DRAM或eDRAM设置有存储单元，该方法包括：In order to achieve the above object, the present invention also provides a method for refreshing a DRAM or eDRAM, where the DRAM or eDRAM is provided with a storage unit, the method comprising:
步骤一，存储控制装置接收读写请求，并根据刷新控制装置的输出决定向存储单元发送读写请求或刷新请求；Step 1, the storage control device receives the read-write request, and decides to send a read-write request or a refresh request to the storage unit according to the output of the refresh control device;
步骤二，刷新控制装置控制生成刷新信号，并根据所述存储控制装置的输出来记录刷新是否被延迟和读写的行地址。Step 2, the refresh control device controls the generation of a refresh signal, and records whether the refresh is delayed and the row address for reading and writing according to the output of the storage control device.
所述的用于DRAM或eDRAM刷新的方法，其中，所述刷新控制装置包括：The method for refreshing DRAM or eDRAM, wherein the refresh control device includes:
刷新周期寄存器，用于存储刷新周期；The refresh cycle register is used to store the refresh cycle;
刷新延迟计数器，用于存储当前刷新被延迟的时间；The refresh delay counter is used to store the time when the current refresh is delayed;
刷新周期计数器，用于对每个刷新周期计时；A refresh cycle counter for timing each refresh cycle;
刷新行数计数器，用于记录当前刷新的行数；Refresh the number of rows counter, used to record the number of rows currently refreshed;
刷新逻辑单元，用于判断寄存器当前的被读写状态，并向所述控制逻辑单元发送刷新的状态；Refresh logic unit, for judging the current reading and writing state of the register, and sending the refresh state to the control logic unit;
总行数寄存器，用于存储总的行数；The total number of rows register is used to store the total number of rows;
刷新延迟寄存器，用于存储刷新总的可被延迟的时间；The refresh delay register is used to store the total refresh delay time;
读写标志寄存器，用于存储在可延迟刷新阶段内读写过的行地址。The read and write flag register is used to store the row address read and written in the deferrable refresh phase.
所述的用于DRAM或eDRAM刷新的方法，其中，所述步骤二中，包括：The method for refreshing DRAM or eDRAM, wherein, in the second step, comprising:
所述刷新逻辑单元当接收到读写请求时，停止刷新，控制所述刷新延迟计数器开始计数，同时在所述读写标志寄存器中记录读写的行地址，并发送当前刷新是否可被打断的信号至所述存储控制装置的控制逻辑单元。When the refresh logic unit receives a read-write request, it stops refreshing, controls the refresh delay counter to start counting, and records the row address for reading and writing in the read-write flag register at the same time, and sends whether the current refresh can be interrupted The signal is sent to the control logic unit of the storage control device.
所述的用于DRAM或eDRAM刷新的方法，其中，所述步骤二中，包括：The method for refreshing DRAM or eDRAM, wherein, in the second step, comprising:
所述刷新逻辑单元在当前刷新未完成，且当所述刷新延迟计数器中的时间等于所述刷新延迟寄存器中的时间时，返回一当前刷新不可被打断的信号至所述控制逻辑单元，控制所述控制逻辑单元继续刷新；或在当前刷新已完成或所述刷新延迟寄存器与所述刷新延迟计数器中的时间差值大于所述总行数寄存器与所述刷新行数计数器中的行数差值与每行刷新时间的乘积时，返回一可被读写的信号至所述控制逻辑单元。The refresh logic unit is not completed in the current refresh, and when the time in the refresh delay counter is equal to the time in the refresh delay register, return a signal that the current refresh cannot be interrupted to the control logic unit, and control The control logic unit continues to refresh; or when the current refresh is completed or the time difference between the refresh delay register and the refresh delay counter is greater than the row number difference between the total row number register and the refresh row number counter When the product is multiplied by the refresh time of each row, a signal that can be read and written is returned to the control logic unit.
所述的用于DRAM或eDRAM刷新的方法，其中，所述步骤二中，包括：The method for refreshing DRAM or eDRAM, wherein, in the second step, comprising:
当所述刷新周期计数器中的时间等于所述刷新周期寄存器中的时间时，所述刷新周期计数器、所述刷新行数计数器、所述刷新延迟计数器归零，所述读写标志寄存器重置。When the time in the refresh cycle counter is equal to the time in the refresh cycle register, the refresh cycle counter, the refresh row number counter, and the refresh delay counter are reset to zero, and the read-write flag register is reset.
所述的用于DRAM或eDRAM刷新的方法，其中，所述刷新周期寄存器的刷新周期与所述刷新延迟计数器的已被延迟的时间之和小于数据保持时间。In the method for refreshing DRAM or eDRAM, the sum of the refresh period of the refresh period register and the delayed time of the refresh delay counter is less than the data retention time.
所述的用于DRAM或eDRAM刷新的方法，其中，当前待刷新的行在读写标志寄存器中被标记为读写过时，则跳过此行的刷新。The method for refreshing DRAM or eDRAM, wherein, if the row to be refreshed is marked as read-write obsolete in the read-write flag register, the refreshing of this row is skipped.
所述的用于DRAM或eDRAM刷新的方法，其中，所述刷新控制装置为一个或多个，各所述刷新控制装置之间的刷新相互独立。The method for refreshing a DRAM or eDRAM, wherein there are one or more refresh control devices, and the refresh between the refresh control devices is independent of each other.
与现有技术相比，本发明的有益技术效果是：Compared with the prior art, the beneficial technical effect of the present invention is:
本发明提供了一种用于DRAM或eDRAM刷新的方法，本刷新方法改进了刷新的方式，使得刷新变得更加灵活，协调刷新与读写冲突，从而提高了DRAM的吞吐量，实现了DRAM性能的提高。具体体现在如下几个方面：The invention provides a method for refreshing DRAM or eDRAM. The refreshing method improves the refreshing method, makes refreshing more flexible, and coordinates refreshing and reading and writing conflicts, thereby improving the throughput of DRAM and realizing DRAM performance. improvement. Specifically reflected in the following aspects:
1，通过可中断刷新方式，减少刷新和读写之间的冲突问题，达到增加DRAM或者eDRAM性能的效果。1. Through the interruptible refreshing method, the conflict between refreshing and reading and writing is reduced, and the effect of increasing the performance of DRAM or eDRAM is achieved.
2，刷新时可以被读写打断，减小了读写延迟。2. When refreshing, it can be interrupted by reading and writing, which reduces the delay of reading and writing.
3，必须设定刷新周期和刷新可延迟时间之和小于数据保持时间。3. The sum of the refresh period and the refresh delay time must be set to be less than the data retention time.
4，刷新时可以被读写打断。4. It can be interrupted by reading and writing when refreshing.
5，可以有一组刷新装置，也可以多个区块bank共享一组刷新装置，也可以每个区块bank独享一组刷新装置。5. There can be a set of refreshing devices, or multiple block banks can share a set of refreshing devices, or each block bank can have a set of refreshing devices exclusively.
6，记录在可延迟刷新阶段读写过的行地址，被读写过的行可以直接跳过刷新，减少了刷新时间及功耗。6. Record the address of the row that has been read and written in the delay refresh stage, and the row that has been read and written can skip the refresh directly, reducing the refresh time and power consumption.
附图说明Description of drawings
图1是传统的刷新方式示意图；FIG. 1 is a schematic diagram of a traditional refresh method;
图2是本发明的刷新方式示意图；Fig. 2 is a schematic diagram of the refresh mode of the present invention;
图3是本发明的刷新装置结构图；Fig. 3 is a structural diagram of the refreshing device of the present invention;
图4是本发明的刷新方法流程图；Fig. 4 is a flowchart of the refreshing method of the present invention;
图5是本发明的刷新方式第一实施例；Fig. 5 is the first embodiment of the refresh mode of the present invention;
图6是本发明的刷新方式第二实施例。FIG. 6 is a second embodiment of the refresh mode of the present invention.
具体实施方式detailed description
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.
如图2所示，是本发明的刷新方式示意图。在图2中示出了刷新的时序，该DRAM刷新电路设定刷新周期小于数据的保持时间。在每个刷新周期内时间域被分成三部分，第一部分叫做刷新时间，在第一部分做刷新，但是当有读写操作时，刷新可以被打断，优先进行读写操作；第二部分叫做延迟刷新时间，在第二部分开始也是优先进行读写，但是当第二部分余下的时间恰能做完刷新操作时，则进行强制刷新操作，此时不响应读写请求。第一部分和第二部分合称为可延迟刷新阶段，第三部分叫做读写时间，在这部分只做读写操作。该刷新方法可以用于DRAM或eDRAM控制器中，下面将以DRAM控制器为例对技术方案进行描述，这同样适用于eDRAM控制器。As shown in FIG. 2 , it is a schematic diagram of the refreshing method of the present invention. FIG. 2 shows the refresh sequence, the DRAM refresh circuit sets the refresh cycle to be shorter than the data retention time. In each refresh cycle, the time domain is divided into three parts. The first part is called the refresh time, and the refresh is done in the first part, but when there is a read and write operation, the refresh can be interrupted, and the read and write operations are prioritized; the second part is called delay For the refresh time, reading and writing are given priority at the beginning of the second part, but when the rest of the second part can just finish the refresh operation, the forced refresh operation will be performed, and the read and write request will not be responded at this time. The first part and the second part are collectively called the deferrable refresh phase, and the third part is called the read and write time, and only read and write operations are performed in this part. The refresh method can be used in a DRAM or eDRAM controller, and the technical solution will be described below taking the DRAM controller as an example, which is also applicable to the eDRAM controller.
DRAM由MOS技术制造，使用电容来做存储单元(对eDRAM控制器来说，也是使用电容来做存储单元)。DRAM的功耗低，速度慢。另一方面，SRAM速度快并且不需要刷新，然而SRAM的面积太大并且更昂贵，因此DRAM应用比SRAM更广泛。DRAM is manufactured by MOS technology and uses capacitors as storage units (for eDRAM controllers, capacitors are also used as storage units). DRAM has low power consumption and is slow. On the other hand, SRAM is fast and does not need to be refreshed, however, the area of SRAM is too large and more expensive, so DRAM is more widely used than SRAM.
不像SRAM用触发器来存储信息，DRAM用电容来存储信息。但是电容会逐渐漏电，从而丢失数据。因此DRAM的存储单元需要周期性的刷新，刷新周期要小于数据保持时间，如果存储单元没有在数据保持时间内被刷新，存储信息就会丢失。Unlike SRAM, which uses flip-flops to store information, DRAM uses capacitors to store information. But the capacitor will gradually leak and lose data. Therefore, the storage unit of the DRAM needs to be periodically refreshed, and the refresh cycle is shorter than the data retention time. If the storage unit is not refreshed within the data retention time, the stored information will be lost.
如图3所示，是本发明的刷新装置结构图，图4是本发明的刷新方法流程图。As shown in FIG. 3 , it is a structural diagram of the refreshing device of the present invention, and FIG. 4 is a flow chart of the refreshing method of the present invention.
结合图3、4，该刷新装置300是用于DRAM或eDRAM刷新的装置，包括存储控制装置31和刷新控制装置32。DRAM或eDRAM包括存储单元33。Referring to FIGS. 3 and 4 , the refreshing device 300 is a device for refreshing DRAM or eDRAM, and includes a storage control device 31 and a refresh control device 32 . DRAM or eDRAM includes storage unit 33 .
刷新控制装置32用于控制生成刷新信号，存储控制装置31用于接收读写请求和向存储单元33发送刷新请求或者读写请求，存储控制装置31根据刷新控制装置32的输出来决定向存储单元33发送读写请求还是刷新请求，刷新控制装置32根据存储控制装置31的输出来记录刷新是否被延迟和读写的行地址。The refresh control device 32 is used to control the generation of a refresh signal, the storage control device 31 is used to receive a read-write request and send a refresh request or a read-write request to the storage unit 33, and the storage control device 31 decides to send a refresh request to the storage unit according to the output of the refresh control device 32. 33 to send a read-write request or a refresh request, and the refresh control device 32 records whether the refresh is delayed and the row address of the read-write according to the output of the storage control device 31 .
进一步，存储控制装置31包括：Further, the storage control device 31 includes:
读缓存1，用于缓存从存储单元33中读出的数据。The read cache 1 is used to cache data read from the storage unit 33 .
写缓存2，用于缓存将要写入到存储单元33的数据。The write buffer 2 is used for buffering data to be written into the storage unit 33 .
控制逻辑单元3，用于接收读写请求并向存储单元控制信号发生器4发送命令。The control logic unit 3 is configured to receive read and write requests and send commands to the storage unit control signal generator 4 .
存储控制信号发生器4，用于将控制逻辑单元3发送的命令译码成存储单元33可以识别的命令。The storage control signal generator 4 is used to decode the command sent by the control logic unit 3 into a command that the storage unit 33 can recognize.
进一步，刷新控制装置32作为一个区块bank，装置300中可以包含多个区块bank。Further, the refresh control device 32 is used as a block bank, and the device 300 may include multiple block banks.
进一步，刷新控制装置32包括：Further, the refresh control device 32 includes:
刷新周期寄存器5，用于存储刷新周期。Refresh period register 5, used to store the refresh period.
刷新延迟计数器6，用于存储当前刷新已经被延迟的时间。Refresh delay counter 6, used to store the current refresh has been delayed time.
刷新周期计数器7，用于记录当前刷新周期的时间，对每个刷新周期计时。The refresh cycle counter 7 is used to record the time of the current refresh cycle and count each refresh cycle.
刷新行数计数器8，用于记录当前刷新进度，如当前刷新的行数。Refresh row count counter 8 is used to record the current refresh progress, such as the current refresh row number.
刷新逻辑单元9，通过判断关于刷新的几个寄存器(即判断当前是否可以被读写)，向控制逻辑单元3发送刷新的状态。The refresh logic unit 9 sends the refresh status to the control logic unit 3 by judging several registers related to refresh (that is, judging whether they can be read or written currently).
总行数寄存器10，用于存储一个bank中总的行数。The total number of rows register 10 is used to store the total number of rows in a bank.
刷新延迟寄存器11，用于存储刷新总的可以被延迟的时间。Refresh delay register 11 is used to store the total refresh delay time.
读写标志寄存器12，用于存储可延迟刷新阶段被读写过的行地址。The read-write flag register 12 is used to store the address of the read-write row which can delay the refresh phase.
进一步地，刷新周期寄存器5存储的刷新周期小于数据保持时间。Further, the refresh period stored in the refresh period register 5 is less than the data retention time.
进一步地，刷新延迟寄存器11存储刷新可以被延迟的时间，要满足以下条件：刷新周期和刷新可以被延迟的时间之和小于或等于数据保持时间。Further, the refresh delay register 11 stores the time that the refresh can be delayed, and the following condition must be met: the sum of the refresh cycle and the time that the refresh can be delayed is less than or equal to the data retention time.
在本发明中，总共只有一组刷新装置，所有的区块bank的刷新操作相同。刷新逻辑单元9通过判断各个刷新寄存器的状态向控制逻辑单元3发送。刷新行数计数器8对区块bank刷新的行数进行计数，刷新延迟计数器11对刷新时的延迟时间进行计数，在刷新时，如果有读写请求则刷新被打断，刷新延迟计数器6开始计数，并且读写标志寄存器12记录读写过的行地址。刷新逻辑单元9发给控制逻辑单元3当前刷新是否可以被打断的信号，如果当前刷新没有完成，并且刷新延迟计数器6中的时间等于刷新延迟寄存器11中的时间，那么刷新逻辑单元9返回一个刷新不可被打断信号，并且控制逻辑单元3继续刷新剩余的行。如果刷新已完成，或者刷新延迟计数器6中的时间小于刷新延迟寄存器11中的时间，那么刷新逻辑单元9返回一个可以被读写的信号。刷新周期寄存器5存储刷新周期的时间，刷新周期计数器7一直开始计时，当刷新周期计数器7等于刷新周期时，表示到了下一个刷新周期，刷新周期计数器7，刷新行数计数器8，刷新延迟计数器6归零，读写标志寄存器12重置。In the present invention, there is only one group of refreshing devices in total, and the refreshing operations of all blocks are the same. The refresh logic unit 9 sends to the control logic unit 3 by judging the status of each refresh register. Refresh row number counter 8 counts the number of rows refreshed by the block bank, and refresh delay counter 11 counts the delay time when refreshing. When refreshing, if there is a read and write request, the refresh is interrupted, and refresh delay counter 6 starts counting , and the read-write flag register 12 records the row address read and written. Refresh logic unit 9 sends the signal whether the current refresh of control logic unit 3 can be interrupted, if the current refresh is not completed, and the time in the refresh delay counter 6 is equal to the time in the refresh delay register 11, then the refresh logic unit 9 returns a The refresh cannot be interrupted signal, and the control logic unit 3 continues to refresh the remaining rows. If the refresh is completed, or the time in the refresh delay counter 6 is less than the time in the refresh delay register 11, then the refresh logic unit 9 returns a signal that can be read and written. The refresh cycle register 5 stores the time of the refresh cycle, and the refresh cycle counter 7 starts counting all the time. When the refresh cycle counter 7 is equal to the refresh cycle, it means that the next refresh cycle is reached, the refresh cycle counter 7, the refresh row number counter 8, and the refresh delay counter 6 Return to zero, and the read and write flag register 12 is reset.
请参阅图3、4，以下结合图3详细介绍DRAM刷新电路的工作过程：Please refer to Figures 3 and 4. The working process of the DRAM refresh circuit is introduced in detail in conjunction with Figure 3 below:
初始化寄存器，刷新周期寄存器5存储了DRAM的刷新周期，总行数寄存器10存储了DRAM一个区块bank的行数，刷新延迟寄存器11存储了在刷新时刷新可以被延迟的时间。其中，刷新可延迟时间+刷新周期<＝存储单元33的数据保持时间，上述寄存器在正常工作前都需要提前配置好。The initialization register, the refresh cycle register 5 stores the refresh cycle of the DRAM, the total row number register 10 stores the row number of a block bank of the DRAM, and the refresh delay register 11 stores the time that the refresh can be delayed during refresh. Wherein, refresh delay time+refresh cycle<=data retention time of the storage unit 33, the above-mentioned registers need to be configured in advance before normal operation.
控制逻辑单元3用于接收外部的命令并执行，在访问存储单元33之前，控制逻辑单元3都要检查一下刷新逻辑单元9返回的信号，如果处于刷新状态，那么就不执行，反之执行。The control logic unit 3 is used to receive and execute external commands. Before accessing the storage unit 33, the control logic unit 3 checks the signal returned by the refresh logic unit 9. If it is in the refresh state, it does not execute it, otherwise it executes.
当进入刷新时间时，如果控制逻辑单元3需要访问存储单元33，刷新逻辑单元9需要判断当前刷新是否能被打断，如果刷新延迟寄存器11与刷新延迟计数器6中的时间差值大于总行数寄存器10与刷新行数计数器8中的行数差值与每行刷新时间的乘积时，则当前刷新可以被打断，控制逻辑单元3开始访问存储单元33，同时刷新延迟计数器6开始计数刷新被延迟的时间。When entering the refresh time, if the control logic unit 3 needs to access the storage unit 33, the refresh logic unit 9 needs to judge whether the current refresh can be interrupted, if the time difference between the refresh delay register 11 and the refresh delay counter 6 is greater than the total number of rows register 10 and the product of the line number difference in the refresh line number counter 8 and the refresh time of each line, then the current refresh can be interrupted, and the control logic unit 3 starts to access the storage unit 33, and the refresh delay counter 6 starts counting and the refresh is delayed time.
刷新周期计数器7始终在计时，如果刷新周期计数器7等于刷新周期寄存器5，表示到了下一个刷新周期，刷新周期计数器5、刷新行数计数器8、刷新延迟计数器6归零，读写标志寄存器12重置。如图5所示，是本发明的刷新方式第一实施例。The refresh cycle counter 7 is always counting. If the refresh cycle counter 7 is equal to the refresh cycle register 5, it means that the next refresh cycle is reached. place. As shown in FIG. 5 , it is the first embodiment of the refresh mode of the present invention.
在本实施例中，每个区块bank都有自己独立的刷新装置，每个区块bank之间的刷新相互独立。每个区块bank都有自己的刷新装置，当一个区块bank在刷新时间内被打断时，不会影响到其他区块bank的刷新。In this embodiment, each block bank has its own independent refreshing device, and the refreshing between each block bank is independent of each other. Each block bank has its own refresh device. When a block bank is interrupted within the refresh time, it will not affect the refresh of other block banks.
如图6所示，是本发明的刷新方式第二实施例。As shown in FIG. 6, it is the second embodiment of the refreshing method of the present invention.
在本实施例中，所有的区块bank分成M个组，每组N个区块bank，每组有一个独立的刷新装置，每个组之间的刷新相互独立。如上图所示，每组都有自己的刷新装置，当一个组在刷新时间内被打断时，不会影响到其他组的刷新。In this embodiment, all block banks are divided into M groups, each group has N block banks, and each group has an independent refreshing device, and the refreshing between each group is independent of each other. As shown in the figure above, each group has its own refresh device. When a group is interrupted within the refresh time, it will not affect the refresh of other groups.
进一步地，在一个DRAM或eDRAM控制器中只有一个刷新装置。Further, there is only one refresh device in a DRAM or eDRAM controller.
进一步地，所有的区块bank共享一个刷新装置，所有的区块bank刷新状态完全相同。Further, all the block banks share a refresh device, and the refresh states of all the block banks are exactly the same.
进一步地，每一个区块bank有自己的刷新装置，每个区块bank的刷新相互独立。Further, each block bank has its own refreshing device, and the refreshing of each block bank is independent of each other.
进一步地，可以将若干个区块bank分为一组，每组区块bank有一个刷新装置。Further, several block banks can be divided into one group, and each group of block banks has a refreshing device.
进一步地，每一组区块bank有自己的刷新装置，每组内的区块bank刷新状态完全相同，组间的刷新相互独立。Furthermore, each group of block banks has its own refresh device, the refresh status of the block banks in each group is exactly the same, and the refresh between groups is independent of each other.
本发明改进刷新的方式使刷新变得更加灵活，可有效的协调读写和刷新之间的冲突，提高了DRAM的吞吐量，从而提高了DRAM的性能，同时记录在可延迟刷新阶段读写过的行地址，被读写过的行可以直接跳过刷新，减少了刷新时间及功耗。The improved refresh method of the present invention makes the refresh more flexible, can effectively coordinate the conflict between reading and writing and refreshing, improves the throughput of DRAM, thereby improving the performance of DRAM, and records the read and write in the delay refresh stage The row address, the row that has been read and written can skip the refresh directly, reducing the refresh time and power consumption.
当然，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明做出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。Of course, the present invention can also have other various embodiments, and those skilled in the art can make various corresponding changes and deformations according to the present invention without departing from the spirit and essence of the present invention. All changes and deformations should belong to the protection scope of the appended claims of the present invention.
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| CN106128499A (en) * | 2016-06-28 | 2016-11-16 | 田彬 | A kind of device refreshed for DRAM or eDRAM and method for refreshing |
| CN106601286A (en) * | 2016-12-20 | 2017-04-26 | 湖南国科微电子股份有限公司 | DDRx SDRAM memory refreshing method and memory controller |
| CN110058793B (en) | 2018-01-19 | 2020-04-28 | 华为技术有限公司 | A refresh processing method, device, system and memory controller |
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| CN111400246B (en) * | 2020-03-26 | 2023-12-19 | 广州酷旅旅行社有限公司 | Asynchronous file import method, device, computer equipment and storage medium |
| CN114388025B (en) | 2021-12-30 | 2022-09-13 | 中科声龙科技发展（北京）有限公司 | Dynamic random access memory refreshing circuit, refreshing method and workload proving chip |
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