CN106847828A - Low temperature polycrystalline silicon array base palte and its manufacture method - Google Patents

Abstract

The present invention provides a kind of low temperature polycrystalline silicon array base-plate structure, including：Substrate；Active layer on the substrate；In the first grid insulating barrier of the active layer；First grid layer on the first grid insulating barrier, the first grid layer is in the top of active layer；Cover the second grid insulating barrier of the first grid layer；Second grid layer on the second grid insulating barrier, the second grid layer is in the top of first grid layer.The present invention advantageously accounts for that polycrystalline SiTFT threshold voltage of the prior art is uneven to be caused to show uneven defect, and the problem that threshold voltage drifts about during technique or use, while not increasing process complexity.

Description

Low-temperature polysilicon array substrate and manufacturing method thereof

technical field

The invention relates to the technical field of display devices, in particular to a low-temperature polysilicon array substrate and a manufacturing method thereof.

Background technique

The low-temperature polysilicon array substrate has the advantages of high mobility (up to hundreds of times that of amorphous silicon), the size of its thin film transistors can be made small, and the response speed is fast. It is a display panel that has become more and more popular in recent years. Array substrates are increasingly used in high-resolution, high-quality organic electroluminescent displays and liquid crystal display panels. However, the composition of low-temperature polysilicon array substrates is generally more complex, and the process is various, especially because the uniformity of polysilicon prepared by the current mainstream excimer laser crystallization method is difficult to maintain, and the uniformity of its threshold voltage is poor. It is used in display devices. Display defects are easy to form during driving. In addition, due to the complexity of the process, pollution and interface treatment during the process may easily cause the threshold voltage of the polysilicon thin film transistor device to shift, resulting in display drive difficulties or display defects.

Since the threshold voltage of the polysilicon thin film transistor has an important influence on the display driving performance of the display device, various methods are used in the prior art to try to solve the problem of poor uniformity of the threshold voltage of the polysilicon thin film transistor. However, these methods require expensive and highly demanding equipment, and these methods themselves add new processes and increase the complexity of the preparation of low-temperature polysilicon array substrates. There is no effective means in the prior art to solve the problem of non-uniform threshold voltage of polysilicon thin film transistors in the prior art without increasing the complexity of the process.

Contents of the invention

In view of the above-mentioned problems in the prior art, the object of the present invention is to provide a low-temperature polysilicon array substrate and its manufacturing method, which can solve the problem of non-uniform threshold voltage of polysilicon thin film transistors in the prior art without increasing process complexity.

To achieve the above object, the present invention adopts the following technical solutions.

The present invention provides a low-temperature polysilicon array substrate structure, comprising: a substrate; an active layer on the substrate; a first gate insulating layer on the active layer; a first gate layer on the On the first gate insulating layer, the first gate layer is above the active layer; the second gate insulating layer covers the first gate layer; the second gate layer is on the first gate layer On the second gate insulating layer, the second gate layer is on the first gate layer.

The low temperature polysilicon array substrate structure further includes a first capacitive electrode layer disposed on the first gate insulating layer and covered by the second gate insulating layer, and a second capacitor electrode layer disposed on the second gate insulating layer. Capacitive electrode layer, the first capacitive electrode layer is on the side away from the active layer above the substrate, and the second capacitive electrode layer is above the first capacitive electrode layer

Wherein, the thickness of the first gate insulating layer is 10 nm to 40 nm.

Wherein, the first gate layer and the second gate layer are single-layer, two-layer or more than two-layer structures.

Wherein, the thickness of the first gate layer and the second gate layer is 100nm to 500nm

The present invention also provides a method for manufacturing a low-temperature polysilicon array substrate structure, comprising: forming an active layer on the substrate; forming a first gate insulating layer covering the active layer on the substrate; A first gate electrode layer and a first capacitor electrode layer are formed on the gate insulating layer, the first gate layer is formed above the active layer, and the first capacitor electrode layer is formed on the substrate away from the One side of the active layer; forming a second gate insulating layer covering the first gate layer and the first capacitor electrode layer; forming a second gate layer and a second capacitor on the second gate insulating layer An electrode layer, wherein the second gate layer is formed above the first gate layer, and the second capacitive electrode layer is above the first capacitive electrode layer.

Wherein, the forming the first gate electrode layer and the first capacitor electrode layer on the first gate insulating layer includes: forming a metal layer on the first gate insulating layer, patterning the metal layer, and simultaneously forming the The first gate electrode layer and the first capacitor electrode layer.

Wherein, the forming the second gate layer and the second capacitor electrode layer on the second gate insulating layer includes: forming a metal layer on the second gate insulating layer, patterning the metal layer, and simultaneously forming the The second gate electrode layer and the second capacitor electrode layer.

Wherein, the thickness of the first gate insulating layer is 10 nm to 40 nm.

Wherein, the first gate layer and the second gate layer are single-layer, two-layer or more than two-layer structures, and the thickness of the first gate layer and the second gate layer is 100 nm to 500 nm.

The low-temperature polysilicon array substrate and its manufacturing method provided by the present invention adopt a double-layer gate structure. By applying a high voltage to the upper gate and the drain at the same time, the electrons in the channel form a thermal electron effect, and are injected into the lower gate to accumulate charges. , thereby adjusting the threshold voltage uniformity of the thin film transistor. This helps to solve the problem of uneven display defects caused by uneven threshold voltage of polysilicon thin film transistors in the prior art, and the threshold voltage drifts during the process or use, resulting in difficult driving of display devices or the occurrence of dot screen defects. At the same time, due to the present invention The dual-layer gate structure and the double-layer gate capacitor structure are formed simultaneously without increasing the complexity of the process.

Description of drawings

FIG. 1 is a schematic structural diagram of a low temperature polysilicon array substrate according to an embodiment of the present invention.

FIG. 2 shows a method for adjusting the threshold voltage of a thin film transistor in a low temperature polysilicon array substrate according to an embodiment of the present invention.

3 to 8 show a flow chart of a process for manufacturing a low-temperature polysilicon array substrate according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

101. Substrate; 102. Active layer; 103. First gate insulating layer; 104. First gate layer; 105. First capacitor electrode layer; 106. Second gate insulating layer; 107. Second gate layer; 108, second capacitor electrode layer; 109, source electrode; 110, drain electrode; 111, charge; 501, 801, metal layer.

detailed description

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, only some structures related to the present invention are shown in the drawings but not all structures.

Embodiment one

This embodiment provides a low-temperature polysilicon array substrate, and FIG. 1 shows the structure of the low-temperature polysilicon array substrate according to an embodiment of the present invention.

As shown in FIG. 1 , the low-temperature polysilicon array substrate according to this embodiment includes: a substrate 101; an active layer 102 disposed on the substrate 101; a first gate insulating layer 103 disposed on the active layer 102, a first insulating The layer 103 covers the active layer 102 and extends on the substrate 101; the first gate layer 104 formed on the first insulating layer 103, the first gate layer 104 is above the active layer 102, on the first insulating layer 103 It also includes a first capacitance electrode layer 105, which is formed on the side of the substrate 101 away from the active layer 102; a second gate insulating layer 106, covering the first gate layer 104 and the first The capacitor electrode layer 105 extends on the first gate insulating layer 103; the second gate layer 107 and the second capacitor electrode layer 108 are on the second gate insulating layer 106, and the second gate layer 107 is on the second Above a gate layer 104 , the second capacitive electrode layer 108 is above the first capacitive electrode layer 105 .

For the low-temperature polysilicon array substrate according to this embodiment, the substrate 101 can be a transparent substrate such as pre-cleaned glass, and the substrate 101 can also include a buffer layer formed by stacking silicon oxide, silicon nitride or both (not shown in the figure). out) to prevent metal ion impurities in the transparent substrate from diffusing into the active layer and affecting the working characteristics of the thin film transistor. The substrate 101 may also be a flexible substrate made of an organic thin film. The thickness of the active layer 102 is between 10 nm and 300 nm, preferably between 50 nm and 100 nm. The first gate insulating layer 102 and the second gate insulating layer 106 may be a single layer of silicon oxide, silicon nitride or a stack of the two, with a thickness between 10 nm and 200 nm. For the first gate insulating layer, in order to facilitate injection of hot electrons, the thickness of the first insulating layer is set between 10 nm and 40 nm. The thickness of the second gate insulating layer 106 can be set according to the actual requirement of the storage capacitor. The first gate layer 104, the second gate layer 107, the first capacitive electrode layer 105 and the second capacitive electrode layer 108 can be a single-layer, two-layer or more than two-layer structure, made of metal, metal alloy such as molybdenum, aluminum , molybdenum and tungsten, etc., with a thickness between 100nm and 500nm, preferably between 150nm and 400nm.

The low temperature polysilicon array substrate according to this embodiment has a double gate structure, which can adjust the uniformity of the threshold voltage of the thin film transistor. FIG. 2 shows a method for adjusting the threshold voltage of a thin film transistor in a low temperature polysilicon array substrate according to an embodiment of the present invention. The method for adjusting the threshold voltage of the thin film transistor will be described in detail below with reference to FIG. 2 .

As shown in FIG. 2 , two gate layers, ie, a first gate layer 104 and a second gate layer 107 , are formed in the left thin film transistor region in FIG. 2 . Through channel hot electron injection (channel hot electron injection is a commonly used "write" operation method in flash memory) method to form charge accumulation in the first gate layer 104, thereby changing the second gate layer 107 to be applied The magnitude of the voltage, and then change the threshold voltage of the thin film transistor device. Its working principle is that when a high voltage is applied to the drain 110 and the second gate layer 107 at the same time, such as greater than 10V (take the N-type thin film transistor as an example, and the P-type thin film transistor is less than -10V), the electrons in the channel 111 obtains high energy under the acceleration of the transverse electric field between the source 109 and the drain 110, and impacts ionization near the drain to generate high-energy electrons. Because the electric field of the first gate layer 104 also applies a high voltage, it can attract electrons, so that some electrons jump over the barrier of the first gate insulating layer 103 (silicon oxide is 3.2 electron volts), and enter the first gate. Layer 104. Since the upper and lower sides of the first gate layer 104 are covered by an insulating layer, incoming electrons will not be lost, thereby forming an additional electric field on the channel, which can cooperate with the second gate layer 107 to adjust the threshold voltage of the thin film transistor.

Therefore, the low-temperature polysilicon array substrate according to this embodiment has a double-gate structure, which can adjust the uniformity of the threshold voltage of the thin film transistor, which is beneficial to solve the defect of display unevenness caused by the uneven threshold voltage of the polysilicon thin film transistor in the prior art, and the threshold The voltage drifts during the process or use, causing difficulty in driving the display device or problems with dot screen defects.

Embodiment two

This embodiment provides a method for manufacturing a low-temperature polysilicon array substrate, which is used to manufacture the low-temperature polysilicon array substrate described in Embodiment 1. 3 to 8 show a flow chart of a process for manufacturing a low-temperature polysilicon array substrate according to an embodiment of the present invention.

As shown in FIGS. 3 to 8 , the method for manufacturing a polysilicon array substrate according to this embodiment includes the following steps.

As shown in Figure 3, first, in step S1, a transparent substrate such as glass that has been cleaned in advance is provided as the substrate 101, and a buffer layer including silicon oxide, silicon nitride, or a stack of the two can be formed on the substrate 101, so as to Prevent metal ion impurities in the transparent substrate from diffusing into the active layer to affect the working characteristics of the TFT. Or a flexible substrate made of organic thin films. The active layer 102 is deposited on the substrate 101 by PECVD, LPCVD, etc. at a temperature of 600°C. The thickness of the deposited active layer 102 is between 10nm and 300nm, preferably between 50nm and 100nm. The ion implantation process used to form the active layer 102 may be ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid-state diffusion implantation. The preferred solution of this embodiment adopts the mainstream ion cloud implantation method, which can be implanted with a mixed gas containing boron such as B2H6/H2 or phosphorus such as PH3/H2 according to the design requirements. The ion implantation energy can be 10-200keV, and the preferred energy is between 40～100keV. The injection dose can be within the range of 1x1011-1x1020 atoms/cm ³ , and the recommended dose is 1x1014-1x1018 atoms/cm ³ . It should be noted that in the specific process, processes such as dehydrogenation by heat treatment, deposition-induced metal, crystallization by heat treatment, crystallization by excimer laser irradiation, and activation of doped impurities need to be added according to the situation, but the present invention will also play a beneficial role. Effect

As shown in Figure 4, then, in step S2, the first gate insulating layer 103 is deposited on the substrate 101 by methods such as PECVD, LPCVD, APCVD or ECR-CVD, and the first gate insulating layer 103 can be a single layer The thickness of silicon oxide, silicon nitride or a stack of the two is set between 10nm and 200nm to facilitate injection of hot electrons. The first gate insulating layer 103 covers the active layer 102 and extends on the substrate 101 .

As shown in FIG. 5, then, in step S3, a metal layer 501 is deposited on the first gate insulating layer 103. The metal layer 501 can be a single-layer, two-layer or more than two-layer structure, and is made of metal, metal alloy such as Composed of molybdenum, aluminum, molybdenum and tungsten, etc., the thickness is between 100nm and 500nm. The metal layer 501 covers the first gate insulating layer 103 .

As shown in FIG. 6 , next, in step S4 , the metal layer 501 is patterned, and the first gate layer 104 and the first capacitor electrode layer 105 are formed at the same time. The first gate layer 104 and the first capacitor electrode layer 105 are formed at different positions above the first gate insulating layer 103, the first gate layer 104 is formed above the active layer 102, and the first capacitor electrode The layer 105 is formed on the side of the first gate insulating layer 103 away from the active layer 102 . .

As shown in FIG. 7, then, in step S5, a second gate insulating layer 106 covering the first gate layer 104 and the first capacitive electrode layer 105 is formed, and the formation process of the second gate insulating layer 106 is the same as that of the first gate insulating layer 106. The same as that of the gate insulating layer 103 , the thickness of the second gate insulating layer 106 can be set according to the design requirements of the storage capacitor.

As shown in FIG. 8, then, in step S6, a metal layer 801 covering the second gate insulating layer 106 is formed. The metal layer 801 can be a single-layer, two-layer or more than two-layer structure, and is made of metal, metal alloy such as Composed of molybdenum, aluminum, molybdenum and tungsten, etc., the thickness is between 100nm and 500nm. The metal layer 801 covers the second gate insulating layer 106 .

Next, in step S7 , the metal layer 801 is patterned, and the second gate layer 107 and the second capacitance electrode layer 108 are formed at the same time to obtain the structure of the low temperature polysilicon array substrate as shown in FIG. 1 . The second gate layer 107 and the second capacitive electrode layer 108 are formed at different positions on the second gate insulating layer 106, and the second gate layer 107 is formed on the first gate layer 107, which is the same as the first gate layer 107. A gate layer 104 together forms a double gate structure of the polysilicon array substrate. The second capacitive electrode layer 108 is formed on the first capacitive electrode layer 105 , and the first capacitive electrode layer 105 , the second capacitive electrode layer 108 and the second gate insulating layer 106 together form a storage capacitive structure of the polysilicon array substrate.

Therefore, according to the manufacturing method of the low-temperature polysilicon array substrate of this embodiment, the first gate layer 104 and the second capacitive electrode layer 105 are formed simultaneously by the same process, and the second gate layer 107 and the second capacitive electrode layer 108 are also formed using the same process. The same process is formed at the same time, so that the double gate structure of the low-temperature polysilicon array substrate is formed without adding new process steps, without increasing the complexity of the process, and realizing the adjustment of the threshold voltage of the thin film transistor at low cost.

The low-temperature polysilicon array substrate according to the present invention has a double-gate structure, and the threshold voltage of the thin-film transistor is adjusted by applying a high voltage to the source and the drain at the same time to store charges in the gate layer, thereby adjusting the uniformity of the threshold voltage of the thin-film transistor, which is beneficial The present invention solves the problem of uneven display defects caused by uneven threshold voltage of polysilicon thin film transistors in the prior art, and threshold voltage drifts during process or use, resulting in difficult driving of display devices or dot screen defects. Moreover, the manufacturing method of the low-temperature polysilicon array substrate of the present invention can form the double gate structure of the low-temperature polysilicon array substrate without increasing the process, without increasing the complexity of the process, and reducing the cost.

Note that the above is only the preferred embodiment of the present invention and the principle of the applied technology. It should be understood by those skilled in the art that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention, and the present invention The scope is determined by the appended claims.

Claims (10)

1. A low-temperature polysilicon array substrate structure, comprising: Substrate; an active layer on the substrate; a first gate insulating layer on the active layer; a first gate layer, on the first gate insulating layer, the first gate layer is on the active layer; a second gate insulating layer covering the first gate layer; The second gate layer is on the second gate insulating layer, and the second gate layer is on the first gate layer. 2. The low-temperature polysilicon array substrate structure according to claim 1, further comprising a first capacitive electrode layer disposed on the first gate insulating layer and covered by the second gate insulating layer and disposed on the first gate insulating layer. The second capacitive electrode layer on the second gate insulating layer, the first capacitive electrode layer is on the side away from the active layer above the substrate, and the second capacitive electrode layer is above the first capacitive electrode layer. 3. The low temperature polysilicon array substrate structure according to claim 1 or 2, wherein the thickness of the first gate insulating layer is 10 nm to 40 nm. 4. The low-temperature polysilicon array substrate structure according to claim 1 or 2, wherein the first gate layer and the second gate layer are single-layer, two-layer or more than two-layer structures. 5. The low temperature polysilicon array substrate structure according to claim 4, wherein the thickness of the first gate layer and the second gate layer is 100 nm to 500 nm. 6. A method for manufacturing a low-temperature polysilicon array substrate structure, comprising: forming an active layer on the substrate; forming a first gate insulating layer covering the active layer on the substrate; A first gate electrode layer and a first capacitor electrode layer are formed on the first gate insulating layer, the first gate layer is formed above the active layer, and the first capacitor electrode layer is formed on the substrate on the side away from the active layer; forming a second gate insulating layer covering the first gate layer and the first capacitor electrode layer; A second gate layer and a second capacitive electrode layer are formed on the second gate insulating layer, wherein the second gate layer is formed above the first gate layer, and the second capacitive electrode layer is formed on the above the first capacitive electrode layer. 7. The method for manufacturing a low-temperature polysilicon array substrate structure according to claim 6, wherein said forming a first gate electrode layer and a first capacitance electrode layer on the first gate insulating layer comprises: A metal layer is formed on the insulating layer, the metal layer is patterned, and the first gate electrode layer and the first capacitor electrode layer are formed at the same time. 8. The method for manufacturing a low-temperature polysilicon array substrate structure according to claim 6, wherein said forming a second gate layer and a second capacitor electrode layer on the second gate insulating layer comprises: A metal layer is formed on the insulating layer, the metal layer is patterned, and the second gate electrode layer and the second capacitance electrode layer are formed at the same time. 9. The manufacturing method of the low-temperature polysilicon array substrate structure according to claim 6, wherein the thickness of the first gate insulating layer is 10 nm to 40 nm. 10. The manufacturing method of the low-temperature polysilicon array substrate structure according to claim 6, wherein the first gate layer and the second gate layer are single-layer, two-layer or more than two-layer structures, and the first gate layer and the second gate layer have a thickness of 100 nm to 500 nm.