CN106817136A - A kind of method for realizing orthogonal signalling treatment, device and receiver - Google Patents
A kind of method for realizing orthogonal signalling treatment, device and receiver Download PDFInfo
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
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Abstract
A kind of method for realizing orthogonal signalling treatment, device and receiver, including：Orthogonal and with phase low-converter receives the rf modulated signal after enhanced processing respectively, and the local oscillation signal according to the fixation provided by frequency synthesizer carries out down-converted, obtains intermediate-freuqncy signal；The intermediate-freuqncy signal of each branch road will be obtained after pulse control circuit carries out phasing, signal band stray suppression is carried out by the intermediate-frequency filter of correspondence branch road respectively；The intermediate-freuqncy signal suppressed to completing band stray in each branch road is exported to analog-digital converter after being amplified by corresponding variable gain amplifier respectively；The data signal that two each branch road analog-to-digital conversions are obtained is exported to baseband chip as orthogonal signalling carries out signal transacting.The embodiment of the present invention realizes phasing by the pulse control circuit being connected with low-converter, on the basis of without extra power consumption, simplifies the treatment of orthogonal signalling.
Description
Technical Field
The present disclosure relates to, but not limited to, wireless communication technologies, and more particularly, to a method, an apparatus, and a receiver for performing orthogonal signal processing.
Background
And the receiver is mainly used for receiving the electromagnetic waves and processing the received electromagnetic waves to obtain information required for data analysis. The receiver comprises an antenna, a radio frequency front end, a baseband processor and the like; wherein the performance of the rf front-end is directly related to the performance of the whole receiver. The rf front-end of a receiver typically includes the following processes: the rf modulated signal is received by an antenna (not shown) into the signal path through an rf input port; filtering by an off-chip surface acoustic wave filter, performing first-stage amplification by an on-chip Low Noise Amplifier (LNA), and then realizing a signal with frequency down-conversion to an intermediate frequency or a zero intermediate frequency by a mixer; filtering useless or interference signals by the intermediate frequency or zero intermediate frequency signal after frequency conversion through an on-chip filter; finally, the signal is amplified by the automatic gain control amplifier and then converted into a digital signal which can be directly utilized by a digital baseband through an analog-to-digital converter. The signals are mainly analog signals. Due to the advantages of simple structure, easy implementation, high applicability, low power consumption and the like, the zero intermediate frequency or low intermediate frequency receiver becomes the mainstream of the market.
In order to solve the problem of amplitude and phase imbalance, the receiver with zero intermediate frequency or low intermediate frequency generally obtains the amplitude difference of orthogonal signals in the aspect of digital baseband through complex digital signal processing and then feeds the amplitude difference back to the radio frequency front end for amplitude adjustment; after amplitude adjustment is completed, the digital baseband is switched to the phase processing of the orthogonal signal, and after an error is obtained, the error is fed back to the radio frequency front end to carry out phase adjustment. Fig. 1 is a block diagram of a receiver in the related art, and the receiver is a zero-if or low-if wireless receiver as shown in fig. 1. The rf modulated signal is received into the receiver through an rf input port via an antenna (not shown); amplifying a received radio frequency modulation signal by a Low Noise Amplifier (LNA) at the front end; in order to filter out adjacent communication interference signals, amplified radio frequency modulation signals need to be output to the outside of a chip, pass through an off-chip acoustic filter (SAW FILTER), then are connected back to a radio frequency preamplifier (RFA) in the chip for further amplification, and are divided into an orthogonal (Q) branch and an in-phase (I) branch for respective processing, wherein in the orthogonal branch, intermediate frequency filtering is obtained through processing of a down converter (Mixer Q) of the orthogonal branch; an orthogonal branch intermediate frequency Filter (IF Filter) performs signal selection and filtering on the intermediate frequency signals obtained by processing (the intermediate frequency signals needing to be demodulated in the bandwidth are selected to pass through, and other signals or noises outside the bandwidth are filtered); after the intermediate frequency signal which is subjected to signal selection and filtering is amplified by a Variable Gain Amplifier (VGA) of the orthogonal branch circuit, a signal meeting the signal strength requirement is provided for an analog-to-digital converter (ADC), and the intermediate frequency signal is converted into a digital signal; in the same-phase branch, intermediate frequency filtering is obtained through processing of a down converter (Mixer I) of the same-phase branch; an in-phase branch intermediate frequency Filter (IF Filter) performs signal selection and filtering on the intermediate frequency signals obtained by processing (selects the intermediate frequency signals needing to be demodulated in the bandwidth to pass through, and filters other signals or noises outside the bandwidth); after the intermediate frequency signal which is selected and filtered is amplified by a Variable Gain Amplifier (VGA) of the in-phase branch, the signal which meets the signal strength requirement is provided for an analog-to-digital converter (ADC), so that the intermediate frequency signal is converted into a digital signal; and taking the digital signals obtained by the orthogonal branch and the in-phase branch as orthogonal signals, and carrying out signal processing through a digital baseband. When the signal processing of the digital baseband is carried out, the amplitude and phase calibration of the orthogonal signal is realized by the Digital Signal Processing (DSP) to realize the feedback control; the digital signals output by the analog-to-digital converters of the orthogonal branch and the homodromous branch are output to a DSP (digital signal processor) for complex digital signal processing, and constant VGA output amplitude is controlled to the analog-to-digital converter by feeding back the digital signals to a gain control voltage end of a Variable Gain Amplifier (VGA); meanwhile, the digital signal processor also detects the phase difference of the orthogonal signal output by the ADC, and the phase difference of the orthogonal signal of the frequency synthesizer (frequency synthesizer) is controlled by a pulse controller (phase controller); the above process may eventually converge to the desired quadrature signal over several iterations.
In the above scheme, if the receiver is designed with digital baseband processing, the orthogonal signal can be processed by the DSP; if the receiver is not designed with digital baseband processing (a pure radio frequency circuit), a DSP (digital signal processor) needs to be designed at the radio frequency front end when orthogonal signal processing is carried out, the orthogonal signal processing is a dynamic processing process, the DSP design is complex, and extra power consumption is increased; in addition, the convergence of the algorithm needs to be considered during the orthogonal signal processing, and the design difficulty of the DSP is further increased. Therefore, the use of the circuit structure of the receiver in the related art is greatly limited when the receiver is not designed for digital baseband processing.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the invention provides a method, a device and a receiver for realizing orthogonal signal processing, which can simplify the processing process of orthogonal signals.
The embodiment of the invention provides a method for realizing orthogonal signal processing, which comprises the following steps:
the down converters of the orthogonal branch and the in-phase branch respectively receive radio frequency modulation signals amplified by the radio frequency amplifier and perform down conversion processing according to fixed local oscillation signals provided by the frequency synthesizer to obtain intermediate frequency signals;
carrying out phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch through a preset pulse control circuit;
carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the orthogonal branch after the phase correction is finished through an intermediate frequency filter of the orthogonal branch; carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished through an intermediate frequency filter of the in-phase branch;
the intermediate frequency signal which is subjected to the out-of-band spurious suppression in the orthogonal branch is amplified by a Variable Gain Amplifier (VGA) of the orthogonal branch and then output to an analog-to-digital converter; the intermediate frequency signal with the out-of-band spurious suppression in the in-phase branch is amplified by the VGA of the in-phase branch and then output to the analog-to-digital converter;
the quadrature branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal and outputs the digital signal to a baseband chip and a digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing; the in-phase branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the in-phase branch into a digital signal, and outputs the digital signal to the baseband chip and the digital signal obtained by the conversion of the quadrature branch analog-to-digital converter to be used as a quadrature signal for signal processing.
Optionally, the pulse control circuit includes:
the gilbert cells of the quadrature branch and the gilbert cells of the in-phase branch.
Optionally, the positive output end and the negative output end of the down converter of the quadrature branch are respectively connected to the in-phase positive input end and the in-phase negative input end of the gilbert cell of the quadrature branch, and the in-phase negative input end and the in-phase positive input end of the gilbert cell of the in-phase branch; the positive output end and the negative output end of the Gilbert unit of the orthogonal branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the orthogonal branch;
the positive output end and the negative output end of the down converter of the in-phase branch are respectively connected to the inverting positive input end and the inverting negative input end of the Gilbert unit of the quadrature branch, and the inverting positive input end and the inverting negative input end of the Gilbert unit of the in-phase branch; and the positive output end and the negative output end of the Gilbert unit of the in-phase branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the in-phase branch.
On the other hand, an apparatus for implementing orthogonal signal processing according to an embodiment of the present invention includes: the frequency synthesizer, a down converter of the orthogonal branch, a down converter of the in-phase branch, a pulse control circuit, an intermediate frequency filter of the orthogonal branch, an intermediate frequency filter of the in-phase branch, an analog-to-digital converter of the orthogonal branch and an analog-to-digital converter of the in-phase branch; wherein,
the frequency synthesizer is used for providing fixed local oscillator signals for the down converter of the orthogonal branch and the down converter of the in-phase branch;
the down-converter of the quadrature branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an orthogonal branch, and sending the intermediate frequency signal to a pulse control circuit;
the down-converter of the in-phase branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an in-phase branch, and sending the intermediate frequency signal to a pulse control circuit;
the pulse control circuit is used for carrying out phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch;
the intermediate frequency filter of the orthogonal branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the orthogonal branch after the phase correction is finished;
the intermediate frequency filter of the in-phase branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished;
the variable gain amplifier VGA of the orthogonal branch is used for amplifying the intermediate frequency signal which finishes the out-of-band spurious suppression in the orthogonal branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the variable gain amplifier of the in-phase branch is used for amplifying the intermediate frequency signal which is subjected to out-of-band spurious suppression in the in-phase branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the quadrature branch analog-to-digital converter is used for converting the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal and outputting the digital signal to the baseband chip and the digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing;
the in-phase branch analog-to-digital converter is used for converting the intermediate-frequency signal amplified by the VGA in the in-phase branch into a digital signal and outputting the digital signal to the baseband chip to be used as an orthogonal signal for signal processing, wherein the digital signal is obtained by conversion of the baseband chip and the orthogonal branch analog-to-digital converter.
Optionally, the pulse control circuit includes:
the gilbert cells of the quadrature branch and the gilbert cells of the in-phase branch.
Optionally, the positive output end and the negative output end of the down converter of the quadrature branch are respectively connected to the in-phase positive input end and the in-phase negative input end of the gilbert cell of the quadrature branch, and the in-phase negative input end and the in-phase positive input end of the gilbert cell of the in-phase branch; the positive output end and the negative output end of the Gilbert unit of the orthogonal branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the orthogonal branch;
the positive output end and the negative output end of the down converter of the in-phase branch are respectively connected to the inverting positive input end and the inverting negative input end of the Gilbert unit of the quadrature branch, and the inverting positive input end and the inverting negative input end of the Gilbert unit of the in-phase branch; and the positive output end and the negative output end of the Gilbert unit of the in-phase branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the in-phase branch.
In still another aspect, an embodiment of the present invention further provides a receiver, including the above apparatus.
Compared with the related art, the technical scheme of the application comprises the following steps: the down converters of the orthogonal branch and the in-phase branch respectively receive radio frequency modulation signals amplified by the radio frequency amplifier and perform down conversion processing according to fixed local oscillation signals provided by the frequency synthesizer to obtain intermediate frequency signals; carrying out phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch through a preset pulse control circuit; carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the orthogonal branch after the phase correction is finished through an intermediate frequency filter of the orthogonal branch; carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished through an intermediate frequency filter of the in-phase branch; the intermediate frequency signal which is subjected to the out-of-band spurious suppression in the orthogonal branch is amplified by a Variable Gain Amplifier (VGA) of the orthogonal branch and then output to an analog-to-digital converter; the intermediate frequency signal with the out-of-band spurious suppression in the in-phase branch is amplified by the VGA of the in-phase branch and then output to the analog-to-digital converter; the quadrature branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal and outputs the digital signal to a baseband chip and a digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing; the in-phase branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the in-phase branch into a digital signal, and outputs the digital signal to the baseband chip and the digital signal obtained by the conversion of the quadrature branch analog-to-digital converter to be used as a quadrature signal for signal processing. The embodiment of the invention realizes phase correction through the pulse control circuit connected with the down converter, and simplifies the processing of orthogonal signals on the basis of no need of extra power consumption.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.
Fig. 1 is a block diagram of a receiver in the related art;
FIG. 2 is a flow chart of a method for implementing orthogonal signal processing according to an embodiment of the present invention;
FIG. 3 is a block diagram of a Gilbert cell according to an embodiment of the present invention;
fig. 4 is a block diagram of an apparatus for implementing quadrature signal processing according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
The steps illustrated in the flow charts of the figures may be performed in a computer system such as a set of computer-executable instructions. Also, while a logical order is shown in the flow diagrams, in some cases, the steps shown or described may be performed in an order different than here.
Fig. 2 is a flowchart of a method for implementing orthogonal signal processing according to an embodiment of the present invention, as shown in fig. 2, including:
200, respectively receiving radio frequency modulation signals amplified by a radio frequency amplifier by down converters of an orthogonal branch and an in-phase branch, and performing down conversion processing according to fixed local oscillation signals provided by a frequency synthesizer to obtain intermediate frequency signals;
it should be noted that, in the frequency synthesizer according to the embodiment of the present invention, only a fixed local oscillation signal needs to be provided, and the local oscillation signal may be determined by a person skilled in the art according to an analysis.
In addition, in the embodiment of the present invention, before amplifying the rf modulation signal, the rf modulation signal is received by an antenna (not shown), and then received into the receiver through the rf input port; amplifying a received radio frequency modulation signal by a Low Noise Amplifier (LNA) at the front end; to filter out the proximity communication interference signals, the amplified RF modulated signal needs to be output off-chip, passed through an off-chip acoustic filter (SAW FILTER), and then back to an on-chip RF preamplifier (RFA).
Step 201, performing phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch through a preset pulse control circuit;
optionally, the pulse control circuit according to an embodiment of the present invention includes:
the gilbert cells of the quadrature branch and the gilbert cells of the in-phase branch.
It should be noted that the gilbert cell is a circuit structure existing in the related art, and its main structure and implementation principle are not described in detail in the embodiments of the present invention.
Optionally, in the circuit of the gilbert cell according to the embodiment of the present invention, a connection relationship between the gilbert cell and the down converter and the intermediate frequency filter is as follows:
the positive output end and the negative output end of the down converter of the orthogonal branch are respectively connected to the in-phase positive input end and the in-phase negative input end of the Gilbert unit of the orthogonal branch, and the in-phase negative input end and the in-phase positive input end of the Gilbert unit of the in-phase branch; the positive output end and the negative output end of the Gilbert unit of the orthogonal branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the orthogonal branch;
the positive output end and the negative output end of the down converter of the in-phase branch are respectively connected to the inverting positive input end and the inverting negative input end of the Gilbert unit of the quadrature branch, and the inverting positive input end and the inverting negative input end of the Gilbert unit of the in-phase branch; and the positive output end and the negative output end of the Gilbert unit of the in-phase branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the in-phase branch.
Step 202, performing signal out-of-band spurious suppression on the intermediate frequency signal of the quadrature branch after the phase correction is completed through an intermediate frequency filter of the quadrature branch; carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished through an intermediate frequency filter of the in-phase branch;
step 203, the intermediate frequency signal with the out-of-band spurious suppression in the orthogonal branch is amplified by a variable gain amplifier VGA of the orthogonal branch and then output to an analog-to-digital converter; the intermediate frequency signal with the out-of-band spurious suppression in the in-phase branch is amplified by a Variable Gain Amplifier (VGA) of the in-phase branch and then output to an analog-to-digital converter;
step 204, the quadrature branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal, and outputs the digital signal to a baseband chip and a digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing; the in-phase branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the in-phase branch into a digital signal, and outputs the digital signal to the baseband chip and the digital signal obtained by the conversion of the quadrature branch analog-to-digital converter to be used as a quadrature signal for signal processing.
In the embodiment of the present invention, after the phase correction is implemented by the pulse control circuit, repeated correction is not required to be performed many times, and the problem of convergence of the phase correction is not required to be considered.
Fig. 3 is a block diagram of a gilbert cell according to an embodiment of the present invention, where as shown in fig. 3, the gilbert cell includes an in-phase positive input terminal, an in-phase negative input terminal, an anti-phase positive input terminal, and an anti-phase negative input terminal connected to a down converter; and also includes corresponding positive and negative output terminals.
The gilbert cell is determined according to the requirements of system power consumption and linearity, and table 1 is parameter information of an optional gilbert cell device and width-to-length ratio according to an embodiment of the present invention, and those skilled in the art can design the gilbert cell by referring to the relevant parameters.
| Device with a metal layer | Width to length ratio |
| Tail current NMOS device | 48um/0.8um |
| Input NMOS device | 8um/0.2um |
| Load PMOS device | 16um/0.4um |
TABLE 1
For convenience of presentation and understanding, in the orthogonal branch, INP1 is a signal input from the positive output terminal of the down-converter in the orthogonal branch to the in-phase positive input terminal of the gilbert cell in the orthogonal branch, and INN1 is a signal input from the negative output terminal of the down-converter in the orthogonal branch to the in-phase negative input terminal of the gilbert cell in the orthogonal branch; QNP1 is the signal input from the positive output end of the down converter of the orthogonal branch to the reverse-phase positive input end of the gilbert cell of the in-phase branch, and QNN1 is the signal input from the reverse-phase negative input end of the gilbert cell of the in-phase branch of the negative output end of the down converter of the orthogonal branch; the signal output by the positive output end of the corresponding gilbert cell of the orthogonal branch is VOUTN1, and the signal output by the negative output end of the gilbert cell of the orthogonal branch is VOUTP 1; where a1 represents the signal input amplitude and Δ represents the phase difference of the quadrature signals; the circuit gain of the gilbert cell is AV 1;
suppose that:
INN1＝A1sin(ωt+0)，
INP1＝A1sin(ωt+180)
QNN1＝A1sin(ωt+90+Δ)
QNP1＝A1sin(ωt+270+Δ)
the signal output by the positive output terminal of the gilbert cell of the quadrature branch is:
VOUTN1＝AV1{A1sin(ωt+180)+A1sin(ωt+90+Δ)}
＝AV1*2A1*A1*{sin[(2ωt+270°+Δ)/2]+sin[(90-Δ)/2]}
＝V1*2A1*A1*{sin[(ωt+135°+Δ/2)]+sin(45-Δ/2)}
the signal output by the negative output terminal of the gilbert cell of the quadrature branch is:
VOUTP1＝AV1{A1sin(ωt+0)+A1sin(ωt+270+Δ)}
＝AV1*2A1*A1*{sin[(2ωt+270+Δ)/2]+sin[(-270-Δ)/2]}
＝AV1*2A1*A1*{sin[(ωt+135°+Δ/2)]+sin[(-270-Δ)/2]}
or,
VOUTP1＝AV1{A1sin(ωt+0)+A1sin(ωt+270+Δ)}
＝AV1*2A1*A1*{sin[(2ωt+270+Δ)/2]+sin(-135-Δ/2)}
＝AV1*2A1*A1*{sin[(ωt+135°+Δ/2)]-sin[(45-Δ/2)}
＝-AV1*2A1*A1*{-sin[(ωt+135°+Δ/2)]+sin[(90-Δ)/2]}
＝AV1*2A1*A1*{sin[(ωt-45°+Δ/2)]+sin[(90-Δ)/2]}
for the in-phase branch, INP2 is a signal input from the positive output terminal of the down-converter of the in-phase branch to the inverting positive input terminal of the gilbert cell of the quadrature branch, and INN2 is a signal input from the negative output terminal of the down-converter of the in-phase branch to the inverting negative input terminal of the gilbert cell of the quadrature branch; QNP2 is the signal input from the positive output end of the down converter of the in-phase branch to the reverse-phase positive input end of the gilbert cell of the in-phase branch, and QNN2 is the signal input from the reverse-phase negative input end of the gilbert cell of the negative output end of the down converter of the in-phase branch; the signal output by the positive output end of the corresponding gilbert cell of the in-phase branch is VOUTN2, and the signal output by the negative output end of the gilbert cell of the in-phase branch is VOUTP 2; where a1 represents the signal input amplitude and Δ represents the phase difference of the quadrature signals; the circuit gain of the gilbert cell is AV 2;
suppose that:
INP2＝A1sin(ωt+0)，
INN2＝A1sin(ωt+180)
QNN2＝A1sin(ωt+90+Δ)
QNP2＝A1sin(ωt+180+Δ)
the signal output by the positive output terminal of the gilbert cell of the in-phase branch is:
VOUTN2＝AV2{A1sin(ωt+0)+A1sin(ωt+90+Δ)}
＝AV2*2A1*A1*{sin[(2ωt+90+Δ)/2]+sin[(-90-Δ)/2]}
＝V2*2A1*A1*{sin[(ωt+45°+Δ/2)]+sin[(-90-Δ)/2]}
or,
VOUTN2＝AV2{A1sin(ωt+0)+A1sin(ωt+90+Δ)}
＝AV2*2A1*A1*{sin[(2ωt+90+Δ)/2]+sin(-90-Δ)/2]}
＝V2*2A1*A1*{sin[(ωt+45°+Δ/2)]+sin(-90-Δ)/2]}
the signal output by the negative output end of the gilbert cell of the in-phase branch is as follows:
VOUTP2＝AV2{A1sin(ωt+180)+A1sin(ωt+270+Δ)}
＝AV2*2A1*A1*{sin[(2ωt+450+Δ)/2]+sin[(-90-Δ)/2]}
＝V2*2A1*A1*{sin[(ωt+225°+Δ/2)]+sin[(-90-Δ)/2]}
comparing a signal output by a positive output end of a Gilbert unit of the orthogonal branch circuit with a signal output by a negative output end; the signal output by the positive output end and the signal output by the negative output end of the Gilbert unit of the same-phase branch circuit; the phase imbalance of the orthogonal signal introduced by the radio frequency end can be evenly distributed to two ports which are finally output, the phase imbalance percentage of the orthogonal signal after final down-conversion is reduced in the related technology, and analysis shows that the phase imbalance degree of the embodiment of the invention is less than 1 degree, and the phase imbalance degree in the related technology is in the range of 2-3 degrees;
the digital signal output of the analog-to-digital converters of the in-phase branch and the quadrature branch is used for detecting the output signal intensity of the variable gain amplifiers in the two channels, and the constant VGA output amplitude is controlled by feeding back to a gain control voltage end of the VGA through the variable gain amplifier control circuits of the in-phase branch and the quadrature branch. The amplitude control of the variable gain amplifiers of the in-phase branch and the quadrature branch must be controlled by the variable gain amplifier control circuit respectively, so that the amplitude deviation of the signals input to the analog-to-digital converter is small, the general phase offset is less than 1 degree, and the amplitude offset is less than 0.5 dB. The method provided by the embodiment of the invention has universal applicability as no additional DSP is required to be designed.
Fig. 4 is a block diagram of an apparatus for implementing quadrature signal processing according to an embodiment of the present invention, as shown in fig. 4, including: the frequency synthesizer, a down converter of the orthogonal branch, a down converter of the in-phase branch, a pulse control circuit, an intermediate frequency filter of the orthogonal branch, an intermediate frequency filter of the in-phase branch, an analog-to-digital converter of the orthogonal branch and an analog-to-digital converter of the in-phase branch; wherein,
the frequency synthesizer is used for providing fixed local oscillator signals for the down converter of the orthogonal branch and the down converter of the in-phase branch;
the down-converter of the quadrature branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an orthogonal branch, and sending the intermediate frequency signal to a pulse control circuit;
the down-converter of the in-phase branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an in-phase branch, and sending the intermediate frequency signal to a pulse control circuit;
it should be noted that, in the frequency synthesizer according to the embodiment of the present invention, only a fixed local oscillation signal needs to be provided, and the local oscillation signal may be determined by a person skilled in the art according to an analysis.
The pulse control circuit is used for carrying out phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch;
the intermediate frequency filter of the orthogonal branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the orthogonal branch after the phase correction is finished;
the intermediate frequency filter of the in-phase branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished;
the variable gain amplifier VGA of the orthogonal branch is used for amplifying the intermediate frequency signal which finishes the out-of-band spurious suppression in the orthogonal branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the variable gain amplifier of the in-phase branch is used for amplifying the intermediate frequency signal which is subjected to out-of-band spurious suppression in the in-phase branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the quadrature branch analog-to-digital converter is used for converting the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal and outputting the digital signal to the baseband chip and the digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing;
the in-phase branch analog-to-digital converter is used for converting the intermediate-frequency signal amplified by the VGA in the in-phase branch into a digital signal and outputting the digital signal to the baseband chip to be used as an orthogonal signal for signal processing, wherein the digital signal is obtained by conversion of the baseband chip and the orthogonal branch analog-to-digital converter.
It should be noted that, after the phase correction is realized through the pulse control circuit, the embodiment of the present invention does not need to perform repeated correction for many times, and does not need to consider the convergence problem of the phase correction;
optionally, the pulse control circuit according to an embodiment of the present invention includes:
the gilbert cells of the quadrature branch and the gilbert cells of the in-phase branch.
It should be noted that the gilbert cell is a circuit structure existing in the related art, and its main structure and implementation principle are not described in detail in the embodiments of the present invention.
Alternatively, in the embodiments of the present invention,
the positive output end and the negative output end of the down converter of the orthogonal branch are respectively connected to the in-phase positive input end and the in-phase negative input end of the Gilbert unit of the orthogonal branch, and the in-phase negative input end and the in-phase positive input end of the Gilbert unit of the in-phase branch; the positive output end and the negative output end of the Gilbert unit of the orthogonal branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the orthogonal branch;
the positive output end and the negative output end of the down converter of the in-phase branch are respectively connected to the inverting positive input end and the inverting negative input end of the Gilbert unit of the quadrature branch, and the inverting positive input end and the inverting negative input end of the Gilbert unit of the in-phase branch; and the positive output end and the negative output end of the Gilbert unit of the in-phase branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the in-phase branch.
An embodiment of the present invention further provides a receiver, including: the frequency synthesizer, a down converter of the orthogonal branch, a down converter of the in-phase branch, a pulse control circuit, an intermediate frequency filter of the orthogonal branch, an intermediate frequency filter of the in-phase branch, an analog-to-digital converter of the orthogonal branch and an analog-to-digital converter of the in-phase branch; wherein,
the frequency synthesizer is used for providing fixed local oscillator signals for the down converter of the orthogonal branch and the down converter of the in-phase branch;
the down-converter of the quadrature branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an orthogonal branch, and sending the intermediate frequency signal to a pulse control circuit;
the down-converter of the in-phase branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an in-phase branch, and sending the intermediate frequency signal to a pulse control circuit;
it should be noted that, in the frequency synthesizer according to the embodiment of the present invention, only a fixed local oscillation signal needs to be provided, and the local oscillation signal may be determined by a person skilled in the art according to an analysis.
The pulse control circuit is used for carrying out phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch;
the intermediate frequency filter of the orthogonal branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the orthogonal branch after the phase correction is finished;
the intermediate frequency filter of the in-phase branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished;
the variable gain amplifier VGA of the orthogonal branch is used for amplifying the intermediate frequency signal which finishes the out-of-band spurious suppression in the orthogonal branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the variable gain amplifier of the in-phase branch is used for amplifying the intermediate frequency signal which is subjected to out-of-band spurious suppression in the in-phase branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the quadrature branch analog-to-digital converter is used for converting the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal and outputting the digital signal to the baseband chip and the digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing;
the in-phase branch analog-to-digital converter is used for converting the intermediate-frequency signal amplified by the VGA in the in-phase branch into a digital signal and outputting the digital signal to the baseband chip to be used as an orthogonal signal for signal processing, wherein the digital signal is obtained by conversion of the baseband chip and the orthogonal branch analog-to-digital converter.
It should be noted that, after the phase correction is realized through the pulse control circuit, the embodiment of the present invention does not need to perform repeated correction for many times, and does not need to consider the convergence problem of the phase correction;
optionally, the pulse control circuit according to an embodiment of the present invention includes:
the gilbert cells of the quadrature branch and the gilbert cells of the in-phase branch.
It should be noted that the gilbert cell is a circuit structure existing in the related art, and its main structure and implementation principle are not described in detail in the embodiments of the present invention.
Alternatively, in the embodiments of the present invention,
the positive output end and the negative output end of the down converter of the orthogonal branch are respectively connected to the in-phase positive input end and the in-phase negative input end of the Gilbert unit of the orthogonal branch, and the in-phase negative input end and the in-phase positive input end of the Gilbert unit of the in-phase branch; the positive output end and the negative output end of the Gilbert unit of the orthogonal branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the orthogonal branch;
the positive output end and the negative output end of the down converter of the in-phase branch are respectively connected to the inverting positive input end and the inverting negative input end of the Gilbert unit of the quadrature branch, and the inverting positive input end and the inverting negative input end of the Gilbert unit of the in-phase branch; and the positive output end and the negative output end of the Gilbert unit of the in-phase branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the in-phase branch.
It will be understood by those skilled in the art that all or part of the steps of the above methods may be implemented by a program instructing associated hardware (e.g., a processor) to perform the steps, and the program may be stored in a computer readable storage medium, such as a read only memory, a magnetic or optical disk, and the like. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits. Accordingly, each module/unit in the above embodiments may be implemented in hardware, for example, by an integrated circuit to implement its corresponding function, or in software, for example, by a processor executing a program/instruction stored in a memory to implement its corresponding function. The present invention is not limited to any specific form of combination of hardware and software.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (7)
1. A method for implementing quadrature signal processing, comprising:
the down converters of the orthogonal branch and the in-phase branch respectively receive radio frequency modulation signals amplified by the radio frequency amplifier and perform down conversion processing according to fixed local oscillation signals provided by the frequency synthesizer to obtain intermediate frequency signals;
carrying out phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch through a preset pulse control circuit;
carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the orthogonal branch after the phase correction is finished through an intermediate frequency filter of the orthogonal branch; carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished through an intermediate frequency filter of the in-phase branch;
the intermediate frequency signal which is subjected to the out-of-band spurious suppression in the orthogonal branch is amplified by a Variable Gain Amplifier (VGA) of the orthogonal branch and then output to an analog-to-digital converter; the intermediate frequency signal with the out-of-band spurious suppression in the in-phase branch is amplified by the VGA of the in-phase branch and then output to the analog-to-digital converter;
the quadrature branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal and outputs the digital signal to a baseband chip and a digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing; the in-phase branch analog-to-digital converter converts the intermediate frequency signal amplified by the VGA in the in-phase branch into a digital signal, and outputs the digital signal to the baseband chip and the digital signal obtained by the conversion of the quadrature branch analog-to-digital converter to be used as a quadrature signal for signal processing.
2. The method of claim 1, wherein the pulse control circuit comprises:
the gilbert cells of the quadrature branch and the gilbert cells of the in-phase branch.
3. The method according to claim 1 or 2,
the positive output end and the negative output end of the down converter of the orthogonal branch are respectively connected to the in-phase positive input end and the in-phase negative input end of the Gilbert unit of the orthogonal branch, and the in-phase negative input end and the in-phase positive input end of the Gilbert unit of the in-phase branch; the positive output end and the negative output end of the Gilbert unit of the orthogonal branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the orthogonal branch;
the positive output end and the negative output end of the down converter of the in-phase branch are respectively connected to the inverting positive input end and the inverting negative input end of the Gilbert unit of the quadrature branch, and the inverting positive input end and the inverting negative input end of the Gilbert unit of the in-phase branch; and the positive output end and the negative output end of the Gilbert unit of the in-phase branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the in-phase branch.
4. An apparatus for implementing quadrature signal processing, comprising: the frequency synthesizer, a down converter of the orthogonal branch, a down converter of the in-phase branch, a pulse control circuit, an intermediate frequency filter of the orthogonal branch, an intermediate frequency filter of the in-phase branch, an analog-to-digital converter of the orthogonal branch and an analog-to-digital converter of the in-phase branch; wherein,
the frequency synthesizer is used for providing fixed local oscillator signals for the down converter of the orthogonal branch and the down converter of the in-phase branch;
the down-converter of the quadrature branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an orthogonal branch, and sending the intermediate frequency signal to a pulse control circuit;
the down-converter of the in-phase branch is used for: receiving a radio frequency modulation signal amplified by a radio frequency amplifier, performing down-conversion processing according to a fixed local oscillation signal provided by a frequency synthesizer to obtain an intermediate frequency signal of an in-phase branch, and sending the intermediate frequency signal to a pulse control circuit;
the pulse control circuit is used for carrying out phase correction on the obtained intermediate frequency signals of the orthogonal branch and the in-phase branch;
the intermediate frequency filter of the orthogonal branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the orthogonal branch after the phase correction is finished;
the intermediate frequency filter of the in-phase branch is used for carrying out signal out-of-band spurious suppression on the intermediate frequency signal of the in-phase branch after the phase correction is finished;
the variable gain amplifier VGA of the orthogonal branch is used for amplifying the intermediate frequency signal which finishes the out-of-band spurious suppression in the orthogonal branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the variable gain amplifier of the in-phase branch is used for amplifying the intermediate frequency signal which is subjected to out-of-band spurious suppression in the in-phase branch and outputting the amplified intermediate frequency signal to the analog-to-digital converter;
the quadrature branch analog-to-digital converter is used for converting the intermediate frequency signal amplified by the VGA in the quadrature branch into a digital signal and outputting the digital signal to the baseband chip and the digital signal obtained by the conversion of the in-phase branch analog-to-digital converter to be used as a quadrature signal for signal processing;
the in-phase branch analog-to-digital converter is used for converting the intermediate-frequency signal amplified by the VGA in the in-phase branch into a digital signal and outputting the digital signal to the baseband chip to be used as an orthogonal signal for signal processing, wherein the digital signal is obtained by conversion of the baseband chip and the orthogonal branch analog-to-digital converter.
5. The apparatus of claim 4, wherein the pulse control circuit comprises:
the gilbert cells of the quadrature branch and the gilbert cells of the in-phase branch.
6. The apparatus according to claim 4 or 5,
the positive output end and the negative output end of the down converter of the orthogonal branch are respectively connected to the in-phase positive input end and the in-phase negative input end of the Gilbert unit of the orthogonal branch, and the in-phase negative input end and the in-phase positive input end of the Gilbert unit of the in-phase branch; the positive output end and the negative output end of the Gilbert unit of the orthogonal branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the orthogonal branch;
the positive output end and the negative output end of the down converter of the in-phase branch are respectively connected to the inverting positive input end and the inverting negative input end of the Gilbert unit of the quadrature branch, and the inverting positive input end and the inverting negative input end of the Gilbert unit of the in-phase branch; and the positive output end and the negative output end of the Gilbert unit of the in-phase branch are connected to the positive input end and the negative input end of the intermediate frequency filter of the in-phase branch.
7. A receiver comprising the apparatus of any of claims 4 to 6.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050226352A1 (en) * | 2002-05-07 | 2005-10-13 | Kasperkovitz Wolfdietrich G | Mirror suppression circuit and receiver using such circuit |
| CN101034900A (en) * | 2007-04-29 | 2007-09-12 | 中国民航大学 | Civil aviation ground-air communication self-adaptive disturbance restraining method based on the extraction of the blind signal and its system |
| EP1876703A2 (en) * | 2000-11-03 | 2008-01-09 | QUALCOMM Incorporated | Modulator with low sensitivity to amplitude and phase errors of the carrier signal |
| CN101361336A (en) * | 2006-01-11 | 2009-02-04 | 国际商业机器公司 | Signal Phase Control in Integrated Radio Circuits |
| US20090040393A1 (en) * | 2003-05-20 | 2009-02-12 | Broadcom Corporation | Quadrature correction method for analog television reception using direct-conversion tuners |
| CN101442392A (en) * | 2007-11-20 | 2009-05-27 | 联发科技股份有限公司 | Method, integrated circuit and apparatus for compensating for in-phase and quadrature phase mismatch |
| CN101540618A (en) * | 2009-04-27 | 2009-09-23 | 电子科技大学 | High linearity LINC transmitter |
| CN101562598A (en) * | 2004-01-30 | 2009-10-21 | 日本电气株式会社 | Apparatus and method for adjusting quadrature modulator, and communication apparatus |
| CN102113172A (en) * | 2008-07-18 | 2011-06-29 | 相量解决方案有限公司 | Phased array antenna and method for operating a phased array antenna |
| CN206698207U (en) * | 2017-02-21 | 2017-12-01 | 和芯星通科技(北京)有限公司 | A kind of device and receiver for realizing orthogonal signalling processing |
-
2017
- 2017-02-21 CN CN201710093682.9A patent/CN106817136B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1876703A2 (en) * | 2000-11-03 | 2008-01-09 | QUALCOMM Incorporated | Modulator with low sensitivity to amplitude and phase errors of the carrier signal |
| US20050226352A1 (en) * | 2002-05-07 | 2005-10-13 | Kasperkovitz Wolfdietrich G | Mirror suppression circuit and receiver using such circuit |
| US20090040393A1 (en) * | 2003-05-20 | 2009-02-12 | Broadcom Corporation | Quadrature correction method for analog television reception using direct-conversion tuners |
| CN101562598A (en) * | 2004-01-30 | 2009-10-21 | 日本电气株式会社 | Apparatus and method for adjusting quadrature modulator, and communication apparatus |
| CN101361336A (en) * | 2006-01-11 | 2009-02-04 | 国际商业机器公司 | Signal Phase Control in Integrated Radio Circuits |
| CN101034900A (en) * | 2007-04-29 | 2007-09-12 | 中国民航大学 | Civil aviation ground-air communication self-adaptive disturbance restraining method based on the extraction of the blind signal and its system |
| CN101442392A (en) * | 2007-11-20 | 2009-05-27 | 联发科技股份有限公司 | Method, integrated circuit and apparatus for compensating for in-phase and quadrature phase mismatch |
| CN102113172A (en) * | 2008-07-18 | 2011-06-29 | 相量解决方案有限公司 | Phased array antenna and method for operating a phased array antenna |
| CN101540618A (en) * | 2009-04-27 | 2009-09-23 | 电子科技大学 | High linearity LINC transmitter |
| CN206698207U (en) * | 2017-02-21 | 2017-12-01 | 和芯星通科技(北京)有限公司 | A kind of device and receiver for realizing orthogonal signalling processing |
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