CN106817021B

CN106817021B - Charge pump circuit

Info

Publication number: CN106817021B
Application number: CN201610072649.3A
Authority: CN
Inventors: 阿伦·罗思; 艾瑞克·苏恩
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2015-12-01
Filing date: 2016-02-02
Publication date: 2019-09-13
Anticipated expiration: 2036-02-02
Also published as: CN106817021A

Abstract

The embodiment provides a kind of charge pump circuit, which includes sub-circuit, which is pump stage circuit or output-stage circuit.Sub-circuit includes input, output end, transistor, first capacitor device, first diode device and the second diode component.Transistor has the first source/drain (S/D) coupled with input terminal end, the 2nd end S/D coupled with output end and gate terminal.First capacitor device has the first end coupled with the gate terminal of transistor and is configured to receive the second end of the first driving signal.First diode device has the cathode coupled with the 2nd end S/D of transistor and the anode coupled with the gate terminal of transistor.Second diode component has the cathode coupled with the gate terminal of transistor and the anode coupled with the 2nd end S/D of transistor.

Description

Charge pump circuit

Technical Field

The present invention relates generally to the field of semiconductor technology, and more particularly, to charge pump circuits and methods of operating the same.

Background

The charge pump circuit is a Direct Current (DC) - (DC) converter that generates a voltage of a voltage level higher than that of the input power supply voltage (positive charge pump) or lower than that of the ground reference voltage (negative charge pump). In some applications, the charge pump circuit includes a capacitor as an energy storage element and a transistor as a memory transfer element. In some applications, the transistors turn on or off in response to various control signals, and the control signals are limited by the voltage levels of the input power supply voltage and the ground reference voltage. Also, through the charging and level shifting operations of the voltage level on the capacitor of the charge pump circuit, the respective drain/source terminals of the transistors have voltages shifted up or down. In some applications, the voltage level of each of the up/down shifted voltages exceeds a voltage range between the input power supply voltage and a ground reference voltage.

Disclosure of Invention

To solve the above-mentioned drawbacks in the prior art, according to an aspect of the present invention, there is provided a charge pump circuit including: a sub-circuit that is a pump stage circuit or an output stage circuit, the sub-circuit comprising: an input end; an output end; a transistor having a first source/drain (S/D) terminal coupled to the input terminal, a second S/D terminal coupled to the output terminal, and a gate terminal; a first capacitive device having a first end portion coupled to a gate terminal of the transistor and a second end portion configured to receive a first drive signal; a first diode device having a cathode coupled to the second S/D terminal of the transistor and an anode coupled to the gate terminal of the transistor; and a second diode device having a cathode coupled to a gate terminal of the transistor and an anode coupled to a second S/D terminal of the transistor.

In the charge pump circuit, the sub-circuit is the pump stage circuit, and the sub-circuit further includes: a second capacitive device having a first end coupled with the output and a second end configured to receive a second drive signal.

The charge pump circuit further includes: a control circuit configured to generate a first control signal and a second control signal, wherein the sub-circuit further comprises: a first driver configured to generate the first drive signal based on the first control signal; and a second driver configured to generate the second driving signal based on the second control signal.

In the charge pump circuit, the first driver is configured to switch the first drive signal between a first voltage level corresponding to a logic high value and a reference voltage level corresponding to a logic low value; and the second driver is configured to switch the second drive signal between a second voltage level corresponding to the logic high value and a reference voltage level corresponding to the logic low value, the first voltage level being different from the second voltage level.

In the charge pump circuit, the first diode device has a forward voltage drop; the second diode device has a forward voltage drop; and the forward voltage drop of the first diode device is greater than the forward voltage drop of the second diode device.

In the charge pump circuit, the first diode device includes X transistors connected as diodes, X is a positive integer greater than zero, and when X is greater than 1, the X transistors connected as diodes are connected in series; and the second diode device includes Y transistors connected as a diode, Y being a positive integer greater than zero and less than X, and when Y is greater than 1, the Y transistors connected as a diode are connected in series.

In the charge pump circuit, the first diode device has a forward voltage drop; the transistor has a threshold voltage; and the forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.

In the charge pump circuit, the transistor is an N-type transistor.

According to another aspect of the present invention, there is provided a charge pump circuit including: an input node; an output node; n pump stage circuits, N being a positive integer greater than zero, each of the N pump stage circuits comprising: an input end; and an output end; and an output stage circuit including an input terminal and an output terminal; wherein an input of a first pump stage circuit of the N pump stage circuits is coupled to the input node; an output terminal of an nth pump stage circuit of the N pump stage circuits is coupled with an input terminal of an (N +1) th pump stage circuit of the N pump stage circuits, N is a positive integer and is more than or equal to 1 and less than or equal to (N-1); the output end of the Nth pump stage circuit in the N pump stage circuits is coupled with the input end of the output stage circuit; an output terminal of the output stage circuit is coupled to the output node; and one of the N pump stage circuits further comprises: a transistor having: a first source/drain (S/D) terminal coupled to an input node of one of the N pump stage circuits; a second S/D terminal coupled to an output node of one of the N pump stage circuits; and a gate terminal; a first capacitive device having a first end portion coupled to a gate terminal of the transistor and a second end portion configured to receive a first drive signal; a second capacitive device having a first end coupled to an output node of one of the N pump stage circuits and a second end configured to receive a second drive signal; a first diode device having a cathode coupled to the second S/D terminal of the transistor and an anode coupled to the gate terminal of the transistor; and a second diode device having a cathode coupled to a gate terminal of the transistor and an anode coupled to a second S/D terminal of the transistor.

The charge pump circuit further includes: a control circuit configured to generate a plurality of control signals, wherein one of the N pump stage circuits further comprises: a first driver configured to generate the first drive signal based on a first control signal of the plurality of control signals; and a second driver configured to generate the second driving signal based on a second control signal of the plurality of control signals.

In the charge pump circuit, the first driver includes a first inverter; and the second driver includes a second inverter.

In the charge pump circuit, the transistor is an N-type transistor.

In the charge pump circuit, the input node is configured to receive a reference voltage; and the output node is configured to output a pump voltage having a voltage level lower than a voltage level of the reference voltage.

According to still another aspect of the present invention, there is provided a method of operating a pump stage circuit or an output stage circuit of a charge pump circuit, the method including: transitioning a voltage level at a first end of the capacitive device from a first voltage level to a second voltage level in response to a first logic value of the control signal; transitioning a voltage level at a second end of the capacitive device to a third voltage level in response to a second voltage level at a first end of the capacitive device, the second end of the capacitive device electrically coupled with a gate terminal of a transistor; and adjusting, by a first diode device having an anode coupled to the gate terminal of the transistor and a cathode coupled to the S/D terminal of the transistor, a first voltage difference between the gate terminal and a source/drain (S/D) terminal of the transistor when the transistor is on and the first diode device is forward biased and on.

The method further comprises the following steps: adjusting, by a second diode device having an anode coupled to the S/D terminal of the transistor and a cathode coupled to the gate terminal of the transistor, a second voltage difference between the S/D terminal and the gate terminal of the transistor when the transistor is off and the second diode device is forward biased and on.

In the method, the first diode device has a forward voltage drop; the transistor has a threshold voltage; and the forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.

Drawings

Various aspects of the invention are better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a functional block diagram of a charge pump circuit according to some embodiments.

Fig. 2 is a circuit schematic of a pumping stage circuit that may be used in the charge pump circuit of fig. 1, in accordance with some embodiments.

Fig. 3 is a circuit schematic of an output stage circuit that may be used in the charge pump circuit of fig. 1, in accordance with some embodiments.

Fig. 4 is a circuit schematic of a control circuit that may be used in the charge pump circuit of fig. 1, in accordance with some embodiments.

Fig. 5A and 5B are circuit schematic diagrams of two exemplary diode devices that may be used as diode devices in the pump stage circuit of fig. 2 or the output stage circuit of fig. 3, according to some embodiments.

Fig. 6 is a timing diagram of voltage levels on various nodes of the charge pump circuit of fig. 1, further illustrated in conjunction with fig. 2-4, in accordance with some embodiments.

FIG. 7 is a flow diagram of a method of operating the pump stage circuit of FIG. 2, in accordance with some embodiments.

FIG. 8 is a circuit schematic of a signal generation circuit that may be used in the control circuit of FIG. 4 according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as shown. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to some embodiments, a pump stage circuit or an output stage circuit of a charge pump circuit includes a transistor, a capacitive device coupled to a gate terminal of the transistor, and two diode devices between the gate terminal and a source/drain (S/D) terminal of the transistor. The two diode devices are coupled in anti-parallel. The voltage difference between the gate terminal and the S/D terminal is maintained at about the forward voltage drop of one of the two diode devices by the discharge path provided by the one of the two diode devices and the DC isolation between the gate terminal of the transistor and the drive signal.

Fig. 1 is a functional block diagram of a charge pump circuit 100 according to some embodiments. The charge pump circuit 100 includes: an input node 102; an output node 104; a reference voltage terminal 106; n pump stage circuits 110[1], 110[2] and 110[ N ]; an output stage circuit 120; and a control circuit 130. N is a positive integer equal to or greater than 1. As a non-limiting example, fig. 1 shows three pump stage circuits 110[1], 110[2], and 110[ N ] (i.e., N-3). Pump stage circuits 110[1], 110[2] and 110[ N ] and output stage circuit 120 are coupled between input node 102 and output node 104. Control circuit 130 is coupled to output node 104 and reference voltage terminal 106 and is configured to generate a plurality of control signals SW [1], SW [2], SW [ N ], SWF, CP [1], CP [2], and CP [ N ] for controlling the operation of pump stage circuits 110[1], 110[2], and 110[ N ] and output stage circuit 120.

Each of the pump stage circuits 110[1], 110[2] and 110[ N ] includes an input terminal IN, an output terminal OUT, and control signal terminals SW and CP. The output stage circuit 120 includes an input terminal IN, an output terminal OUT, and a control signal terminal SW. The input IN of first pump stage circuit 110[1] is coupled to input node 102. The output OUT of the nth pump stage circuit 110[ N ] is coupled to the input IN of the (N +1) th pump stage circuit 110[ N +1], where N is a positive integer and 1 ≦ N ≦ N-1. The output OUT of the Nth pump stage circuit 110[ N ] is coupled to the input IN of the output stage circuit 120. The output terminal OUT of the output stage circuit 120 is coupled to the output node 104.

In some embodiments, a pump stage circuit110[1]、110[2]And 110[ N ]]Is configured to have a voltage level V at the input node 102_INTo a predetermined voltage level V at the output node 104_OUT. During steady state operation of charge pump circuit 100, and ignoring transient overshoots or undershoots, pump stage circuit 110[1]]At a voltage level of V at the output terminal OUT_INAnd V₁Switching between the two modes; pump stage circuit 110[2]]At a voltage level of V at the output terminal OUT₁And V₂Switching between the two modes; pump stage circuit 110[ N ]]At a voltage level of V_N-2And V_N-1Switching between the two modes; and a pump stage circuit 110[ N ]]At a voltage level of V at the output terminal OUT_N-1And V_OUTTo switch between. In some embodiments, pump stage circuit 110[ n ]]At the output terminal OUT according to the following equation at V_n-1And V_nSwitching between:

ΔV＝V_OUT-V_N； (1)

V₀＝V_N； (2)

V_N＝V_OUT(ii) a And (3)

V_n＝V_N+ N (Δ V/N), N being a positive integer and 1. ltoreq. n.ltoreq.N-1 (4)

In some embodiments, voltage level V_OUTGreater than voltage level V_INThe charge pump circuit 100 functions as a positive charge pump, and therefore, Δ V has a positive value. In some embodiments, voltage level V_OUTLess than voltage level V_INThe charge pump circuit 100 functions as a negative charge pump, and thus, Δ V has a negative value.

In addition, the control signal terminal SW of the pump stage circuit 110[1] is configured to receive the control signal SW [1 ]; and the control signal terminal CP of the pump stage circuit 110[1] is configured to receive the control signal CP [1 ]. The control signal terminal SW of the pump stage circuit 110[2] is configured to receive the control signal SW [2 ]; and the control signal terminal CP of the pump stage circuit 110[2] is configured to receive the control signal CP [2 ]. Control signal terminal SW of pump stage circuit 110[ N ] is configured to receive control signal SW [ N ]; and the control signal terminal CP of the pump stage circuit 110N is configured to receive the control signal CP N. The control signal terminal SW of the output stage circuit 120 is configured to receive the control signal SWF. Exemplary implementations and operations of the pump stage circuits 110[1], 110[2] and 110[ N ] and the output stage circuit 120 in response to the respective control signals are also described in detail in conjunction with FIGS. 2 and 6.

Control circuit 130 is coupled with output node 104 and reference voltage terminal 106, and is configured to: based on the voltage level V at the output node 104_OUTAnd a reference voltage level V at reference voltage terminal 106_REFGenerates a plurality of control signals SW [1]]、SW[2]、SW[N]、SWF、CP[1]、CP[2]And CP [ N ]]. In some embodiments, signal SW [ n ]]And a corresponding signal CP [ n ]]Having the same waveform. In some embodiments, signal SW [ n ]]Having a voltage level pulse width (corresponding to a logic high value) different from the corresponding signal CP n]Voltage level pulse width of (2).

In some embodiments, all odd signals SW [ n ] have the same first waveform and all even signals SW [ n ] have the same second waveform. In some embodiments, the first waveform and the second waveform are not at the same voltage level corresponding to a logic high value, and thus the odd signal SW [ n ] and the even signal SW [ n ] are referred to as non-overlapping signals. In some embodiments, all odd-numbered signals CP [ n ] have the same third waveform and all even-numbered signals CP [ n ] have the same fourth waveform. In some embodiments, the third waveform and the fourth waveform are not at the same voltage level corresponding to a logic high, and thus the odd signal CP [ n ] and the even signal CP [ n ] are referred to as non-overlapping signals.

An exemplary implementation and operation of the control circuit 130 is also described in detail in conjunction with fig. 4.

Fig. 2 is a circuit schematic of a pump stage circuit 200 that may be used in the charge pump circuit 100 in fig. 1, in accordance with some embodiments. In some embodiments, pump stage circuit 200 may be used as any or all of pump stage circuits 110[1], 110[2], and 110[ N ].

Pump stage circuit 200 includes an input IN, an output OUT, and control signal terminals SW and CP, which correspond to pump stage circuit 110[1] of FIG. 1, respectively]、110[2]Or 110[ N ]]Terminals IN, OUT, SW and CP. For illustration, the input IN has a voltage V_SAnd the output terminal OUT has a voltage V_D. The control signal terminal SW is configured to receive the control signal S₁The control signal corresponding to the control signal SW [1]]、SW[2]Or SW [ N ]]. The control signal terminal CP is configured to receive the control signal S₂The control signal corresponding to the control signal CP [1]]、CP[2]Or CP [ N ]]。

The pump stage circuit 200 includes a transistor 210, a first capacitive device 222, a second capacitive device 224, a first diode device 232, a second diode device 234, a first driver 242, and a second driver 244.

The transistor 210 is an N-type transistor and functions as a switching device. In some embodiments, the transistor 210 is implemented as a P-type transistor or other applicable switching device. The transistor 210 includes a gate terminal 212, a first S/D terminal 214, and a second S/D terminal 216. The first S/D terminal 214 is coupled to the input terminal IN. The second S/D terminal 216 is coupled to the output terminal OUT. The gate terminal 212 has a voltage V_G。

The first capacitive device 222 has a first end coupled to the gate terminal 212 of the transistor 210 and is configured to receive the drive signal S₃The second end portion of (a). The second capacitive device 224 has a first end coupled to the output OUT and is configured to receive the drive signal S₄The second end portion of (a). The first diode device 232 has a cathode coupled to the second S/D terminal 216 of the transistor 210 and an anode coupled to the gate terminal 212 of the transistor 210. The second diode device 234 has a cathode coupled to the gate terminal 212 of the transistor 210 and an anode coupled to the second S/D terminal 216 of the transistor 210.

The first driver 242 is configured to: based on control signal S₁Generating a drive signal S₃. The second driver 244 is configured to: based on control signal S₂Generating a drive signal S₄. The first driver 242 is an inverter and,having an input coupled to the control signal terminal SW and an output coupled to a second end of the capacitive device 222. The second driver 244 is an inverter having an input coupled to the control signal terminal CP and an output coupled to the second end of the capacitive device 224. In some embodiments, the first driver 242 and the second driver 244 are implemented as one or a combination of the following: inverters, buffers, level shifters, or other suitable devices. In some embodiments, the signal S₁、S₂、S₃And S₄Each of which is switched between a first voltage level corresponding to a logic high value (hereinafter referred to as "first logic high level") and a reference ground voltage level corresponding to a logic low value (hereinafter referred to as "logic low level"). In some embodiments, the signal S₃And S₄Is switched between a first logic high level and a logic low level, and the signal S₁And S₂Each of which switches between a second voltage level (hereinafter referred to as "second logic high level") corresponding to a logic high value and a logic low level. In some embodiments, the second logic high level is greater than the first logic high level.

When the diode device is forward biased and conducting, the diode device has a forward voltage drop between its anode and cathode. In some embodiments, first diode device 232 has a forward voltage drop V_FB1The second diode device 234 has a forward voltage drop V_FB2And a forward voltage drop V_FB1Greater than the forward pressure drop V_FB2. Also, the transistor 210 has a threshold voltage V between the gate terminal 212 and the S/D terminal 216_TH. In some embodiments, the forward pressure drop V_FB1Greater than the threshold voltage V of transistor 210_TH。

In some embodiments, diode 232 is configured to: when the diode device 232 is forward biased and conducting, a discharge path between the gate terminal 212 and the S/D terminal 216 is provided to cause the voltage V_GAnd voltage V_DThe voltage difference between is reduced to be not greater than the forward voltage of the diode device 232Reduce V_FB1. In some embodiments, diode 234 is configured to: when the diode device 234 is forward biased and conducting, a discharge path between the gate terminal 212 and the S/D terminal 216 is provided to couple the voltage V_GAnd voltage V_DThe voltage difference therebetween is defined to be not greater than the forward voltage drop V of the diode device 234_FB2. In some embodiments, when the voltage V is_GAnd voltage V_DIn response to the signal S₃And S₄And switched by operation of the capacitive devices 222 and 224, the diode devices 232 and 234 also provide a conductive path to reduce the voltage V_GAnd voltage V_DThe peak voltage level of.

In operation, diode devices 232 and 234 thus serve to ensure that the DC value on capacitor 222 is in the correct range to turn transistor 210 on or off.

In some embodiments, diode device 232 includes one or more diodes in series, and the forward voltage drop V of diode device 232_FB1Is the sum of the forward voltage drops of each diode in the series. In some embodiments, diode device 234 includes one or more diodes in series, and the forward voltage drop V of diode device 234_FB2Is the sum of the forward voltage drops of each diode in the series.

In operation, the capacitive device 222 couples the drive signal S₃Level shifting is performed so that there is no need to generate control signals with large voltage swings. This feature simplifies circuit design and makes it possible to implement a charge pump without the cost associated with high voltage capability. The detailed operation of the various components of pump stage circuit 200 is illustrated in conjunction with fig. 6.

Fig. 3 is a circuit schematic of an output stage circuit 300 that may be used in the charge pump circuit 100 in fig. 1, in accordance with some embodiments. Components in fig. 3 that are the same as or similar to those in fig. 2 have the same reference numerals, and thus detailed descriptions thereof are omitted.

In contrast to pump stage circuit 200, output stage circuit 300 does not have control signal terminal CP and driver 244. Capacitive device 224 is coupled between the output terminal and power reference terminal 310. In some embodiments, the power reference terminal 310 has a voltage level corresponding to a ground reference voltage level or a 0V level. In some embodiments, the power reference 310 has the same voltage level as the logic low level.

In operation, the output stage circuit 300 stores and holds the charge from the previous pump stage circuit at the capacitive device 224 and outputs a voltage having a predetermined pump voltage level at the output terminal OUT. The capacitance value of the capacitive device 224 in the output stage circuit 300 is set large enough to substantially maintain a predetermined pump voltage level while allowing a predetermined current to be output to an external circuit.

Fig. 4 is a circuit schematic of a control circuit 400 that may be used in the charge pump circuit 100 of fig. 1, in accordance with some embodiments.

The control circuit 400 includes a feedback voltage terminal 402, a reference voltage terminal 404, a supply voltage terminal 408, resistive devices 412 and 414, a comparator 420, a signal generation circuit 430, and a plurality of control lines 440. In some embodiments, the control circuit 400 includes a clock terminal 406.

The feedback voltage terminal 402 is coupled to the output node 104 of the charge pump circuit 100. The reference voltage terminal 404 is configured to receive a reference voltage having a reference voltage level V_REFThe reference voltage of (1). The supply voltage terminal 408 is configured to carry a voltage having a supply voltage level. In some embodiments, the power supply voltage level is the same as the first logic high level or the second logic high level. Resistive devices 412 and 414 are coupled in series between the supply voltage terminal 408 and the feedback voltage terminal 402. The resistive devices 412 and 414 are configured as a voltage divider to convert the voltage on the output node 104 to a feedback voltage having a voltage level V comparable to the reference voltage level_REFVoltage level V of comparison_FB。

The comparator 420 includes a first input 422, a second input 424, and an output 426. The first input 422 is configured to receive a referenceVoltage (with reference voltage level V)_REF). The second input 424 is configured to receive a feedback voltage (having a feedback voltage level V)_FB). Comparator 420 compares reference voltage level V_REFAnd a feedback voltage level V_FBAnd generates a comparison result at output 426.

The signal generation circuit 430 is coupled to the output 426 of the comparator 420 and to the clock terminal 406 (if present). Signal generation circuit 430 is also coupled to pump stage circuits 110[1], 110[2], and 110[ N ] and output stage circuit 120 via a plurality of control lines 440. Signal generation circuit 430 is configured to receive the comparison result at output 426 of comparator 420 and the clock signal CLK from clock terminal 406 and generate control signals SW [1], SW [2], SW [ N ], SWF, CP [1], CP [2], and CP [ N ] on a plurality of control lines 440. In some embodiments, the signal generation circuit 430 is further configured to receive a clock signal CLK from the clock terminal 406.

The control circuit 400 is a non-limiting example. Other types of control circuits that may be used to generate control signals SW [1], SW [2], SW [ N ], SWF, CP [1], CP [2], and CP [ N ] are within the scope of various embodiments of the present invention to control the charge pump circuit 100 based on pulse width, frequency, or amplitude information of these signals.

Fig. 8 is a circuit schematic of an exemplary signal generation circuit 800 that may be used as the signal generation circuit 430 in the control circuit of fig. 4, in accordance with some embodiments.

The signal generation circuit 800 includes a D flip-flop (DFF)802, an and gate 804, and a two-phase non-overlapping clock generator 808. DFF 802 includes a clock input 806 and a comparator input 826. The two-phase non-overlapping clock generator 808 includes a first output 810 and a second output 812.

DFF 802 is configured to receive the clock signal CLK at clock input 806 and the comparator output, e.g., the comparison result at output 426, at logic input 826. DFF 802 samples the comparator output based on the clock signal CLK and outputs the sampled comparator output.

The and gate 804 is configured to receive the sampled comparator output from the DFF 802 and the clock signal CLK, and provide a gated output to a two-phase non-overlapping clock generator 808. In response to the sampled logic high level of the comparator output, the and gate 804 is configured to output a gated clock signal. In response to the sampled logic low level of the comparator output, the and gate 804 is configured to output a logic low level.

The two-phase non-overlapping clock generator 808 is configured to receive the gated clock signal from the and gate 804 and, in response, create a first pulse signal a at a first output 810 and a second pulse signal B at a second output 812. In some embodiments, the first pulse signal A and the second pulse signal B are used as the charge pump control signals SW [ i ] and CP [ i ]. In some embodiments, the first output 810 and the second output 812 are coupled to a plurality of control lines 440.

In some embodiments, the first pulse signal a is used as the charge pump control signal SW [ i ] with i being an even value, and the second pulse signal B is used as the charge pump control signal SW [ i ] with i being an odd value.

In some embodiments, the first pulse signal a is used as the charge pump control signal CP [ i ] with i being an odd value, and the second pulse signal B is used as the charge pump control signal CP [ i ] with i being an even value.

In operation, when the voltage level V is fed back_FBAbove reference voltage level V_REFThe signal generation circuit 800 responds to the comparator output by generating a first pulse signal a and a second pulse signal B, and when a voltage level V is fed back_FBBelow a reference voltage level V_REFThe signal generation circuit 800 responds to the comparator output by not generating the first pulse signal a and the second pulse signal B.

The signal generation circuit 800 is a non-limiting example. Other types of signal generation circuits (including signal generation circuits that do not have a clock signal input) that may be used to generate control signals SW [1], SW [2], SW [ N ], SWF, CP [1], CP [2], and CP [ N ] to control the charge pump circuit 100 are within the scope of the various embodiments of the present invention.

Fig. 5A is a circuit schematic of an exemplary diode device 500A that may be used as diode device 232 or 234 in pump stage circuit 200 of fig. 2 or output stage circuit 300 of fig. 3, according to some embodiments.

The diode device 500A includes an anode terminal 502, a cathode terminal 504, and J P-type transistors 510[ 1] connected as diodes between the anode terminal 502 and the cathode terminal 504]To 510[ J ]]. J is a positive integer greater than zero. When J is greater than 1, the P-type transistor 510[ 1]]To 510[ J ]]Are coupled in series. To implement diode device 232 and diode device 234 using a configuration based on diode device 500A, diode device 232 is configured with X (J ═ X) transistors 510[ 1] connected as diodes]To 510[ X ]]And diode device 234 is configured with Y (J ═ Y) transistors 510[ 1] connected as diodes]To 510[ Y ]]Wherein X and Y are positive integers. In some embodiments, the forward voltage drop V of the diode device 232_FB1Greater than the forward voltage drop V of the diode device 234_FB2. Therefore, Y is set to be smaller than X.

Fig. 5B is a circuit schematic of another exemplary diode device 500B that may be used as diode device 232 or 234 in pump stage circuit 200 of fig. 2 or output stage circuit 300 of fig. 3, in accordance with some embodiments. Components in fig. 5B that are the same as or similar to those in fig. 5A have the same reference numerals, and thus detailed descriptions thereof are omitted.

The diode device 500B includes K N-type transistors 520[ 1] connected as diodes between the anode terminal 502 and the cathode terminal 504]To 520[ K ]]. K is a positive integer greater than zero. When K is greater than 1, N-type transistor 520[ 1]]To 520[ K ]]Are coupled in series. To implement diode device 232 and diode device 234 using a configuration based on diode device 500B, diode device 232 is configured with X (K ═ X) transistors 520[ 1] connected as diodes]To 520[ X ]]And diode device 234 is configured with Y (K ═ Y) transistors 520[ 1] connected as diodes]To 520[ Y ]]Wherein X and Y are positive integers. In some embodiments, diode device 232 hasWith positive pressure drop V_FB1Greater than the forward voltage drop V of the diode device 234_FB2. Therefore, Y is set to be smaller than X.

In some embodiments, one of diode device 232 and diode device 234 is implemented based on the configuration of diode device 500A, and the other of diode device 232 and diode device 234 is implemented based on the configuration of diode device 500B. In some embodiments, diode device 232 or diode device 234 is implemented with other types of diode devices than diode device 500A and diode device 500B.

Fig. 6 is a timing diagram of voltage levels at various nodes of the charge pump circuit 100 in fig. 1, further illustrated in conjunction with fig. 2-4, in accordance with some embodiments.

In the example shown in fig. 6, the number of pump stage circuits (i.e., the number N in fig. 1) is set to 2, and the charge pump circuit is configured as a negative charge pump. Voltage level V_INIs set to 0V and voltage level V_OUTSet to-2.2V. The charge pump circuits shown in connection with fig. 1 to 4 also function as positive charge pumps. Different configurations and arrangements of the charge pump circuit 100 are within the scope of various embodiments of the present invention.

Waveform 602 corresponds to first pump stage circuit 110[1]]Signal S of₁The voltage level of (c). Waveform 604 corresponds to first pump stage circuit 110[1]]Signal S of₂The voltage level of (c). Waveform 612 corresponds to first pump stage circuit 110[1]]Voltage V of_DThe voltage level of (c). Waveform 614 corresponds to first pump stage circuit 110[1]]Voltage V of_GThe voltage level of (c). Waveform 622 corresponds to second pump stage circuit 110[2]]Voltage V of_DThe voltage level of (c). Waveform 632 corresponds to the voltage V of output stage circuit 120_DThe voltage level of (c).

If not otherwise specified, the following description is based primarily on the operation of first pump stage circuit 110[1] using reference numerals from pump stage circuit 200 in FIG. 2. The operation of the transistor 210 and capacitive device 222 of the second pump stage circuit 110[2] and output stage circuit 120 is similar to the operation of the transistor 210 and capacitive device 222 of the first pump stage circuit 110[1 ]. The operation of the capacitive device 224 of the second pump stage circuit 110[2] is similar to the operation of the capacitive device 224 of the first pump stage circuit 110[1 ]. And thus detailed description thereof is omitted.

In this embodiment, the signal S₁、S₂、S₃And S₄Has a logic high level of 1.8 volts (V) and a logic low level of 0.0V. In some embodiments, the signal S₁And S₃Each signal of (a) has an and signal S₂And S₄Is different from the logic high level. In some embodiments, the signal S₁And S₃Has a logic high level of 2.5V, and the signal S₂And S₄Each having a logic high level of 1.8V.

At time T₁First pump stage circuit 110[1] during previous steady state operation of charge pump circuit 100]Signal S of₁(waveform 602) and Signal S₂(waveform 604) is a logic low level. Thus, first pump stage circuit 110[1]]Signal S3 (not shown) and signal S4 (not shown) are high level signals. In this example, a first pump stage circuit 110[1]]Voltage V of_DAt an input voltage level from a power supply or a previous pump stage circuit, such as for the first pump stage circuit 110[1]]0.0V of (1). Also, in this example, first pump stage circuit 110[1]]Voltage V of_GIs equal to the input voltage level plus the forward voltage drop V of the diode device 232_FB1(such as V)_FB1) And (4) adding the sums. Because of the forward pressure drop V_FB1Is set to be greater than the threshold voltage V of the transistor 210_THSo transistor 210 is turned on to change the input voltage level (e.g., 0.0V in this example) to a voltage V_D。

At time T₁A signal S₁(waveform 602) transitions from a low logic level to a high logic level. Signal S₂(waveform 604) is still at a low logic level. Thus, the signal S₃(not shown) from high logic powerFlat transitions to low logic level and signal S₄(not shown) is still a high signal. Through a first pump stage circuit 110[1]]At time T, the capacitive device 222 operates₁First pump stage circuit 110[1]]Voltage V of_G(waveform 614) is pulled down by about 1.8V. At the same time, the first pump stage circuit 110[1]]Diode device 234 also provides a discharge path to couple voltage V_G(waveform 614) and voltage V_D(waveform 612) are pulled closer together. As a result of these opposing tensile forces, at time T₁At a voltage V_G(waveform 614) slave voltage level V_FB1Transition to specific voltage level V_FB1The voltage level after the 1.8V subtraction is a voltage level that is several hundred millivolts (mV) higher. The voltage difference between the gate terminal of transistor 210 and the S/D terminal of transistor 210 is insufficient to turn transistor 210 on. Voltage V_D(waveform 612) is still at 0.0V. Thus, the transistor 210 is turned off.

At time T₁After but at time T₂Previously, the voltage V was applied through the diode device 234_G(waveform 614) and voltage V_D(waveform 612) are pulled closer together. Transistor 210 is still off. In some embodiments, time T₁And time T₂The time period in between is set to be insufficient to apply the voltage V_GIs pulled large enough to cause transistor 210 to be at time T₂Is turned on. In some embodiments, time T₁And time T₂The time period in between is sufficiently small that the voltage V_G(waveform 614) voltage level or voltage V_DThe voltage level of (waveform 612) is less than 100 mV.

At time T₂A signal S₂(waveform 604) transitions from a low logic level to a high logic level. Signal S₁(waveform 602) is still at a high logic level. Thus, the signal S₄(not shown) transitions from a high logic level to a low logic level, and signal S₃(not shown) is still a low signal. By operation of the capacitive device 224, at time T₂At a voltage V_D(waveform 612) is pulled down by about 1.8V. Also, in this example, via capacitive device 224 with another capacitance of the next pump stage circuitSexual devices (e.g., second pump stage circuit 110[2]]Of the capacitive device 224) or another capacitive device of the corresponding output stage circuit 120 (e.g., the capacitive device 224 of the output stage circuit 120), the voltage V_DIs also pulled to the steady state output voltage level of the pump stage, such as-1.1V. In some embodiments, also by adjusting control signal SW [1]]、SW[2]、SW[N]、SWF、CP[1]、CP[2]And CP [ N ]]By adjusting the frequency of the signal S and/or by adjusting the frequency of the signal S₄To control the shared charge. Time T when diode device 234 changes from conducting to reverse biased₂At a voltage V_G(waveform 614) is pulled down slightly. As a result, at time T₂At a voltage V_D(waveform 612) transitions from 0.0V to a voltage level that is several hundred mV higher than the voltage level of-1.8V. Transistor 210 is still off.

At time T₂After but at time T₃Previously, voltage V was after diode devices 232 and 234 reached their charge equilibrium state after being turned off_G(waveform 614) is still at about the same voltage level. Voltage V_D(waveform 612) is pulled down and then still at the steady state output voltage level (e.g., -1.1V in this example). In this example, V_GVoltage level of greater than V_DBut the voltage difference between them is not sufficient to turn on transistor 210. Transistor 210 is still off.

At time T₃A signal S₂(waveform 604) transitions from a high logic level to a low logic level. Signal S₁(waveform 602) is still at a high logic level. Thus, the signal S₄(not shown) transitions from a low logic level to a high logic level, while signal S₃(not shown) is still a low signal. By operation of the capacitive device 224, at time T₃At a voltage V_D(waveform 612) is pulled up by about 1.8V. At the same time, diode device 234 also provides a discharge path to couple voltage V_G(waveform 614) and voltage V_D(waveform 612) are pulled closer together. As a result, at time T₃At a voltage V_D(waveform 612) transitions from the steady state output voltage level (e.g., -1.1V in this example)To a voltage level that is several hundred mV higher than the voltage level of 0.7V (i.e., -1.1V plus 1.8V). The voltage difference between the gate terminal of transistor 210 and the S/D terminal of transistor 210 is insufficient to turn transistor 210 on. Transistor 210 is still off.

At time T₃After but at time T₄Previously, the voltage V was applied through the diode device 234_G(waveform 614) and voltage V_D(waveform 612) are pulled closer together. Transistor 210 is still off. In some embodiments, time T₃And time T₄The time period in between is sufficiently small that the voltage V_G(waveform 314) voltage level or voltage V_DThe voltage level of (waveform 612) is less than 100 mV.

At time T₄A signal S₁(waveform 602) transitions from a high logic level to a low logic level. Signal S₂(waveform 604) is still at a low logic level. Thus, the signal S₃(not shown) transitions from a low logic level to a high logic level, while signal S₄(not shown) is still a high signal. By operation of the capacitive device 222, at time T₄At a voltage V_G(waveform 614) is pulled up by about 1.8V. At the same time, diode device 232 also provides a discharge path to couple voltage V_G(waveform 614) is pulled to near voltage V_D. As a result, at time T₄At a voltage V_G(waveform 614) transition to specific voltage level V_FB1A voltage level that is several hundred mV higher. The voltage difference between the gate terminal of the transistor 210 and the S/D terminal 216 is sufficient to turn on the transistor 210.

At time T₄After but at time T₅Front, voltage V_D(waveform 612) is pulled down and then still at a steady state input voltage level (e.g., 0V in this example), and voltage V is_G(waveform 614) is pulled down and then still at the forward voltage drop V of diode device 232_FB1Summed with the steady state input voltage level. Transistor 210 is still on.

At time T₅At this point, the next cycle of operation of the pump stage circuit 200 begins. Time T₅Correspond toTime T of the next operating cycle₁。

Except that the corresponding control signal of the second pump stage circuit is associated with the first pump stage circuit 110[1]]To the first pump stage circuit 110[1]]Second pump stage circuit 110[2] operates in a similar manner]. As a result, pump stage circuit 110[2]]Voltage V of_D(waveform 622) at time T₁To time T₄During which it is at-1.1V and at time T₄To time T₅During which time it is pumped (pump) to-2.2V. The transistor 210 of the output stage circuit 120 is connected to the first input stage 110[1]]Operates in a similar manner as transistor 210. The capacitive device 224 of the output stage circuit 120 is configured to: when the transistor 210 of the output stage circuit 120 is at the time T₁To time T₄When the period is cut off, the voltage V is applied_DIs maintained at-2.2V. The capacitive device 224 of the output stage circuit 120 is further configured to: when the transistor 210 of the output stage circuit 120 is at the time T₄To time T₅During which it is turned on, it receives the signal from the second pump stage circuit 110[2]]The capacitive device 224. As a result, the voltage V of the output stage circuit 120_DStill remaining at-2.2V.

As shown in fig. 6 and 2, through the discharge path provided by diode device 232 and gate terminal 212 of transistor 210 and the output of driver 242 (i.e., signal S)₃) With the DC isolation between, when the transistor 210 is turned on, the voltage difference between the gate terminal 212 and the S/D terminal 216 and the voltage difference between the gate terminal 212 and the S/D terminal 214 remain approximately the forward voltage drop V of the diode device 232_FB1. In some embodiments, the forward voltage drop V of the diode device 232_FB1Set to less than a logic high level (such as 1.8V in this example). For the pump stage circuit or output stage circuit 120 of the subsequent stage of the charge pump circuit 100, regardless of the corresponding input voltage level or pumping voltage level, therefore, the transistor corresponding to the transistor 210 has a forward voltage drop V through the diode device 232_FB1The regulated gate terminal, the S/D terminal voltage, is less than the logic high level when transistor 210 is on.

FIG. 7 is a flow diagram of a method 700 of operating the pump stage circuit of FIG. 2, in accordance with some embodiments. Fig. 7 is illustrated in connection with the example shown in fig. 2. It should be understood that additional operations may be performed before, during, and/or after the method 700 shown in fig. 7, and thus only some other processes are briefly described herein.

The method 700 begins at operation 710, where a voltage level at a first end of a capacitive device (such as a signal S between a driver 242 and the capacitive device 222) is caused in response to a first logic value of a control signal₃) Transitioning from a first voltage level to a second voltage level. In some embodiments, the first voltage level corresponds to a logic low level, the second voltage level corresponds to a logic high level, and the control signal corresponds to the signal S₁And the first logic value corresponds to a logic low value.

The method 700 proceeds to operation 720, where a voltage level (such as voltage V) at a second end of the capacitive device 222 is caused in response to a second voltage level at the first end of the capacitive device_G) Transitioning to a third voltage level. A second end of the capacitive device 222 is electrically coupled to the gate terminal 212 of the transistor 210.

In some embodiments, operations 710 and 720 correspond to time T in the timing diagram of FIG. 6₄The signal transitions at (a).

The method 700 proceeds to operation 730, wherein a first voltage difference between the gate terminal 232 and the source/drain (S/D) terminal 216 of the transistor 210 is regulated by a first diode device, such as the diode device 232, when the transistor 210 is on and the first diode device 232 is forward biased and conductive. The first diode device 232 has an anode coupled to the gate terminal 212 of the transistor 210 and a cathode coupled to the S/D terminal 216 of the transistor 210. In some embodiments, operation 730 corresponds to the slave time T in the timing diagram of FIG. 6₄To time T₅The signal transition of (2).

The method 700 proceeds to operation 740, where the first terminal of the capacitive device 222 is caused to be responsive to a second logic value of the control signalVoltage level at the section (such as signal S)₃) Transitioning from the second voltage level to the first voltage level. In some embodiments, the second logic value corresponds to a logic high value. As a result, the voltage V is made_GTo a fourth voltage level that is insufficient to turn transistor 210 on. In some embodiments, operation 740 corresponds to time T in the timing diagram of FIG. 6₁The signal transitions at (a).

The method 700 proceeds to operation 750 where a second voltage difference between the S/D terminal 216 of the transistor 210 and the gate terminal 212 of the transistor 210 is regulated by a second diode device (such as the diode device 234) when the transistor 201 is on and the second diode device 234 is forward biased and on. The second diode device 234 has an anode coupled to the S/D terminal 216 of the transistor 210 and a cathode coupled to the gate terminal 212 of the transistor 210. In some embodiments, operation 750 corresponds to slave time T in the timing diagram of FIG. 6₁To time T₂And/or from time T₃To time T₄The signal transition of (2).

In some embodiments, first diode device 232 has a forward voltage drop V_FB1The second diode device 234 has a forward voltage drop V_FB2And a forward voltage drop V_FB1Greater than the forward pressure drop V_FB2. Also, the transistor 210 has a threshold voltage V between the gate terminal 212 and the S/D terminal 216_TH. In some embodiments, the forward pressure drop V_FB1Greater than the threshold voltage V of transistor 210_TH。

In some embodiments, operations 710-750 may be applicable to a method of operating the output stage circuit 300 in fig. 3.

The method 700 proceeds to operation 760, where it is responsive to another control signal (such as control signal S)₂) The voltage level at the S/D terminal 216 of the transistor 210 is pumped to a predetermined pump voltage level. In some embodiments, operation 760 corresponds to slave time T in the timing diagram of FIG. 6₂To time T₃The signal transition of (2).

According to one embodiment, a charge pump circuit includes a sub-circuit that is either a pump stage circuit or an output stage circuit. The sub-circuit comprises an input terminal, an output terminal, a transistor, a first capacitive device, a first diode device and a second diode device. The transistor has a first source/drain (S/D) terminal coupled to the input terminal, a second S/D terminal coupled to the output terminal, and a gate terminal. The first capacitive device has a first end portion coupled to the gate terminal of the transistor and a second end portion configured to receive a first drive signal. The first diode device has a cathode coupled to the second S/D terminal of the transistor and an anode coupled to the gate terminal of the transistor. The second diode device has a cathode coupled to the gate terminal of the transistor and an anode coupled to the second S/D terminal of the transistor.

According to another embodiment, a charge pump circuit includes an input node, an output node, N pump stage circuits, and an output stage circuit. N is a positive integer greater than zero. Each of the N pump stage circuits includes an input terminal and an output terminal. The output stage circuit comprises an input end and an output end. An input terminal of a first pump stage circuit of the N pump stage circuits is coupled to the input node. The output of the nth of the N pump stage circuits is coupled to the input of the (N +1) th of the N pump stage circuits, where N is a positive integer and 1 ≦ N (N-1). The output end of the Nth pump stage circuit in the N pump stage circuits is coupled with the input end of the output stage circuit. The output stage circuit has an output coupled to the output node. One of the N pump stage circuits further includes a transistor, a first capacitive device, a second capacitive device, a first diode device, and a second diode device. The transistor has: a first source/drain (S/D) terminal coupled to an input node of one of the N pump stage circuits; a second S/D terminal coupled to an output node of one of the N pump stage circuits; and a gate terminal. The first capacitive device has a first end portion coupled to the gate terminal of the transistor and a second end portion configured to receive a first drive signal. The second capacitive device has a first end coupled to the output node of one of the N pump stage circuits and a second end configured to receive a second drive signal. The first diode device has a cathode coupled to the second S/D terminal of the transistor and an anode coupled to the gate terminal of the transistor. The second diode device has a cathode coupled to the gate terminal of the transistor and an anode coupled to the second S/D terminal of the transistor.

According to another embodiment, a method of operating a pump stage circuit or an output stage circuit of a charge pump circuit is disclosed. The method comprises the following steps: the voltage level at the first end of the capacitive device is transitioned from a first voltage level to a second voltage level in response to a first logic value of the control signal. The method further comprises the following steps: transitioning the voltage level at the second end of the capacitive device to a third voltage level in response to a second voltage level on the first end of the capacitive device, the second end of the capacitive device being electrically coupled with the gate terminal of the transistor; and adjusting, by the first diode device, a first voltage difference between a gate terminal and a source/drain (S/D) terminal of the transistor when the transistor is on and the first diode device is forward biased and conducting. The first diode device has an anode coupled to a gate terminal of the transistor and a cathode coupled to an S/D terminal of the transistor.

The components of several embodiments are discussed above so that those of ordinary skill in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A charge pump circuit, comprising:

a sub-circuit that is a pump stage circuit or an output stage circuit, the sub-circuit comprising:

an input end;

an output configured to receive a second drive signal generated based on a second control signal;

a transistor having a first source/drain (S/D) terminal coupled with the input terminal, a second source/drain terminal coupled with the output terminal, and a gate terminal;

a first capacitive device having a first end portion coupled to a gate terminal of the transistor and a second end portion configured to receive a first drive signal generated based on a first control signal;

a first diode device having a cathode coupled to a second source/drain terminal of the transistor and an anode coupled to a gate terminal of the transistor; and

a second diode device having a cathode coupled to a gate terminal of the transistor and an anode coupled to a second source/drain terminal of the transistor;

a control circuit configured to generate the first control signal and the second control signal, the control circuit comprising:

a voltage divider configured to convert a voltage at an output of the charge pump circuit to a feedback voltage;

a comparator configured to compare the feedback voltage with a reference voltage; and

a signal generator configured to receive an output of the comparator and a clock signal, generate the first control signal and the second control signal,

wherein the first diode device has a forward voltage drop, the second diode device has a forward voltage drop, and the forward voltage drop of the first diode device is greater than the forward voltage drop of the second diode device.

2. The charge pump circuit of claim 1, wherein the sub-circuit is the pump stage circuit, the sub-circuit further comprising:

a second capacitive device having a first end coupled with the output of the sub-circuit and a second end configured to receive the second drive signal.

3. The charge pump circuit of claim 2,

wherein the sub-circuit further comprises:

a first driver configured to generate the first drive signal based on the first control signal; and

a second driver configured to generate the second drive signal based on the second control signal.

4. The charge pump circuit of claim 3, wherein:

the first driver is configured to switch the first drive signal between a first voltage level corresponding to a logic high value and a reference voltage level corresponding to a logic low value; and

the second driver is configured to switch the second drive signal between a second voltage level corresponding to the logic high value and a reference voltage level corresponding to the logic low value, the first voltage level being different from the second voltage level.

5. The charge pump circuit of claim 1, wherein:

the first diode device comprises X transistors connected as diodes, X is a positive integer greater than zero, and when X is greater than 1, the X transistors connected as diodes are connected in series; and

the second diode device includes Y transistors connected as a diode, Y being a positive integer greater than zero and less than X, and when Y is greater than 1, the Y transistors connected as a diode are connected in series.

6. The charge pump circuit of claim 1, wherein:

the first diode device has a forward voltage drop;

the transistor has a threshold voltage; and

the forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.

7. The charge pump circuit of claim 1, wherein the transistor is an N-type transistor.

8. A charge pump circuit, comprising:

an input node;

an output node;

n pump stage circuits, N being a positive integer greater than zero, each of the N pump stage circuits comprising:

an input end; and

an output end; and

the output stage circuit comprises an input end and an output end;

a control circuit configured to generate a plurality of control signals, the control circuit comprising:

a voltage divider configured to convert a voltage at the output node to a feedback voltage;

a signal generator configured to receive an output of the comparator and a clock signal, generate the plurality of control signals,

wherein,

an input terminal of a first pump stage circuit of the N pump stage circuits is coupled to the input node;

an output terminal of an nth pump stage circuit of the N pump stage circuits is coupled with an input terminal of an (N +1) th pump stage circuit of the N pump stage circuits, N is a positive integer and is more than or equal to 1 and less than or equal to (N-1);

the output end of the Nth pump stage circuit in the N pump stage circuits is coupled with the input end of the output stage circuit;

an output terminal of the output stage circuit is coupled to the output node; and

one of the N pump stage circuits further comprises:

a transistor having: a first source/drain (S/D) terminal coupled to an input terminal of one of the N pump stage circuits; a second source/drain terminal coupled to an output of one of the N pump stage circuits; and a gate terminal;

a first capacitive device having a first end portion coupled to a gate terminal of the transistor and a second end portion configured to receive a first drive signal generated based on a first control signal of the plurality of control signals;

a second capacitive device having a first end coupled to an output of one of the N pump stage circuits and a second end configured to receive a second drive signal generated based on a second control signal of the plurality of control signals;

a second diode device having a cathode coupled to a gate terminal of the transistor and an anode coupled to a second source/drain terminal of the transistor,

9. The charge pump circuit of claim 8, further comprising:

wherein one of the N pump stage circuits further comprises:

a first driver configured to generate the first drive signal based on the first control signal of the plurality of control signals; and

a second driver configured to generate the second drive signal based on the second control signal of the plurality of control signals.

10. The charge pump circuit of claim 9, wherein:

the first driver includes a first inverter; and

the second driver includes a second inverter.

11. The charge pump circuit of claim 9, wherein:

12. The charge pump circuit of claim 8, wherein:

13. The charge pump circuit of claim 8, wherein:

the first diode device has a forward voltage drop;

the transistor has a threshold voltage; and

14. The charge pump circuit of claim 8, wherein the transistor is an N-type transistor.

15. The charge pump circuit of claim 8, wherein:

the input node is configured to receive a reference voltage; and

the output node is configured to output a pump voltage having a voltage level lower than a voltage level of the reference voltage.

16. A method of operating a pump stage circuit or an output stage circuit of a charge pump circuit, the method comprising:

transitioning a voltage level at a first end of the capacitive device from a first voltage level to a second voltage level in response to a first logic value of the control signal;

transitioning a voltage level at a second end of the capacitive device to a third voltage level in response to a second voltage level at a first end of the capacitive device, the second end of the capacitive device electrically coupled with a gate terminal of a transistor; and

adjusting, by a first diode device having an anode coupled to a gate terminal of the transistor and a cathode coupled to a first source/drain terminal of the transistor, a first voltage difference between the gate terminal and a first source/drain (S/D) terminal of the transistor when the transistor is on and the first diode device is forward biased and on, wherein the first source/drain terminal of the transistor is coupled to an output node of the charge pump circuit,

wherein adjusting the first voltage difference is based on a forward voltage drop of the first diode device being greater than a forward voltage drop of a second diode device having a cathode coupled to a gate terminal of the transistor and an anode coupled to a first source/drain terminal of the transistor,

wherein the method of generating the control signal comprises:

converting a voltage at an output node of the charge pump circuit to a feedback voltage;

comparing the values of the feedback voltage and a reference voltage to generate a comparison result; and

and receiving the comparison result and a clock signal, and generating the control signal.

17. The method of claim 16, further comprising:

adjusting, by the second diode device, a second voltage difference between the first source/drain terminal and the gate terminal of the transistor when the transistor is off and the second diode device is forward biased and on.

18. The method of claim 17, wherein:

the first diode device has a forward voltage drop;

the transistor has a threshold voltage; and