CN106816509B - Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit - Google Patents
Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit Download PDFInfo
- Publication number
- CN106816509B CN106816509B CN201710224742.6A CN201710224742A CN106816509B CN 106816509 B CN106816509 B CN 106816509B CN 201710224742 A CN201710224742 A CN 201710224742A CN 106816509 B CN106816509 B CN 106816509B
- Authority
- CN
- China
- Prior art keywords
- layer
- gallium nitride
- nitride layer
- preparation
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 99
- 238000002360 preparation method Methods 0.000 title claims abstract description 38
- 150000001875 compounds Chemical class 0.000 title description 31
- 229910002601 GaN Inorganic materials 0.000 claims abstract description 94
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 90
- 238000001039 wet etching Methods 0.000 claims abstract description 24
- 239000002131 composite material Substances 0.000 claims abstract 12
- 239000000463 material Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 24
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 10
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 229910004541 SiN Inorganic materials 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims 2
- 230000000903 blocking effect Effects 0.000 claims 2
- 239000013078 crystal Substances 0.000 abstract description 17
- 238000010586 diagram Methods 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052594 sapphire Inorganic materials 0.000 description 8
- 239000010980 sapphire Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 6
- 229910052906 cristobalite Inorganic materials 0.000 description 6
- 229910052682 stishovite Inorganic materials 0.000 description 6
- 229910052905 tridymite Inorganic materials 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 5
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
- H10H20/82—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
- H10H20/0137—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials the light-emitting regions comprising nitride materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/822—Materials of the light-emitting regions
- H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
- H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
Landscapes
- Led Devices (AREA)
- Weting (AREA)
Abstract
本申请公开了一种复合衬底及其制备方法，基于该复合衬底，本申请公开了一种垂直结构发光二极管芯片的制备方法。在本申请提供的复合衬底中，由于夹在第一图形层和第二图形层之间的第一氮化镓层的厚度小于第一突起结构的高度，所以，第一图形层上的第一突起结构和第二图形层上的第二突起结构能够相互连接贯通，而且又由于第二图形层上的各个第二突起结构相互连接在一起，如此，第一图形层和第二图形层能够形成一整体相互连接的可被湿法腐蚀溶液所腐蚀的图形。当湿法腐蚀溶液一旦从复合衬底的侧面开始腐蚀图形层时，其能够较好地渗入蚀刻到每个突起结构，如此方便后续外延衬底的湿法腐蚀剥离。此外，该复合衬底还能够保证后续外延层的晶体质量。
The application discloses a composite substrate and a preparation method thereof. Based on the composite substrate, the application discloses a preparation method of a vertical light-emitting diode chip. In the composite substrate provided by the present application, since the thickness of the first gallium nitride layer sandwiched between the first patterned layer and the second patterned layer is smaller than the height of the first protrusion structure, the second gallium nitride layer on the first patterned layer A protruding structure and the second protruding structure on the second graphic layer can be connected to each other, and because each second protruding structure on the second graphic layer is connected to each other, so that the first graphic layer and the second graphic layer can An integrally interconnected pattern that can be etched by wet etching solutions is formed. Once the wet etching solution starts to etch the pattern layer from the side of the composite substrate, it can penetrate and etch each protruding structure well, which facilitates the subsequent wet etching and stripping of the epitaxial substrate. In addition, the composite substrate can also guarantee the crystal quality of subsequent epitaxial layers.
Description
Technical field
This application involves light emitting diode fields more particularly to a kind of compound substrate and preparation method thereof, compound based on this
Substrate, the application is gone back more particularly to a kind of preparation method of light emitting diode chip with vertical.
Background technique
Blue green LED chip includes horizontal structure light-emitting diode chip for backlight unit and light emitting diode chip with vertical,
Wherein, for horizontal structure light-emitting diode chip for backlight unit due to making substrate using Sapphire Substrate, thermal conductivity is poor, and influence chip can
By property, under the higher situation of cooling requirements especially in terms of high-power illumination, horizontal structure light-emitting diode chip for backlight unit it is bad
Gesture is more obvious.
And light emitting diode chip with vertical has since it can use the preferable substrate of heating conduction such as silicon substrate
There are higher reliability and preferable current spreading effect, becomes one of the important directions of current light emitting diode development.
The substrate of light emitting diode chip with vertical includes silicon carbide (SiC) substrate and Sapphire Substrate.Currently, due to
Sapphire Substrate is cheap compared with SiC substrate and is easy to obtain, thus using Sapphire Substrate is light emitting diode with vertical structure core
The most common substrate of piece.
Sapphire Substrate must be removed for production light emitting diode chip with vertical.Currently, main be widely used
Sapphire Substrate lift-off technology be laser lift-off technique.It is on the one hand needed using laser lift-off technique using expensive laser stripping
From equipment, on the other hand removing is by laser ablation epitaxial layer interface, and the yield rate of removing is not high, and special envoy is to be widely used at present
4,6 cun of Sapphire Substrates, since epitaxy technique makes the epitaxial wafer angularity finally to grow out big, the stripping of full wafer epitaxial wafer
Absciss layer is frequently not in same level, so that the focusing etching point of laser is more difficult, removing yield rate is lower.
Summary of the invention
In view of this, this application provides a kind of compound substrate and preparation method thereof, to be realized by Wet stripping techniques
The substrate and epitaxial structure of light emitting diode with vertical structure are effectively peeled off.
In addition, present invention also provides a kind of preparation methods of light emitting diode chip with vertical.
In order to achieve the above-mentioned object of the invention, present invention employs following technical solutions:
A kind of preparation method of compound substrate, comprising:
Epitaxial substrate is provided；
Form the first graph layer in the epitaxial substrate, first graph layer includes multiple mutually isolated first prominent
Structure is played, there are gaps between the multiple the first mutually isolated raised structures；
The first gallium nitride layer is formed on the gap, the thickness of first gallium nitride layer is less than the first protrusion knot
The height of structure；
Second graph layer, the second graph are formed on first raised structures and on first gallium nitride layer
Layer includes multiple second raised structures, and each second raised structures interconnect；
The material of first graph layer and the second graph layer is the material that can be corroded by wet etching liquid.
Optionally, the thickness of first gallium nitride layer is no more than the 2/3 of the height of first raised structures.
Optionally, each second raised structures cover at least one described first raised structures.
Optionally, the material of first graph layer and/or the second graph layer includes SiO2、SiN、GaAs、
At least one of AlGaAs, AlAs, AlGaInP, AlInP and GaInP.
Optionally, first raised structures and/or second raised structures include the circle packet, sub warhead, cone of bulging
At least one of shape, pyramid, rotary table and bucking ladder structure.
A kind of compound substrate, comprising:
Epitaxial substrate；
The first graph layer being formed in the epitaxial substrate；First graph layer includes multiple mutually isolated first
Raised structures, the multiple the first mutually isolated raised structures are in the presence of there are gaps；
The first gallium nitride layer being formed on the gap, it is prominent that the thickness of first gallium nitride layer is less than described first
Play the height of structure；
It is formed in the second graph layer on first raised structures and on first gallium nitride layer；Second figure
Shape layer includes multiple second raised structures, and each second raised structures interconnect；First graph layer and
The material of the second graph layer is the material that can be corroded by wet etching liquid.
Optionally, the thickness of first gallium nitride layer is no more than the 2/3 of the height of first raised structures.
Optionally, each second raised structures cover at least one described first raised structures.
Optionally, the material of first graph layer and/or the second graph layer includes SiO2、SiN、GaAs、
At least one of AlGaAs, AlAs, AlGaInP, AlInP and GaInP.
A kind of preparation method of light emitting diode chip with vertical, comprising:
Compound substrate is prepared using preparation method described in any of the above-described embodiment；
The second gallium nitride layer, the gallium nitride layer of the first doping type, volume are formed epitaxially one after the other in the compound substrate
Sub- well structure, electronic barrier layer, the second doping type gallium nitride layer and ohmic contact layer；Wherein, first doping type
It is opposite with the conduction type of second doping type；
Conductive layer is formed on the ohmic contact layer；
Metal mirror layer is formed on the conductive layer；
The first surface of electrically-conductive backing plate and the metal mirror layer are linked together；
First graph layer and second graph layer are etched using wet etching method, so that first graph layer and the second figure
Shape layer village hollowing, so that the epitaxial substrate and first gallium nitride layer be peeled off from second gallium nitride layer；
Second gallium nitride layer is etched until exposing the gallium nitride layer of the first doping type, thus in first doping
The production region of first electrode is formed on the gallium nitride layer of type；
First electrode is formed in the production region of the first electrode；
First electrode separation layer is formed around the first electrode, so that the first electrode and the multiple quantum wells
Structure, electronic barrier layer, the gallium nitride layer of the second doping type, ohmic contact layer realize isolation；
Second electrode is formed on the second surface of the electrically-conductive backing plate；The first surface and the second surface phase
It is right.
Compared to the prior art, the application has the advantages that
In the compound substrate prepared by the preparation method of compound substrate provided by the present application, due to being clipped in the first figure
Layer second graph layer between the first gallium nitride layer thickness less than the first raised structures height, so, the first graph layer
On the first raised structures and second graph layer on the second raised structures can be connected with each other perforation, and again due to the second figure
Each second raised structures on shape layer interconnect, in this way, the first graph layer and second graph layer are capable of forming one
The whole figure interconnected that can be corroded by wet etching solution.In this way, wet etching solution is once from compound substrate
When side starts etch pattern layer, it can preferably penetrate into and etch into each raised structures (including the first raised structures and
Two raised structures), so facilitate the corrosion of subsequent epitaxial substrate to remove.
In addition, the first gallium nitride layer being formed between the first graph layer and second graph layer can be regarded as inlaying thereon
There is an integral layer structure of multiple the first mutually isolated raised structures, from the integral layer structure the first raised structures outstanding portion
Divide the nucleus that can be used as subsequent epitaxial layer, thus, which is conducive to grow the preferable gallium nitride of crystal quality
Crystal.The crystal quality of the second gallium nitride layer grown on the preferable gallium nitride of the crystal quality is also preferable, in turn
It can guarantee the crystal quality of the light emitting diode of subsequently epitaxial growing in compound substrate, to guarantee the hair of light emitting diode
Light efficiency.
Detailed description of the invention
In order to which the technical solution of the application is expressly understood, that uses when the application specific embodiment is described below is attached
Figure does a brief description.
Fig. 1 is the preparation method flow diagram of compound substrate provided by the embodiments of the present application；
Fig. 2A to Fig. 2 D is a series of corresponding structural representation of processing procedures in the preparation method of compound substrate provided by the present application
Figure；
Fig. 3 is the flow diagram of the preparation method of vertical structure diode chip for backlight unit provided by the embodiments of the present application；
Fig. 4 A to Fig. 4 J is a series of systems in the preparation method of vertical structure diode chip for backlight unit provided by the embodiments of the present application
The corresponding structural schematic diagram of journey.
Specific embodiment
The specific embodiment of the application is described in detail with reference to the accompanying drawing.
Fig. 1 is the preparation method flow diagram of compound substrate provided by the embodiments of the present application.Fig. 2A to Fig. 2 D is this Shen
A series of corresponding structural schematic diagram of processing procedures in the preparation method for the compound substrate that please be provide.
As shown in Figure 1, the preparation method the following steps are included:
S101, epitaxial substrate 20 is provided:
As an example, the epitaxial substrate can be Sapphire Substrate.In addition, epitaxial substrate can be with are as follows: silicon substrate,
SiC etc. is other III/V, VI race's semiconductor substrate of II/.The structural schematic diagram for the epitaxial substrate 20 that Fig. 2A is to provide.It is to be appreciated that
The epitaxial substrate 20 can be the substrate of surfacing.
S102, the first graph layer 21 is formed in the epitaxial substrate 20, first graph layer 21 includes multiple mutual
First raised structures 211 of isolation, there are gaps 212 between the multiple the first mutually isolated raised structures 211:
This step can be specifically, form the first material using technological means customary in the art in epitaxial substrate 20
Then layer carries out dry etching to the first material layer, form the first graph layer 21.Fig. 2 B (1) and Fig. 2 B (2) is to execute respectively
Corresponding cross section structure schematic diagram and top view after the complete step.
It include multiple the first mutually isolated protrusions on the first graph layer 21 of formation as shown in Fig. 2 B (1) and Fig. 2 B (2)
Structure 211, there are gaps 212 between multiple the first mutually isolated raised structures 211.
In order to erode the first graph layer subsequently through wet etching method, it is used to prepare the material of the first graph layer
Expect the material for that can be corroded by wet etching solution.As an example, the material for being used to prepare the first graph layer may include
SiO2, at least one of SiN, GaAs, AlGaAs, AlAs, AlGaInP, AlInP and GaInP.
It is to be appreciated that multiple the first mutually isolated raised structures 211 being arranged on the first graph layer 21 can be uniform
It is distributed on the first graph layer 21.As an example, the first raised structures 211 may include the drum from the bottom surface of the first graph layer 21
At least one of circle packet, sub warhead, taper, pyramid, rotary table and bucking ladder structure out.
It is to be appreciated that due to mutually isolated between the first raised structures 211, so, be present in the first raised structures 211 it
Between gap 212 can interconnect, formed and one be inlaid with the whole of multiple the first mutually isolated raised structures therebetween
Body structure.
As an example, one layer of SiO can be formed in epitaxial substrate 20 using the method for vapor deposition2Material layer.Then to SiO2
Material layer carries out dry etching, to form the first graph layer 21 including multiple the first mutually isolated raised structures 211.
S103, the first gallium nitride layer 22 is formed on the gap 212, the thickness of first gallium nitride layer 22 is less than institute
State the height of the first raised structures 211:
As an example, as shown in Figure 2 C, technological means customary in the art such as MOCVD (metal oxide can be used
Chemical vapor deposition, metal oxide chemical vapor deposition) gap 212 of the technique in epitaxial substrate 20
Upper the first gallium nitride layer of extension 22, and the thickness of first gallium nitride layer 22 is less than the height of the first raised structures 211, in this way,
First raised structures 211 are not buried by the first gallium nitride layer 22 close to the part of upper end, are exposed to outer.First protrusion
Outer part is exposed in structure 211 to link together with the second raised structures on subsequent second graph layer 23, thus
The first graph layer 21 and second graph layer 23 is set to form integral layer structure.
As an example, the thickness of first gallium nitride layer 22 is no more than the height of first raised structures 211
2/3.As a more specific embodiment, the thickness of first gallium nitride layer 22 is the height of first raised structures 211
2/3.When the thickness of the first gallium nitride layer 22 is the 2/3 of the height of the first raised structures 211, the thickness of the first gallium nitride layer 22
Will not be too thin, in this way, the crystal quality of the first gallium nitride layer 22 formed is preferable, moreover, being exposed to the first outer raised structures
211 can form preferable connection with the second raised structures 231 on the second graph layer 23 that is subsequently formed, so that first
A stable overall structure is capable of forming between raised structures 211 and the second raised structures 231.
It is to be appreciated that in the embodiment of the present application, the first gallium nitride layer 22 of formation is unintentional doped layer, that is, u-GaN.
Since the gap 212 being present between the first raised structures 211 can interconnect, formation one is inlaid with multiple therebetween
The overall structure of the first mutually isolated raised structures 211, so, first be formed on the gap 212 in epitaxial substrate 20
Gallium nitride layer 22 is also integral a layer structure, and multiple the first mutually isolated raised structures are inlaid in the integral layer structure
211。
Since the first gallium nitride layer 22 is integral a layer structure, in this way, the gallium nitride quality formed is preferable, and should
First gallium nitride layer 22 is the nucleating layer of subsequent epitaxial layer, so, preferable first gallium nitride layer 22 of the crystal quality can be protected
The crystal quality of subsequent epitaxial layer is demonstrate,proved, and then can guarantee the luminous efficiency of light emitting diode.
S104, second graph layer 23 is formed on first raised structures 211 and on first gallium nitride layer 22,
The second graph layer 23 includes multiple second raised structures 231:
As shown in Figure 2 D, this step can use evaporated device on the first raised structures 211 and the first gallium nitride layer
Second material layer is formed on 22, dry etching then is carried out to the second material layer, and being formed includes multiple second raised structures 231
Second graph layer 23.
In order to erode second graph layer subsequently through wet etching method, it is used to prepare the material of second graph layer
Expect the material for that can be corroded by wet etching solution.As an example, the material for being used to prepare second graph layer may include
SiO2, at least one of SiN, GaAs, AlGaAs, AlAs, AlGaInP, AlInP and GaInP.
It is to be appreciated that multiple second raised structures 231 being arranged on second graph layer 23 can be evenly distributed on second
On graph layer 23.As an example, the second raised structures 231 may include bloated from the bottom surface of second graph layer 23 circle packet,
At least one of sub warhead, taper, pyramid, rotary table and bucking ladder structure.
When being corroded due to second graph layer 23 by wet solution, etchant solution is to enter second from the side of second graph layer
Graph layer starts to corrode, and therefore, all second raised structures 231 on second graph layer 23 can be corroded in order to subsequent
Solution is eroded, and each second raised structures 231 on second graph layer 23 interconnect, more specifically
Ground says, is usually the small shape in the big top in bottom in view of the second raised structures 231, so, each the on second graph layer 23
The bottom edge of two raised structures 231 interconnects.In this way, etchant solution can be deep into it is each on second graph layer 23
On a second raised structures 231.
Further, since height of the thickness of the first gallium nitride layer 22 less than the first raised structures 211 on the first graph layer 21
Degree, so, be formed in the second raised structures 231 on second graph layer 23 can with below not by the first gallium nitride layer 22
The the first raised structures part buried links together, so that the first graph layer links together with second graph layer, shape
It include the graph layer structure of two layers of graph layer at one.In this way, etchant solution, which once enters, carries out corruption on second graph layer 23
When losing the second raised structures 231, with the progress of corrosion process, etchant solution can also penetrate into each on the first graph layer
First raised structures, so that each first raised structures 211 be eroded.
It is to be appreciated that in order to accelerate wet etching rate, the floor space of the second raised structures 231 is greater than the first raised structures
211 floor space, as more specific embodiment, each second raised structures 231 cover at least two first protrusions
Structure 211.As an example, each second raised structures 231 cover 4 the first raised structures 211.
The above are the specific embodiments of the preparation method of compound substrate provided by the embodiments of the present application.Pass through the specific reality
The compound substrate that the mode of applying is prepared is as shown in Figure 2 D comprising:
Epitaxial substrate 20；
The first graph layer 21 being formed in the epitaxial substrate 20；First graph layer 21 includes multiple mutually isolated
The first raised structures 211, the multiple mutually isolated the first raised structures 211 have that there are gaps 212；
The thickness of the first gallium nitride layer 22 being formed on the gap 212, first gallium nitride layer 22 is less than institute
State the height of the first raised structures 211；
It is formed in the second graph layer 23 on first raised structures 211 and on first gallium nitride layer 22；Institute
Stating second graph layer 23 includes multiple second raised structures 231, and each second raised structures 231 interconnect；
The material of first graph layer and the second graph layer is the material that can be corroded by wet etching liquid.
Can consider by the overall structure of above-mentioned compound substrate: the first gallium nitride layer 22 is clipped in the first graph layer 21 and
Between two graph layers 23, since the thickness for the first gallium nitride layer 22 being clipped between the first graph layer 21 and second graph layer 23 is small
In the height of the first raised structures 211, so, 23 on the first raised structures 211 and second graph layer on the first graph layer 21
The second raised structures 231 can be connected with each other perforation, and again due to each second raised structures on second graph layer 23
231 interconnect, in this way, the first graph layer 21 and second graph layer 23 be capable of forming one it is whole it is interconnected can quilt
The figure that wet etching solution is corroded.In this way, wet etching solution once since the side of compound substrate etch pattern layer
When, it can preferably penetrate into and etch into each raised structures (including the first raised structures 211 and second raised structures 231),
So the corrosion of subsequent epitaxial substrate 20 is facilitated to remove.
In addition, the first gallium nitride layer 22 being formed between the first graph layer 21 and second graph layer 23 can be regarded as it
On be inlaid with an integral layer structure of multiple the first mutually isolated raised structures 211, from the integral layer structure outstanding first
211 part of raised structures can be used as the nucleus of subsequent epitaxial layer, thus, which is conducive to grow crystal quality
Preferable gallium nitride.The crystal matter of the second gallium nitride layer 24 grown on the preferable gallium nitride of the crystal quality
Amount is also preferable, and then can guarantee the crystal quality of the light emitting diode of subsequently epitaxial growing in compound substrate, to guarantee
The luminous efficiency of light emitting diode.
Compound substrate provided based on the above embodiment and preparation method thereof, the embodiment of the present application also provides a kind of vertical
The specific embodiment of the preparation method of structure light-emitting diode chip.
Two pole of vertical structure light-emitting provided by the embodiments of the present application is described in detail in 3 and Fig. 4 A to Fig. 4 J with reference to the accompanying drawing
The specific embodiment of the preparation method of tube chip.
Fig. 3 is the flow diagram of the preparation method of vertical structure diode chip for backlight unit provided by the embodiments of the present application.Fig. 4 A
It is the corresponding structure of processing procedures a series of in the preparation method of vertical structure diode chip for backlight unit provided by the embodiments of the present application to Fig. 4 J
Schematic diagram.
As shown in figure 3, the preparation method of vertical structure diode chip for backlight unit provided by the present application the following steps are included:
S301, compound substrate 40 is prepared using compound substrate preparation method described in any of the above-described embodiment:
As shown in Figure 4 A, the structure of compound substrate 40 is identical as the structure for the compound substrate that above-described embodiment is prepared.
S302, the second gallium nitride layer 41, n type gallium nitride layer 42, volume are formed epitaxially one after the other in the compound substrate 40
Sub- well structure 43, electronic barrier layer 44, p-type gallium nitride layer 45 and ohmic contact layer 46:
As shown in Figure 4 B, the second nitridation is formed epitaxially one after the other in compound substrate 40 using technological means customary in the art
Gallium layer 41, n type gallium nitride layer 42,43, electronic barrier layer EBL multi-quantum pit structure MQW (multiple quantum well)
(electron-blocking layer) 44, p-type gallium nitride layer 45 and ohmic contact layer 46.
S303, conductive layer 47 is formed on the ohmic contact layer 46:
As shown in Figure 4 C, conductive layer 47 is formed on ohmic contact layer 46.More specifically, the material of the conductive layer 47 is
ITO。
S304, metal mirror layer 48 is formed on the conductive layer 47:
As shown in Figure 4 D, metal mirror layer 48 is formed on conductive layer 47.
S305, the first surface of electrically-conductive backing plate 49 and the metal mirror layer 48 are linked together:
It is to be appreciated that electrically-conductive backing plate 49 includes opposite first surface and second surface.By the first table of electrically-conductive backing plate 49
Face links together with metal mirror layer 48.As an example, can be using bonding technology the first surface of electrically-conductive backing plate 49
It is bonded on the metal mirror layer 48.As an example, electrically-conductive backing plate 49 can be silicon substrate.One as the application is specific
The first surface of electrically-conductive backing plate 48 is bonded in metal mirror layer 48 using flip chip bonding process as shown in Figure 4 E by embodiment
On.
S306, the first graph layer 21 and second graph layer 23 are etched using wet etching method, so that first figure
Layer 21 and 23 village hollowing of second graph layer, thus by the epitaxial substrate 20 and first gallium nitride layer 22 from described second
It is peeled off on gallium nitride layer 41:
This step can be with specifically: S301 through the above steps to the S305 structure formed is immersed in etchant solution,
And etchant solution is shaken, to accelerate wet etching rate, etchant solution is made to etch the first graph layer 21 and second graph layer 23, with
Make 23 village hollowing of first graph layer 21 and second graph layer, thus by the epitaxial substrate 20 and first gallium nitride
Layer 22 is peeled off from second gallium nitride layer 41.Execute the step corresponding structural schematic diagram such as Fig. 4 F institute after S306
Show.
It is to be appreciated that wet etching solution corrodes since the side of second graph layer 23, due to the first graph layer and
Two graph layers 23, which pass through, is respectively set the first raised structures 211 on it and the second raised structures 231 are joined together to form
One integral layer structure, so, once etchant solution starts to corrode the second raised structures on second graph layer 23, with corroding
The progress of journey, the etchant solution can penetrate into the inside of the first raised structures 211, realize the corruption to the first raised structures 211
Erosion, so as to realize the village hollowing of the first graph layer 21 and second graph layer 23, thus by the epitaxial substrate 20 and institute
The first gallium nitride layer 22 is stated to peel off from second gallium nitride layer 41.
S307, etching second gallium nitride layer 41 are until expose n type gallium nitride layer 42, thus in the n type gallium nitride
The production region 410 of first electrode is formed on layer 42:
As an example, ICP (inductively coupled plasma, inductively coupled plasma) engraving method can be used
Second gallium nitride layer 41 is etched until exposing n type gallium nitride layer 42, to form first on the n type gallium nitride layer 42
The production region 410 of electrode.It is as shown in Figure 4 G that the step has executed corresponding structural schematic diagram.
S308, first electrode 411 is formed in the production region 410 of the first electrode:
First electrode 411 is formed on the production region 410 of first electrode using technological means customary in the art.The step
Suddenly corresponding structural schematic diagram has been executed as shown at figure 4h.
S309, first electrode separation layer 412 is formed around the first electrode 411, so that the first electrode 411
It is isolated with the multi-quantum pit structure 43, electronic barrier layer 44, p-type gallium nitride layer 45, the realization of ohmic contact layer 46:
First electrode separation layer 412 is formed around the first electrode 411 using technological means customary in the art,
So that the first electrode 411 and the multi-quantum pit structure 43, electronic barrier layer 44, p-type gallium nitride layer 45, ohmic contact layer
46 realize isolation.The step has executed corresponding structural schematic diagram as shown in fig. 41.
S310, second electrode 413 is formed on the second surface of the electrically-conductive backing plate 49.
Second electrode is formed on the un-joined surfaces of the electrically-conductive backing plate 49 using technological means customary in the art
413.The step has executed corresponding structural schematic diagram as shown in fig. 4j.
The above are the specific embodiment parties of the preparation method of light emitting diode chip with vertical provided by the embodiments of the present application
Formula.
The method for realizing the removing of substrate in compared to the prior art using laser lift-off mode, the present invention are rotten using wet process
Etching method realizes that the mode of the removing of substrate has the advantage that
The application is removed at peeling liner bottom using wet etching method, and wet etching equipment is compared to source, laser apparatus
It is standby that cost is relatively low.
Due to instead of laser lift-off technique, the specific embodiment can be avoided in laser lift-off due to
The caused fragment phenomenon of the problems such as bonding technology is uneven, improves the yields of thin-film LED.
In addition, the epitaxial substrate that the application uses can be semiconductor substrate customary in the art, in this way, vertical for preparation
Structure light-emitting diode provides wider raw material selection.In addition, the epitaxial substrate is not limited to SiC substrate, it therefore, should
Preparation method also has the advantages that low manufacture cost and raw material sources are reliable.
In addition, in the compound substrate that the application uses, be formed between the first graph layer 21 and second graph layer 23 the
One gallium nitride layer 22 can be regarded as the integral layer structure for being inlaid with multiple the first mutually isolated raised structures 211 thereon,
It can be used as the nucleus of subsequent epitaxial layer from the integral layer structure the first raised structures outstanding part, thus, the integral layer knot
Structure is conducive to grow the preferable gallium nitride of crystal quality.It is grown on the preferable gallium nitride of the crystal quality
The crystal quality of second gallium nitride layer 24 is also preferable, and then can guarantee the light-emitting diodes of the subsequently epitaxial growing in compound substrate
The crystal quality of pipe, so that the luminous efficiency of light emitting diode is higher.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710224742.6A CN106816509B (en) | 2017-04-07 | 2017-04-07 | Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710224742.6A CN106816509B (en) | 2017-04-07 | 2017-04-07 | Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106816509A CN106816509A (en) | 2017-06-09 |
| CN106816509B true CN106816509B (en) | 2018-12-21 |
Family
ID=59116494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710224742.6A Active CN106816509B (en) | 2017-04-07 | 2017-04-07 | Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106816509B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108878596B (en) * | 2018-05-29 | 2020-12-15 | 河源市众拓光电科技有限公司 | A transfer method of vertical structure LED chip substrate with no edge loss |
| CN114464712B (en) * | 2022-03-21 | 2025-10-31 | 厦门乾照光电股份有限公司 | Epitaxial structure, LED chip and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100414005C (en) * | 2001-02-14 | 2008-08-27 | 丰田合成株式会社 | Manufacturing method of semiconductor crystal and semiconductor light emitting element |
| CN101572283A (en) * | 2008-05-04 | 2009-11-04 | 先进开发光电股份有限公司 | Method for manufacturing three-group nitrogen compound semiconductor light-emitting component and structure thereof |
| US20150069418A1 (en) * | 2012-03-19 | 2015-03-12 | Seoul Viosys Co., Ltd. | Method for separating epitaxial layers and growth substrates, and semiconductor device using same |
| CN105633222A (en) * | 2014-11-06 | 2016-06-01 | 展晶科技(深圳)有限公司 | Method for manufacturing vertical light-emitting diode |
-
2017
- 2017-04-07 CN CN201710224742.6A patent/CN106816509B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100414005C (en) * | 2001-02-14 | 2008-08-27 | 丰田合成株式会社 | Manufacturing method of semiconductor crystal and semiconductor light emitting element |
| CN101572283A (en) * | 2008-05-04 | 2009-11-04 | 先进开发光电股份有限公司 | Method for manufacturing three-group nitrogen compound semiconductor light-emitting component and structure thereof |
| US20150069418A1 (en) * | 2012-03-19 | 2015-03-12 | Seoul Viosys Co., Ltd. | Method for separating epitaxial layers and growth substrates, and semiconductor device using same |
| CN105633222A (en) * | 2014-11-06 | 2016-06-01 | 展晶科技(深圳)有限公司 | Method for manufacturing vertical light-emitting diode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106816509A (en) | 2017-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10644200B2 (en) | Vertical topology light emitting device | |
| US7465592B2 (en) | Method of making vertical structure semiconductor devices including forming hard and soft copper layers | |
| JP5165276B2 (en) | Vertical structure gallium nitride based light-emitting diode device and method of manufacturing the same | |
| CN102067339B (en) | A method of preparing InGaAlN light-emitting diode with metal substrate | |
| CN102017193B (en) | Semiconductor light-emitting device with double-sided passivation | |
| JP2012500479A (en) | Method for manufacturing a semiconductor light-emitting device with double-sided passivation | |
| CN102067340B (en) | Semiconductor light-emitting device with passivation in p-type layer | |
| TW201547053A (en) | Method of forming a light emitting device | |
| CN106816509B (en) | Compound substrate and preparation method thereof, the preparation method of light-emitting diode chip for backlight unit | |
| US20060284188A1 (en) | Light-emitting diode and method for manufacturing the same | |
| JP5281536B2 (en) | Manufacturing method of semiconductor light emitting device | |
| WO2015027654A1 (en) | Method for preparing gallium nitride-based high-voltage light-emitting diode | |
| CN109326702A (en) | A kind of LED chip with annular electrode structure and preparation method thereof | |
| TWI817264B (en) | Vertical light-emitting diode and manufacturing method thereof | |
| KR20120029279A (en) | Manufacturing method for nitride single crystal and nitride semiconductor light emitting device | |
| WO2022099501A1 (en) | Vertical structure light emitting diode and preparation method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |