CN106816416B - Semiconductor embedded hybrid packaging structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor embedded hybrid packaging structure and a manufacturing method thereof. The packaging structure comprises: a circuit board, which has a first surface and a second surface arranged oppositely; Openings or cavities of semiconductor chips (Bare Die) and semiconductor chip packages (Semiconductor Package); semiconductor chips arranged in openings or cavities; semiconductor chip packages arranged in openings or cavities; packaging materials, at least with It covers the first surface of the circuit board and fills the space not occupied by the semiconductor chip and the semiconductor chip package in the opening or cavity; the redistribution layer is at least used to electrically connect the semiconductor chip, the semiconductor chip package and the circuit board. The semiconductor embedded hybrid packaging structure and its manufacturing method in the present invention adopt the circuit board embedded technical scheme, which can simplify the integration process of the semiconductor chip and the semiconductor chip package, improve the integration quality and performance, and effectively reduce the integration area.

Description

Semiconductor embedded hybrid package structure and fabrication method thereof

technical field

The invention relates to a circuit carrier board packaging structure, in particular to a semiconductor embedded hybrid packaging structure and a manufacturing method thereof.

Background technique

In the prior art, the packaging of the semiconductor chip and the assembly of the semiconductor chip package are completed by an electronic packaging factory and an electronic assembly factory respectively. The packaging of the semiconductor chip is completed first, and then the semiconductor chip package is assembled on the circuit board. The assembly of the semiconductor chip package on the circuit board is usually completed by a surface mount process.

Surface Mount Technology (SMT) is a method of mounting leadless or short lead surface mount components (SMC/SMD for short, chip components in Chinese) on a printed circuit board (Printed CircuitBoard, PCB). A circuit assembly technology that is soldered and assembled on the surface or the surface of other substrates by means of reflow soldering or dip soldering. Surface mount technology has high assembly density, small size and light weight of electronic products. The volume and weight of SMD components are only about 1/10 of those of traditional plug-in components. Generally, after SMT is used, the volume of electronic products is reduced by 40% to 60%. The weight is reduced by 60% to 80%. The assembly of the semiconductor packaged devices on the circuit board is usually completed through surface mount engineering. During the surface mount process, the semiconductor packaged devices and the circuit board are usually electrically interconnected through solder connections.

However, the packaging between the semiconductor chip and the semiconductor chip package and the circuit board in the prior art has the following deficiencies:

The docking standard and process between the semiconductor chip/semiconductor chip package and the circuit board are complex and cumbersome;

Generally, semiconductor chips need to be packaged into semiconductor package devices before being mounted/soldered on printed circuit boards. In addition, on the surface mount, the semiconductor chip package and the circuit board are usually electrically interconnected by solder connection. At present, the solder connection of the surface mount requires a larger pitch between the pads and the pads of the semiconductor package, such as soldering. Disk/pad spacing = 280 microns/400 microns, the precision needs to be improved, and the solder connection requires more complicated solder reflow process control;

In addition, the semiconductor chip package is assembled on the circuit board using the surface mount method. Since the area of the semiconductor chip package increases, it will occupy a larger surface area of the circuit board, hindering the development of miniaturization of the assembly of the semiconductor package device.

Therefore, there is an urgent need to provide a new semiconductor embedded hybrid package structure and a manufacturing method thereof to solve the above problems.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a semiconductor embedded hybrid package structure and a manufacturing method thereof, which can effectively improve the problems of large pads and pad spacings of the semiconductor chip package and miniaturization of the package structure.

In order to solve the above technical problems, a semiconductor embedded hybrid packaging structure provided in a technical solution adopted by the present invention is characterized in that, the packaging structure includes:

a circuit board, which has a first surface and a second surface arranged oppositely;

an opening or cavity provided in the circuit board at least for accommodating a semiconductor chip and a semiconductor chip package;

a semiconductor chip disposed in the opening or cavity;

a semiconductor chip package disposed in the opening or cavity;

packaging material, at least used to cover the first surface of the circuit board and fill the space in the opening or cavity that is not occupied by the semiconductor chip and the semiconductor chip package;

The redistribution layer is at least used to electrically connect the semiconductor chip, the semiconductor chip package and the circuit board.

In a preferred embodiment, the first surface of the circuit board is provided with a module alignment mark, and the surface of the module alignment mark and the second surface of the circuit board correspond to the highest surface and the lowest surface of the circuit board, respectively. .

In a preferred embodiment, a passive electronic element is further provided in the opening or cavity, and the passive electronic element includes any one or a combination of capacitance, resistance and inductance elements.

In a preferred embodiment, the semiconductor chip package has at least one semiconductor bare chip, and is a semiconductor chip package with a plastic sealing material package.

Further, the semiconductor chip package includes conductive leads or wirings that are electrically connected to electrodes/pads of a semiconductor die within the semiconductor chip package and extend outward from the semiconductor die.

Further, the semiconductor chip package also includes an external electrode electrically connected to the semiconductor bare wafer, and the external electrode is exposed in the air or covered by a film; the material of the external electrode is a copper metal layer or A copper metal layer covered with a nickel/gold layer; the material of the film is an accumulation layer dielectric material, including a plastic sealing material, a build-up material, or a polyimide.

Further, the encapsulation material is also used to fill the space in the opening or cavity that is not occupied by passive electronic components.

In a preferred embodiment, the packaging structure further includes a first accumulation layer covering at least the second surface of the circuit board, the packaging material, the semiconductor chip, and the semiconductor chip package; the The first accumulation layer is a dielectric material layer, including an ABF build-up layer or a photosensitive dielectric layer.

Further, the first accumulation layer is provided with blind holes above the electrodes/pads of the semiconductor chip, the external electrodes of the semiconductor chip package and the circuit layer of the circuit board; the first accumulation layer is provided with a first rewiring layer, and the first redistribution layer on the first accumulation layer is electrically interconnected with the electrodes/pads of the semiconductor chip, the external electrodes of the semiconductor chip package and/or the circuit layers on the circuit board through the blind holes.

Further, a second redistribution layer is also provided on the packaging material on the first surface of the circuit board, and the second redistribution layer is connected to at least the circuit layer, the semiconductor chip, and/or the circuit layer on the circuit board through the conductive blind vias. External electrodes of the semiconductor chip package are electrically interconnected.

Further, the first redistribution layer and/or the second redistribution layer is covered with a second accumulation layer, and the second accumulation layer is formed with electrical connections with the first redistribution layer and/or the second redistribution layer. A third redistribution layer of the interconnect, the second accumulation layer comprising an ABF build-up layer or a photosensitive dielectric layer.

Further, the package structure further includes a solder mask covering at least the outermost circuit layer, and an opening provided in the solder mask; the circuit layer in the mask opening forms a pad for connecting external components.

Further, the package structure further includes a semiconductor package device and/or a passive electronic element mounted on the solder mask, and the passive electronic element includes any one or a combination of capacitors, resistors, and inductance elements, so The semiconductor packaged devices and/or passive electronic components are electrically interconnected through the pads and the third redistribution layer.

Another technical solution adopted by the present invention provides a method for fabricating a semiconductor embedded hybrid packaging structure, the fabrication method comprising the following steps:

S1. Provide a circuit board, which has a first surface and a second surface disposed opposite to each other, and the circuit board is provided with at least an opening or a cavity for accommodating a semiconductor chip and a semiconductor chip package;

S2, attaching an adhesive film on the second surface of the circuit board, placing the semiconductor chip and the semiconductor chip package into the opening or cavity, and making the semiconductor chip and the semiconductor chip package and the Adhesive film bonding and fixing;

S3. Apply a packaging material on at least the first surface of the circuit board and the opening or cavity, so that the first surface of the circuit board is covered with the packaging material, and the opening or the cavity is covered with the packaging material and the semiconductor chip and the semiconductor chip package are completely filled;

S4, removing the adhesive film, and turning the circuit board over;

S5, covering one or more accumulation layers on the second surface of the circuit board, the semiconductor chip, the semiconductor chip package and the surface of the packaging material coplanar with the second surface of the circuit board;

S6. At least a redistribution layer for electrically connecting the semiconductor chip, the semiconductor chip package, and the circuit board is formed on the accumulation layer.

The step S6 provided in another technical solution adopted by the present invention includes:

Blind holes are provided in the first accumulation layer located above the electrodes/pads of the semiconductor chip, the external electrodes of the semiconductor chip package and the circuit layer of the circuit board, and the electrodes/pads and the semiconductor chips are formed through the blind holes and the semiconductor chips. a first redistribution layer for electrical interconnection of the external electrodes of the package body and/or the circuit layers on the circuit board;

A second redistribution layer is provided on the encapsulation material on the first surface of the circuit board; the second redistribution layer passes through conductive blind holes and external electrodes of the circuit layer, the semiconductor chip, and/or the semiconductor chip package on the circuit board electrical interconnection;

A second accumulation layer is formed on the first redistribution layer and/or the second redistribution layer, and conductive blind vias are arranged on the second accumulation layer, and the first redistribution layer and/or the first redistribution layer and/or the first redistribution layer are electrically connected through the conductive blind vias. The third redistribution layer of the double wiring layer.

Further, after the step S6, it also includes:

A solder mask is formed on the outermost circuit layer of the package structure, and an opening is formed on the solder mask above the circuit layer to form a corresponding pad;

A semiconductor packaged device and/or passive electronic component is mounted over the solder mask, the semiconductor packaged device and/or passive electronic component being electrically interconnected with the third redistribution layer through the pads.

Compared with the prior art, the present invention has at least the following advantages:

The packaging and processing of the semiconductor chip and the semiconductor package are completed on the circuit board at the same time, which omits the complex and cumbersome standards and process docking of the two in the prior art, reduces the circulation and transfer of electronic manufacturing, saves manpower and material resources, and can further reduce the cost of electronic products ;

The electrical connection between the semiconductor chip and the circuit board and the semiconductor chip package and the circuit board does not require a solder connection scheme, but adopts a simple copper redistribution (RDL) scheme, which has stable process and high reliability;

It can meet the assembly requirements of more precise semiconductor chips and semiconductor chip packages, such as the pad/pad spacing of semiconductor chips or semiconductor chip packages can be reduced to less than 150 microns/200 microns;

The embedded assembly of the semiconductor chip and the semiconductor chip package fully releases the surface area of the circuit board, and can achieve a significant reduction in the system assembly area, and the reduction ratio can exceed 50%.

Description of drawings

1 is a schematic structural diagram of a semiconductor embedded hybrid package structure in a preferred embodiment of the present invention;

1a-1m are process step diagrams of a method for fabricating a semiconductor embedded hybrid package structure in a preferred embodiment of the present invention, wherein:

1a is a schematic structural diagram of a circuit board in a preferred embodiment of the present invention;

Fig. 1b is a schematic diagram of the installation of a semiconductor chip and a semiconductor chip package in a preferred embodiment of the present invention;

FIG. 1c is a schematic diagram of a packaging structure of a semiconductor chip package in a preferred embodiment of the present invention;

1d is a schematic diagram of the package structure after the semiconductor chip and the semiconductor chip package are installed in a preferred embodiment of the present invention;

1e is a schematic diagram of a package structure including packaging materials in a preferred embodiment of the present invention;

1f is a schematic diagram of the package structure after the circuit board including the packaging material is inverted in a preferred embodiment of the present invention;

1g is a schematic diagram of a package structure including a first accumulation layer in a preferred embodiment of the present invention;

1h is a schematic diagram of a package structure of blind holes on the first accumulation layer and the packaging material in a preferred embodiment of the present invention;

1i is a schematic diagram of a package structure including a first redistribution layer and a second redistribution layer in a preferred embodiment of the present invention;

1j is a schematic diagram of a package structure including a second accumulation layer in a preferred embodiment of the present invention;

1k is a schematic diagram of a package structure including a third redistribution layer in a preferred embodiment of the present invention;

11 is a schematic diagram of a package structure including a solder mask in a preferred embodiment of the present invention;

FIG. 1m is a schematic structural diagram of a semiconductor chip and a semiconductor chip package after embedded packaging in a preferred embodiment of the present invention to complete the surface mount of passive components;

2 is a schematic structural diagram of a semiconductor embedded hybrid packaging structure in another preferred embodiment of the present invention;

2a-2l are process step diagrams of a method for fabricating a semiconductor embedded hybrid package structure in another preferred embodiment of the present invention, wherein:

Figure 2a is a schematic structural diagram of a circuit board in another preferred embodiment of the present invention;

Figure 2b is a schematic diagram of the installation of a semiconductor chip, a semiconductor chip package and a passive electronic component in another preferred embodiment of the present invention;

2c is a schematic diagram of the package structure of the semiconductor chip, the semiconductor chip package body and the passive electronic component after installation in another preferred embodiment of the present invention;

2d is a schematic diagram of a package structure including a package material in another preferred embodiment of the present invention;

2e is a schematic diagram of the package structure after the circuit board including the packaging material is inverted in another preferred embodiment of the present invention;

2f is a schematic diagram of a package structure including a first accumulation layer in another preferred embodiment of the present invention;

2g is a schematic diagram of a package structure of blind holes in the first accumulation layer and the packaging material in another preferred embodiment of the present invention;

2h is a schematic diagram of a package structure including a first redistribution layer and a second redistribution layer in another preferred embodiment of the present invention;

2i is a schematic diagram of a package structure including a second accumulation layer in another preferred embodiment of the present invention;

2j is a schematic diagram of a package structure including a third redistribution layer in another preferred embodiment of the present invention;

2k is a schematic diagram of a package structure including a solder mask in another preferred embodiment of the present invention;

FIG. 21 is a schematic structural diagram of surface mounting of passive components after a semiconductor chip and a semiconductor chip package are embedded and packaged in another preferred embodiment of the present invention.

The components in the drawings are marked as follows: 1-circuit board, 11-first surface, 12-second surface, 13-circuit layer, 2-opening or cavity, 21-first space, 22-second space, 31-Semiconductor chip, 32-Semiconductor chip package, 321-Semiconductor bare wafer, 322-Plastic packaging material, 323-Internal conductive lead or wiring, 324-External electrode, 4-Packaging material, 5-Module alignment mark, 6- Redistribution layer, 61-first redistribution layer, 62-second redistribution layer, 63-third redistribution layer, 7-passive electronic components, 81-first accumulation layer, 82-second accumulation layer, 811, 812 , 813-opening, 10-solder mask, 101-semiconductor package device and/or passive electronic component, 201-adhesive film.

Detailed ways

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, and the protection scope of the present invention can be more clearly defined.

The semiconductor embedded hybrid packaging structure in a specific embodiment of the present invention, as shown in FIG. 1 , the packaging structure specifically includes:

A circuit board 1, that is, a circuit carrier for packaging a semiconductor chip (Bare Die) and a semiconductor chip package (Semiconductor Package), which has a first surface 11 and a second surface 12 disposed oppositely;

at least one opening or cavity 2 provided in the circuit board 1 for accommodating a semiconductor chip 31 and at least one for accommodating a semiconductor chip package 32;

the semiconductor chip 31 and the semiconductor chip package 32 disposed in the opening or cavity 2;

The packaging material 4 is used at least to cover the first surface 11 of the circuit board, the module alignment mark 5 and to fill the space in the opening or cavity 2 that is not occupied by the semiconductor chip 31 and the semiconductor chip package 32;

The redistribution layer 6 is used for at least electrically connecting the semiconductor chip 31 , the semiconductor chip package 32 and the circuit board 1 .

1a and 1b, the first surface 11, the second surface 12, and the area between the first surface 11 and the second surface 12 of the circuit board are respectively provided with a circuit layer 13, and the module alignment mark 5 is provided on the The first surface of the circuit board 1, and the surface of the module alignment mark 5 and the second surface of the circuit board correspond to the highest surface and the lowest surface of the circuit board, respectively. The module alignment mark 5 is used to realize precise arrangement of semiconductor chips, semiconductor chip packages and interconnection of conductive lines, and all or part of the marks can simultaneously become connection lines and provide conductive functions.

The highest surface and the lowest surface of the opening or cavity 2 in the vertical direction are respectively the highest surface of the circuit board 1 or the surface of the module alignment mark 5 and the second surface 12 of the circuit board 1 or its The lowermost surface, and the boundary of the opening or cavity 2 in the horizontal direction is the opening of the circuit board 1 between the first surface 11 and the second surface 12 or the side wall of the cavity 2, while the opening or The cavity 2 includes a first space 21 and a second space 22, wherein the first space 21 is distributed between the first surface 11 and the second surface 12 of the circuit board 1, and the second space 22 is distributed in all the Between the first surface 11 of the circuit board 1 and the surface of the module alignment mark 5, and the side wall of the first space 21 is the circuit board between the first surface 11 and the second surface 12 of the circuit board 1 has a continuous section, and the second space 21 has no side walls.

As shown in FIG. 1 c , the semiconductor chip package 32 contains at least one semiconductor bare chip 321 . Among them, a semiconductor bare wafer is a type of semiconductor device that is made by etching, wiring, etc. on a semiconductor sheet, and can realize a specific function. The semiconductor chip package body 32 can be obtained by plastic-encapsulating the above-mentioned semiconductor bare chip 321 with the plastic-encapsulating material 322 . The semiconductor chip package 32 is disposed in the opening or cavity 2 . The semiconductor chip package 32 includes electrodes/pads electrically connected to the semiconductor die 321 in the semiconductor chip package and extends outward from the semiconductor die 321 . The package internal conductive leads or wirings 323 and external electrodes 324 are electrically interconnected with electrodes/pads on the semiconductor die 321 in the semiconductor chip package via the internal conductive leads or wirings. The external electrode 324 of the semiconductor chip package may be a metal copper layer or a metal copper layer covered with a nickel/gold layer. The semiconductor chip package 32 may be a semiconductor chip package having a package structure such as InFO, WLCSP, eWLB, FOWLP, FC-BGA, FC-CSP, WB-BGA, QFN, or the like.

Further, in the present invention, the external electrode 324 of the semiconductor chip package 32 is exposed in the air or covered by a film; the external electrode 324 is a copper metal layer or a copper metal layer covered with a nickel/gold layer; The material of the film is an accumulation layer dielectric material, which may be a plastic packaging material, a build-up layer material, or other accumulation layer dielectric materials such as polyimide.

In this embodiment, the package structure further includes a first accumulation layer 81 covering at least the second surface 12 of the circuit board 1 , the packaging material 4 , the semiconductor chip 31 and the semiconductor chip package 32 ; The accumulation layer 81 is a dielectric material layer, including an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layers.

As shown in FIG. 1i, the first accumulation layer 81 is provided with blind holes above the circuit layers of the semiconductor chip, the external electrodes of the semiconductor chip package and the circuit board; the first accumulation layer is provided with the first redistribution layer 61, and all The first redistribution layer 61 on the first accumulation layer 81 is electrically interconnected with the semiconductor chip, the external electrodes of the semiconductor chip package, and the circuit layer on the circuit board through the blind hole. A second redistribution layer 62 is further provided on the packaging material 4 on the first surface 11 of the circuit board, and the second redistribution layer 62 passes through the conductive blind holes and the circuit layers, semiconductor chips, and/or semiconductor chips on the circuit board The package external electrodes 324 are electrically interconnected.

Further, as shown in FIGS. 1j and 1k, the first redistribution layer 61 and the second redistribution layer 62 are covered with a second accumulation layer 82, and the second accumulation layer 82 is formed with the first redistribution layer respectively. The third redistribution layer 63 is electrically interconnected with the second redistribution layer, wherein the second accumulation layer is an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layers.

In addition, the package structure further includes a solder mask 10 covering at least the outermost circuit layer, an opening of the solder mask disposed above the outermost circuit layer, and the pads formed in the opening are mounted on the solder mask 10 There are other semiconductor packaged devices and/or passive electronic components 101, and passive electronic components include but are not limited to capacitors, resistors, inductors and other components. The semiconductor packaged devices and/or passive electronic components 101 are electrically connected to the third redistribution layer through the pads. interconnection. In this embodiment, the first accumulation layer and the second accumulation layer are both ABF build-up layers for illustration. In other embodiments, the first accumulation layer and the second accumulation layer may also be layers of other dielectric materials.

The above embodiment is only a preferred embodiment of the present invention, and it should be understood that in other embodiments, the first accumulation layer, the second accumulation layer, the first redistribution layer, the second redistribution layer and the third redistribution layer It can be set selectively, for example, only the first accumulation layer, the first redistribution layer and the second redistribution layer are set; in addition, other interconnections for electrical connection can be further set in addition to the above accumulation layer and redistribution layer As long as other semiconductor package devices and/or passive electronic components 101 are electrically connected to the semiconductor chip, semiconductor chip package or circuit board, the package structure belongs to the scope of protection of the present invention.

Another aspect of the present invention also provides a method for fabricating a semiconductor embedded hybrid package structure, comprising the following steps:

S1. Provide a circuit board, which has a first surface and a second surface disposed opposite to each other, the circuit board is provided with at least one opening or cavity for accommodating a semiconductor chip and a semiconductor chip package, and the circuit board is provided with at least one opening or cavity. A module alignment mark is arranged around the opening or cavity on the first surface of the board;

S2. Attach an adhesive film on the second surface of the circuit board, place the semiconductor chip and the semiconductor chip package into the opening or cavity, and make the semiconductor chip package and the adhesive film bonding and fixing;

S3. Apply a packaging material on at least the first surface of the circuit board, the module alignment mark, and the opening or cavity, so that the first surface of the circuit board and the module alignment mark are covered by the packaging material, and make the opening or cavity is completely filled with packaging material and the semiconductor chip and semiconductor chip package;

S4, removing the adhesive film, and turning the circuit board over;

S5, covering one or more accumulation layers on the second surface of the circuit board, the semiconductor chip, the semiconductor chip package and the surface of the packaging material coplanar with the second surface of the circuit board;

S6. At least a redistribution layer for electrically connecting the semiconductor chip, the semiconductor chip package and the circuit board is formed on the accumulation layer.

Specifically, a method for fabricating a semiconductor embedded hybrid package structure in a preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 1a, a circuit board 1 is provided, which has a first surface 11 and a second surface 12 disposed opposite to each other, the first surface 11, the second surface 12 of the circuit board, and the first surface 11 and the second surface 12 on the first surface 11 and the second surface 12 are provided. The areas in between are respectively provided with circuit layers 13 . The circuit board 1 includes at least one opening or cavity 2 for accommodating the semiconductor chip 31 and the semiconductor chip package 32 . Preferably, this embodiment includes a plurality of openings or cavities 2 for accommodating the semiconductor chip 31 and the semiconductor chip package 32 respectively.

The module alignment mark 5 is disposed on the first surface of the circuit board 1 , and the surface of the module alignment mark 5 and the second surface of the circuit board correspond to the highest surface and the lowest surface of the circuit board, respectively.

1b and 1d, an adhesive film 201 is attached to the second surface 12 of the circuit board 1, and the semiconductor chip 31 and the semiconductor chip package 32 are placed in the opening or cavity 2 in an inverted state. , and the external electrodes of the semiconductor chip package 3 and the adhesive film 201 are bonded and fixed in the opening or cavity 2 .

The schematic structural diagram of the semiconductor chip package 32 in this embodiment is shown in FIG. 1 c , and the semiconductor chip package 32 has at least one semiconductor bare chip 321 therein. Among them, a semiconductor bare wafer is a type of semiconductor device that is made by etching, wiring, etc. on a semiconductor sheet, and can realize a specific function. The semiconductor chip package body 32 can be obtained by plastic-encapsulating the above-mentioned semiconductor bare chip 321 with the plastic-encapsulating material 322 . The semiconductor chip package 32 is disposed in the opening or cavity 2 . The semiconductor chip package 32 includes electrodes/pads electrically connected to the semiconductor die 321 in the semiconductor chip package and extends outward from the semiconductor die 321 . The package internal conductive leads or wirings 323 and external electrodes 324 are electrically interconnected with electrodes/pads on the semiconductor die 321 in the semiconductor chip package via the internal conductive leads or wirings.

Referring to FIG. 1e, a layer of packaging is formed by plastic sealing on the first surface 11 of the circuit board, above the module alignment mark 5, and filling the space in the opening or cavity 2 that is not occupied by the semiconductor chip 31 and the semiconductor chip package 32. Material 4.

In this step, the encapsulation material 4 may also be planarized.

Wherein, the encapsulation material 4 may be a molding compound, epoxy resin, or epoxy resin/filler compound, etc., which fills the opening or cavity 2 and covers the first layer of the circuit board 1 as a flat build-up layer. a surface 11 .

Referring to FIG. 1f, the adhesive film 201 is removed, and the circuit board 1 is turned over.

1g, 1h and 1i, a second surface covering at least the second surface 12 of the circuit board 1, the packaging material 4, the semiconductor chip 31 and the semiconductor chip package 32 is formed on the second surface 12 of the circuit board 1 after being turned over. An accumulation layer 81 is removed, and the first accumulation layer 81 above the electrodes of the semiconductor chip 31 and the external electrodes 32 of the semiconductor chip package 3 is removed to form openings 811 . Then, the first redistribution layer 61 (RDL) is formed on the first accumulation layer 81 through the opening 811; similarly, the surface of the encapsulation material 4 on the first surface 11 of the circuit board 1 can also be removed by the laser opening process. An opening 812 is formed on the encapsulation material, and a second redistribution layer 62 is formed on the encapsulation material through the opening 812 . The formation method of the redistribution layer includes a series of processes of metal deposition, dry film lamination, exposure pattern, development, copper plating, film removal, and copper etching; or includes metal deposition, copper plating, dry film lamination, exposure pattern , development, copper etching, a series of processes to remove the film.

1j and 1k, a second accumulation layer 82 is formed above the first redistribution layer 61 and the second redistribution layer 62, an opening 813 is formed on the second accumulation layer 82, and an opening 813 is formed on the first surface of the circuit board. The second accumulation layer is provided with conductive blind vias, and a third redistribution layer electrically interconnected through the conductive blind vias and the first redistribution layer 61 and/or the second redistribution layer 62 is formed on the second accumulation layer 81 through the opening 813 63. In this embodiment, the third redistribution layers are located on the upper and lower sides of the package structure, respectively.

Referring to FIG. 11, a solder mask 10 is formed on the outermost circuit layer of the package structure, an opening is made on the solder mask above the outermost circuit layer, and the surface of the copper electrode at the opening of the solder mask is nickel-plated. The process of immersion gold to form the pad after depositing the nickel/gold layer;

Finally, as shown in FIG. 1m, a semiconductor package device and/or passive electronic component 101 is mounted over the opening in the solder mask 10, and the semiconductor package device and/or passive electronic component is rewired with a third through the pads layer electrical interconnection.

In other preferred embodiments, the packaged object involves one or more passive electronic components 7 in addition to the semiconductor chip 31 and the semiconductor chip package body 32 . One of the typical packaging structures can be seen in Figure 2, and its fabrication method is shown in Figures 2a-2l. The fabrication method is basically the same as the aforementioned fabrication method (Fig. 1a-Fig. 1m). For the opening or cavity 2 of the component 7, the first redistribution layer 61 and the third redistribution layer 63 are encapsulated correspondingly at the position corresponding to the opening or cavity 2 where the passive electronic component 7 is located.

Specifically, the semiconductor embedded hybrid package structure in another specific embodiment of the present invention, as shown in FIG. 2 , the package structure specifically includes:

Circuit board 1, that is, a circuit carrier for packaging semiconductor chips (Bare Die), semiconductor chip packages (SemiconductorPackage) and passive electronic components 7, which has a first surface 11 and a second surface 12 arranged oppositely;

At least one opening or cavity 2 provided in the circuit board 1 for accommodating a semiconductor chip 31, at least one for accommodating a semiconductor chip package 32, and at least one for accommodating a passive electronic component 7;

the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic element 7 disposed in the opening or cavity 2;

The packaging material 4 is used at least to cover the first surface 11 of the circuit board, the module alignment mark 5 and to fill the space in the opening or cavity 2 that is not occupied by the semiconductor chip 31 , the semiconductor chip package 32 and the passive electronic components 7 ;

The redistribution layer 6 is at least used to electrically connect the semiconductor chip 31 , the semiconductor chip package 32 , the passive electronic element 7 and the circuit board 1 .

2a and 2b, the first surface 11, the second surface 12, and the area between the first surface 11 and the second surface 12 of the circuit board are respectively provided with a circuit layer 13, and the module alignment mark 5 is provided on the The first surface of the circuit board 1, and the surface of the module alignment mark 5 and the second surface of the circuit board correspond to the highest surface and the lowest surface of the circuit board, respectively. The module alignment mark 5 is used to realize precise semiconductor chip, semiconductor chip package, passive electronic component arrangement and conductive line interconnection. All or part of the mark can simultaneously become a connection line and provide a conductive function.

The highest surface and the lowest surface of the opening or cavity 2 in the vertical direction are respectively the highest surface of the circuit board 1 or the surface of the module alignment mark 5 and the second surface 12 of the circuit board 1 or its The lowermost surface, and the boundary of the opening or cavity 2 in the horizontal direction is the opening of the circuit board 1 between the first surface 11 and the second surface 12 or the side wall of the cavity 2, while the opening or The cavity 2 includes a first space 21 and a second space 22, wherein the first space 21 is distributed between the first surface 11 and the second surface 12 of the circuit board 1, and the second space 22 is distributed in all the Between the first surface 11 of the circuit board 1 and the surface of the module alignment mark 5, and the side wall of the first space 21 is the circuit board between the first surface 11 and the second surface 12 of the circuit board 1 has a continuous section, and the second space 21 has no side walls.

Similar to the above-mentioned embodiment, the semiconductor chip package 32 contains at least one semiconductor bare chip 321 . Among them, a semiconductor bare wafer is a type of semiconductor device that is made by etching, wiring, etc. on a semiconductor sheet, and can realize a specific function. The semiconductor chip package body 32 can be obtained by plastic-encapsulating the above-mentioned semiconductor bare chip 321 with the plastic-encapsulating material 322 . The semiconductor chip package 32 is disposed in the opening or cavity 2 . The semiconductor chip package 32 includes electrodes/pads electrically connected to the semiconductor die 321 in the semiconductor chip package and extends outward from the semiconductor die 321 . The package internal conductive leads or wirings 323 and external electrodes 324 are electrically interconnected with electrodes/pads on the semiconductor die 321 in the semiconductor chip package via the internal conductive leads or wirings. The external electrode 324 of the semiconductor chip package may be a metal copper layer or a metal copper layer covered with a nickel/gold layer. The semiconductor chip package 32 may be a semiconductor chip package having a package structure such as InFO, WLCSP, eWLB, FOWLP, FC-BGA, FC-CSP, WB-BGA, QFN, or the like.

Different from the embodiment shown in FIG. 1 , in this embodiment, in addition to mounting the semiconductor chip 31 and the semiconductor chip package 32 in part of the opening or cavity 2 , the other opening or cavity 2 can also be used for mounting other passive components. Electronic components 7, passive electronic components include but are not limited to capacitors, resistors, inductors and other components, and the packaging material 4 is also used to fill the space not occupied by the passive electronic components 7 in the opening or cavity.

Further, in the present invention, the external electrode 324 of the semiconductor chip package 32 is exposed in the air or covered by a film; the external electrode 324 is a copper metal layer or a copper metal layer covered with a nickel/gold layer; The material of the film is an accumulation layer dielectric material, which may be a plastic packaging material, a build-up layer material, or other accumulation layer dielectric materials such as polyimide.

As in this embodiment, the packaging structure further includes a first accumulation covering at least the second surface 12 of the circuit board 1 , the packaging material 4 , the semiconductor chips 31 , the semiconductor chip package 32 and the passive electronic components 7 . Layer 81; the first accumulation layer 81 is a dielectric material layer, including an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layers.

As shown in FIG. 2h, the first accumulation layer 81 is provided with blind holes above the circuit layers of the semiconductor chip, the external electrodes of the semiconductor chip package, the passive electronic components 7 and the circuit board; the first accumulation layer is provided with a first rewiring layer 61, and the first redistribution layer 61 on the first accumulation layer 81 is electrically interconnected with semiconductor chips, external electrodes of semiconductor chip packages, passive electronic components and circuit layers on circuit boards through the blind vias. A second redistribution layer 62 is further provided on the packaging material 4 on the first surface 11 of the circuit board, and the second redistribution layer 62 passes through the conductive blind holes and the circuit layers, semiconductor chips, and/or semiconductor chips on the circuit board The package external electrodes 324 and/or the passive electronic components 7 are electrically interconnected.

Further, as shown in FIGS. 2i and 2j, the first redistribution layer 61 and the second redistribution layer 62 are covered with a second accumulation layer 82, and the second accumulation layer 82 is formed with the first redistribution layer respectively. The third redistribution layer 63 is electrically interconnected with the second redistribution layer, wherein the second accumulation layer is an ABF build-up layer, a photosensitive dielectric layer, or other dielectric material layers.

In addition, the package structure further includes a solder mask 10 covering at least the outermost circuit layer, an opening of the solder mask disposed above the outermost circuit layer, and the pads formed in the opening are mounted on the solder mask 10 There are other semiconductor packaged devices and/or passive electronic components 101, and passive electronic components include but are not limited to capacitors, resistors, inductors and other components. The semiconductor packaged devices and/or passive electronic components 101 are electrically connected to the third redistribution layer through the pads. interconnection. In this embodiment, the first accumulation layer and the second accumulation layer are both ABF build-up layers for illustration. In other embodiments, the first accumulation layer and the second accumulation layer may also be layers of other dielectric materials.

The above embodiment is only a preferred embodiment of the present invention, and it should be understood that in other embodiments, the first accumulation layer, the second accumulation layer, the first redistribution layer, the second redistribution layer and the third redistribution layer It can be set selectively, for example, only the first accumulation layer, the first redistribution layer and the second redistribution layer are set; in addition, other interconnections for electrical connection can be further set in addition to the above accumulation layer and redistribution layer As long as other semiconductor package devices and/or passive electronic components 101 are electrically connected to semiconductor chips, semiconductor chip packages, passive electronic components or circuit boards, the package structure belongs to the protection scope of the present invention.

Another aspect of the present invention also provides a method for fabricating a semiconductor embedded hybrid package structure, comprising the following steps:

S1. Provide a circuit board, which has a first surface and a second surface disposed opposite to each other, the circuit board is provided with at least one opening or cavity for accommodating semiconductor chips, semiconductor chip packages and passive electronic components, and A module alignment mark is provided around the opening or cavity on the first surface of the circuit board;

S2. Attach an adhesive film on the second surface of the circuit board, place the semiconductor chip, the semiconductor chip package and the passive electronic component into the opening or cavity, and make the semiconductor chip package Adhesive and fixed with adhesive film;

S3. Apply a packaging material on at least the first surface of the circuit board, the module alignment mark, and the opening or cavity, so that the first surface of the circuit board and the module alignment mark are covered by the packaging material, and make the opening or cavity is completely filled with packaging material and the semiconductor chip, semiconductor chip package and passive electronic components;

S4, removing the adhesive film, and turning the circuit board over;

S5, covering one or more accumulation layers on the second surface of the circuit board, the semiconductor chip, the semiconductor chip package, the passive electronic component, and the surface of the packaging material coplanar with the second surface of the circuit board;

S6. At least a redistribution layer for electrically connecting semiconductor chips, semiconductor chip packages, passive electronic components and circuit boards is formed on the accumulation layer.

Specifically, a method for fabricating a semiconductor embedded hybrid package structure in a preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 2a, a circuit board 1 is provided, which has a first surface 11 and a second surface 12 disposed opposite to each other, the first surface 11, the second surface 12 of the circuit board, and the first surface 11 and the second surface 12 on the first surface 11 and the second surface 12. The areas in between are respectively provided with circuit layers 13 . The circuit board 1 includes at least one opening or cavity 2 for accommodating the semiconductor chip 31 , the semiconductor chip package 32 and the passive electronic component 7 . Preferably, this embodiment includes a plurality of openings or cavities 2 for accommodating semiconductor chips 31 , semiconductor chip packages 32 and passive electronic components 7 respectively.

The module alignment mark 5 is disposed on the first surface of the circuit board 1 , and the surface of the module alignment mark 5 and the second surface of the circuit board correspond to the highest surface and the lowest surface of the circuit board, respectively.

Referring to Figures 2b and 2c, an adhesive film 201 is attached to the second surface 12 of the circuit board 1, and the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic component 7 are placed in the inverted state. The opening or cavity 2 is formed, and the external electrodes of the semiconductor chip package 3 and the adhesive film 201 are bonded and fixed in the opening or cavity 2 .

The structure of the semiconductor chip package 32 shown in FIG. 1 c in the first embodiment is the same as that of the semiconductor chip package 32 in this embodiment, and there is at least one semiconductor bare chip 321 in the semiconductor chip package 32 in this embodiment. Among them, a semiconductor bare wafer is a type of semiconductor device that is made by etching, wiring, etc. on a semiconductor sheet, and can realize a specific function. The semiconductor chip package body 32 can be obtained by plastic-encapsulating the above-mentioned semiconductor bare chip 321 with the plastic-encapsulating material 322 . The semiconductor chip package 32 is disposed in the opening or cavity 2 . The semiconductor chip package 32 includes electrodes/pads electrically connected to the semiconductor die 321 in the semiconductor chip package and extends outward from the semiconductor die 321 . The package internal conductive leads or wirings 323 and external electrodes 324 are electrically interconnected with electrodes/pads on the semiconductor die 321 in the semiconductor chip package via the internal conductive leads or wirings.

Referring to FIG. 2d, above the first surface 11 of the circuit board, the module alignment mark 5 and filling the space not occupied by the semiconductor chip 31, the semiconductor chip package 32 and the passive electronic components 7 in the opening or cavity 2 The plastic encapsulation forms a layer of encapsulation material 4 .

In this step, the encapsulation material 4 may also be planarized.

Wherein, the encapsulation material 4 may be a molding compound, epoxy resin, or epoxy resin/filler compound, etc., which fills the opening or cavity 2 and covers the first layer of the circuit board 1 as a flat build-up layer. A surface 11.

As shown in FIG. 2e, the adhesive film 201 is removed, and the circuit board 1 is turned over.

2f, 2g and 2h, on the second surface 12 of the circuit board 1 after flipping, at least covering the second surface 12 of the circuit board 1, the packaging material 4, the semiconductor chip 31, the semiconductor chip package 32 and the passive circuit board 1 are formed. The first accumulation layer 81 of the electronic component 7, and the first accumulation layer 81 above the electrodes of the semiconductor chip 31, the semiconductor chip package 3 and the external electrode 32 of the passive electronic component 7 is removed to form an opening 811, and the opening 811 is formed in the following ways. Laser drilling, lithography, etc. Then, the first redistribution layer 61 (RDL) is formed on the first accumulation layer 81 through the opening 811; similarly, the surface of the encapsulation material 4 on the first surface 11 of the circuit board 1 can also be removed by the laser opening process. An opening 812 is formed on the encapsulation material, and a second redistribution layer 62 is formed on the encapsulation material through the opening 812 . The formation method of the redistribution layer includes a series of processes of metal deposition, dry film lamination, exposure pattern, development, copper plating, film removal, and copper etching; or includes metal deposition, copper plating, dry film lamination, exposure pattern , development, copper etching, a series of processes to remove the film.

2i and 2j, a second accumulation layer 82 is formed above the first redistribution layer 61 and the second redistribution layer 62, an opening 813 is formed on the second accumulation layer 82, and an opening 813 is formed on the first surface of the circuit board. The second accumulation layer is provided with conductive blind vias, and a third redistribution layer electrically interconnected through the conductive blind vias and the first redistribution layer 61 and/or the second redistribution layer 62 is formed on the second accumulation layer 81 through the opening 813 63. In this embodiment, the third redistribution layers are located on the upper and lower sides of the package structure, respectively.

Referring to FIG. 2k, a solder mask 10 is formed on the outermost circuit layer of the package structure, an opening is made on the solder mask above the outermost circuit layer, and nickel plating is performed on the surface of the copper electrode at the opening of the solder mask. The process of immersion gold to form the pad after depositing the nickel/gold layer;

Finally, as shown in FIG. 21, a semiconductor package device and/or passive electronic component 101 is mounted over the opening in the solder mask 10, and the semiconductor package device and/or passive electronic component is rewired with a third through the pads Layer electrical interconnection.

Compared with the prior art, the semiconductor embedded hybrid packaging structure and the manufacturing method thereof in the present invention adopt the circuit board embedded technical scheme, which can simplify the integration process of the semiconductor chip and the semiconductor chip package, improve the integration quality and performance, and effectively. Reduce the integration area, including:

The packaging and processing of the semiconductor chip and the semiconductor package are completed on the circuit board at the same time, which omits the complex and cumbersome standards and process docking of the two in the prior art, reduces the circulation and transfer of electronic manufacturing, saves manpower and material resources, and can further reduce the cost of electronic products ;

The electrical connection between the semiconductor chip and the circuit board and the semiconductor chip package and the circuit board does not require a solder connection scheme, but adopts a simple copper redistribution (RDL) scheme, which has stable process and high reliability;

It can meet the assembly requirements of more precise semiconductor chips and semiconductor chip packages, such as the pad/pad spacing of semiconductor chips or semiconductor chip packages can be reduced to less than 150 microns/200 microns;

The embedded assembly of the semiconductor chip and the semiconductor chip package fully releases the surface area of the circuit board, and can achieve a significant reduction in the system assembly area, and the reduction ratio can exceed 50%.

It should be understood that the above descriptions are only the embodiments of the present invention, and are not intended to limit the scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied to other Relevant technical fields are similarly included within the scope of patent protection of the present invention.

Claims (11)

1. A semiconductor embedded hybrid package structure, the package structure comprising:

the circuit board is provided with a first surface and a second surface which are oppositely arranged;

an opening or cavity in the circuit board for accommodating at least the semiconductor chip and the semiconductor chip package;

a semiconductor chip disposed in the opening or cavity for at least receiving the semiconductor chip and the semiconductor chip package;

a semiconductor chip package disposed in the opening or cavity for at least receiving the semiconductor chip and the semiconductor chip package, the semiconductor chip package having at least one semiconductor bare chip and a semiconductor chip package with a plastic package material, the semiconductor chip package further comprising: a conductive lead or wire electrically connected to an electrode/pad of a semiconductor bare chip in a semiconductor chip package and extending outward from the semiconductor bare chip, and an external electrode electrically connected to the semiconductor bare chip; the external electrode is exposed in the air or covered by a film;

the packaging material is at least used for covering the first surface of the circuit board and filling the space which is not occupied by the semiconductor chip and the semiconductor chip packaging body in the opening or the cavity for accommodating the semiconductor chip and the semiconductor chip packaging body;

the first accumulation layer at least covers the second surface of the circuit board, the packaging material, the semiconductor chip and the semiconductor chip packaging body, the first accumulation layer is a dielectric material layer, and blind holes are formed in the first accumulation layer above the electrode/bonding pad of the semiconductor chip, the external electrode of the semiconductor chip packaging body and the circuit layer of the circuit board;

a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the circuit board, the rewiring layer including a first rewiring layer and a second rewiring layer; and

a solder mask covering at least the outermost circuit layer and an opening provided in the solder mask, the circuit layer provided in the opening in the solder mask forming a pad to which an external component is connected;

the first accumulation layer is provided with a first rewiring layer, the first rewiring layer on the first accumulation layer is electrically interconnected with an electrode/bonding pad of a semiconductor chip, an external electrode of a semiconductor chip packaging body and/or a circuit layer on a circuit board through the blind hole, a second rewiring layer is further arranged on packaging materials on the first surface of the circuit board, the second rewiring layer is electrically interconnected with at least the circuit layer on the circuit board, the semiconductor chip and/or an external electrode of the semiconductor chip packaging body through the conductive blind hole, the first rewiring layer and/or the second rewiring layer are/is covered with a second accumulation layer, and a third rewiring layer electrically interconnected with the first rewiring layer and/or the second rewiring layer is/are formed on the second accumulation layer.

2. The semiconductor embedded hybrid package structure of claim 1, wherein: the first surface of circuit board is provided with the module alignment sign, the surface of module alignment sign and the second surface of circuit board correspond respectively the highest surface and the lowest surface of circuit board.

3. The semiconductor embedded hybrid package structure of claim 1, wherein: and a passive electronic element is arranged in the opening or the cavity at least used for accommodating the semiconductor chip and the semiconductor chip packaging body, and the passive electronic element comprises any one or combination of a capacitor, a resistor and an inductance element.

4. The semiconductor embedded hybrid package structure of claim 1, wherein: the external electrode is made of a copper metal layer or a copper metal layer covered by a nickel/gold layer; the film is made of an accumulation layer dielectric material, and the accumulation layer dielectric material comprises a plastic package material, a layer adding material or polyimide.

5. The semiconductor embedded hybrid package structure of claim 3, wherein: the packaging material is also used for filling the space which is not occupied by the passive electronic element in the opening or the cavity at least used for accommodating the semiconductor chip and the semiconductor chip packaging body.

6. The semiconductor embedded hybrid package structure of claim 1 or 3, wherein: the package structure further includes the first accumulation layer including an ABF build-up layer or a photosensitive dielectric layer.

7. The semiconductor embedded hybrid package structure of claim 1, wherein: the second accumulation layer includes an ABF build-up layer or a photosensitive dielectric layer.

8. The semiconductor embedded hybrid package structure of claim 1, wherein: the packaging structure further comprises a semiconductor packaging device and/or a passive electronic element above the mounting solder mask, wherein the passive electronic element comprises any one or combination of a plurality of capacitance elements, resistance elements and inductance elements, and the semiconductor packaging device and/or the passive electronic element are electrically interconnected through the bonding pad and the third redistribution layer.

9. The method of fabricating a semiconductor embedded hybrid package structure of any one of claims 1-8, wherein the method of fabricating comprises the steps of:

s1, providing a circuit board, wherein the circuit board is provided with a first surface and a second surface which are oppositely arranged, and the circuit board is provided with an opening or a cavity which is at least used for accommodating the semiconductor chip and the semiconductor chip packaging body;

s2, attaching an adhesive film on the second surface of the circuit board, placing the semiconductor chip and the semiconductor chip package into the opening or the cavity at least for accommodating the semiconductor chip and the semiconductor chip package, and adhering and fixing the semiconductor chip and the semiconductor chip package with the adhesive film;

s3, applying packaging materials on at least the first surface of the circuit board and the opening or cavity at least used for accommodating the semiconductor chip and the semiconductor chip package, so that the first surface of the circuit board is covered by the packaging materials, and the opening or cavity at least used for accommodating the semiconductor chip and the semiconductor chip package is completely filled by the packaging materials and the semiconductor chip package;

s4, removing the adhesive film and turning over the circuit board;

s5, covering more than one accumulation layer on the second surface of the circuit board, the semiconductor chip packaging body and the packaging material surface coplanar with the second surface of the circuit board;

and S6, forming a rewiring layer at least for electrically connecting the semiconductor chip, the semiconductor chip package and the circuit board on the accumulation layer.

10. The method for manufacturing the semiconductor embedded hybrid package structure of claim 9, wherein the step S6 comprises:

arranging blind holes on a first accumulation layer positioned above an electrode/bonding pad of a semiconductor chip, an external electrode of a semiconductor chip packaging body and a circuit layer of a circuit board, and forming a first rewiring layer which is electrically interconnected with the electrode/bonding pad of the semiconductor chip, the external electrode of the semiconductor chip packaging body and/or the circuit layer on the circuit board through the blind holes;

arranging a second rewiring layer on the packaging material on the first surface of the circuit board; the second redistribution layer is electrically interconnected with the circuit layer on the circuit board, the semiconductor chip, and/or the external electrode of the semiconductor chip package via the conductive blind via;

a second accumulation layer is formed on the first redistribution layer and/or the second redistribution layer, a conductive blind via is provided on the second accumulation layer, and a third redistribution layer electrically connecting the first redistribution layer and/or the second redistribution layer via the conductive blind via is formed.

11. The method for manufacturing a semiconductor embedded hybrid package structure according to claim 10, wherein the step S6 is further followed by:

forming a solder mask on the outermost circuit layer of the packaging structure, and opening the solder mask above the circuit layer to form a corresponding pad;

and mounting a semiconductor packaging device and/or a passive electronic element above the solder mask, wherein the semiconductor packaging device and/or the passive electronic element are electrically interconnected with the third redistribution layer through the bonding pad.

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