CN106815380A - A method and system for extracting parasitic resistance - Google Patents

Abstract

The invention provides a method for extracting parasitic resistance, which comprises the following steps: simulating integrated circuit layout data; acquiring integrated circuit layout simulation data; and extracting parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters. The invention also provides a system for extracting the parasitic resistance. The scheme of the invention can effectively solve the problem of inaccuracy in extracting the parasitic resistance caused by the geometric figure deviation between actual manufacturing and integrated circuit design in the manufacturing process of the integrated circuit, and improve the accuracy of extracting the parasitic resistance.

Description

A method and system for extracting parasitic resistance

technical field

The invention belongs to the field of integrated circuit design, and in particular relates to a method and system for extracting parasitic resistance.

Background technique

With the development of technology, circuit optimization design has become an important stage in the integrated circuit design process. The purpose of circuit optimization is to improve the electrical performance of the circuit, and the final actual electrical performance of the circuit not only depends on the device parameter values of the circuit, but also depends on the parasitic effect of the device itself, the parasitic effect between devices, the parasitic effect of the connection itself, the connection The parasitic effect between the lines, and the parasitic effect between the wiring and the device, and the parasitic effect between the adjacent wiring is particularly critical. From the perspective of circuit optimization theory, in order to obtain accurate circuit optimization results, it is necessary to accurately consider the parasitic effects between the various device connections on the designed circuit, including the parasitic resistance between the interconnection lines.

The premise of the traditional method of extracting parasitic resistance is that the deviation between the geometric figures actually manufactured in the integrated circuit manufacturing process and the geometric figures in the layout data obtained from the integrated circuit design is very small and negligible on the X-Y plane, and the deviation in the Z direction is negligible. The deviation is so small that it can be ignored. Therefore, the traditional method of extracting parasitic resistance is shown in Figure 1. The parasitic resistance extraction engine extracts the parasitic resistance from the design data of the integrated circuit layout according to the process parameters of the integrated circuit to form a parasitic resistance netlist.

With the continuous improvement of integrated circuit process technology, the feature size of integrated circuit process is continuously reduced, and the spacing between interconnection lines is also continuously reduced, because of the inconsistency of optical effects caused by differences in adjacent graphics and the difference in the direction of etching. Due to the inconsistency of the metal chemical-mechanical-grinding (polishing) caused by the edge roughness of the metal pattern and the difference in the density of the metal pattern, the geometric figures actually produced in the integrated circuit manufacturing process and the geometric figures in the layout data obtained by the integrated circuit design The deviation between them is very large. This deviation is not only manifested as a geometric difference on the X-Y plane (parallel to the plane of the silicon wafer), but also as a geometric difference in the Z direction (perpendicular to the plane of the silicon wafer). This difference The impact of the change of parasitic resistance on the function and performance of the circuit is more obvious and cannot be ignored. The premise of the traditional method of extracting parasitic resistance is no longer valid, so the traditional method of extracting parasitic resistance is no longer suitable for the extraction of parasitic resistance of integrated circuit layout under advanced integrated circuit technology, especially for high-speed , Parasitic resistance extraction of high-frequency integrated circuit layout. To this end, we need new high-precision parasitic resistance extraction methods between metal interconnection lines in integrated circuit layouts.

Contents of the invention

The present invention provides a method and system for extracting parasitic resistance, which solves the problem of inaccurate extraction of parasitic resistance caused by the geometric deviation between actual manufacturing and integrated circuit design in the integrated circuit manufacturing process,

To achieve the above object, the present invention provides the following technical solutions:

A method for extracting parasitic resistance, comprising the following steps:

Simulation of integrated circuit layout data;

Obtain IC layout simulation data;

The parasitic resistance is extracted from the integrated circuit layout simulation data according to the integrated circuit process parameters.

Preferably, the integrated circuit layout data includes: data on the X-Y plane of the geometric figures on each physical layer, and data on the Z direction of the geometric figures on each physical layer.

Preferably, said simulating the integrated circuit layout data includes:

Carrying out lithography simulation on the X-Y plane of the layout data on each physical layer of the integrated circuit, so as to obtain the geometric shape curve of each geometric figure on the X-Y plane; and/or

The chemical-mechanical-grinding and polishing simulation is performed on the integrated circuit layout data in the Z direction, so as to obtain the geometric surface of each geometric figure in the Z direction.

Preferably, said simulating the integrated circuit layout data includes:

The chemical-mechanical-grinding and polishing simulation is performed on the dielectric layer in the Z direction to obtain the geometric surface of each dielectric layer in the Z direction.

Preferably, said simulating the integrated circuit layout data includes:

The integrated circuit layout data is simulated in the sequence of process steps used in fabrication.

Preferably, said simulating the layout data of the integrated circuit also includes:

Before performing the lithography simulation, the layout data of the integrated circuit is decomposed by double lithography or layout decomposed by multiple lithography, so as to obtain the decomposed layout data of the integrated circuit.

Preferably, said simulating the layout data of the integrated circuit also includes:

Before performing the lithography simulation, optical proximity correction is performed on the integrated circuit layout data.

Preferably, the process parameters of the integrated circuit include: resistivity of the physical wiring layer, thickness of the physical wiring layer, and thickness of the dielectric layer;

The parasitic resistance extraction of the integrated circuit layout simulation data includes:

Construct the three-dimensional geometric figure of the connection segment on the same connection layer;

The finite element or boundary element method is used to calculate the parasitic resistance of the connection segment on the three-dimensional geometric figure.

Preferably, the construction of the three-dimensional geometry of the connection segment on the same connection layer includes: using the integrated circuit layout and simulation data of the connection segment on the same connection layer to construct the front, rear, left, and right surface topography, construct the top surface topography, Build the lower surface topography.

Preferably, the construction of the front, rear, left, and right surface topography of the three-dimensional geometry of the physical connection segment includes: on the basis of the integrated circuit layout and simulation data of the connection segment on the same connection layer, using the physical connection segment in X-Y The geometric figure on the plane constructs the front, rear, left, and right surface topography, or uses the geometric figure topography curve on the X-Y plane to construct the front, back, left, and right surface topography, or uses the physical connection line on the X-Y plane The shape curve of the bottom surface and the shape curve of the top surface of the geometric figure construct the surface topography of the front, back, left and right sides.

Preferably, the construction of the lower surface morphology of the three-dimensional geometry of the physical connection segment includes: on the basis of the integrated circuit layout and simulation data of the connection segment on the same connection layer, constructing a horizontal bottom surface as the lower surface, or using the The topographic surface in the Z direction corresponding to the upper surface of the dielectric layer under the area where the layout pattern of the connection segment is located is used as the lower surface.

Preferably, the construction of the upper surface topography of the three-dimensional geometry of the physical connection segment includes: on the basis of the integrated circuit layout and simulation data of the connection segment on the same connection layer, the distance above the horizontal lower surface is Create a horizontal upper surface at the position of the thickness value of the line layer, or use the topographic surface of the layout graph of the line segment in the Z direction as the upper surface.

The present invention also provides a system for extracting parasitic resistance, including:

The simulation module is used to simulate the layout data of the integrated circuit and obtain the simulation data of the layout of the integrated circuit;

The extraction module is used to extract the parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters.

Preferably, the simulation module includes:

The first simulation unit is configured to perform lithography simulation on the X-Y plane of the integrated circuit layout data, so as to obtain the geometric shape on the X-Y plane; and/or

The second simulation unit is configured to perform chemical-mechanical-polishing simulation on the layout data of the integrated circuit in the Z direction, so as to obtain the geometric shape in the Z direction.

Preferably, the simulation module further includes: a third simulation unit, configured to perform chemical-mechanical-polishing simulation in the Z direction of the integrated circuit layout data, so as to obtain the geometry of each dielectric layer in the Z direction.

Preferably, the simulation module also includes:

The layout decomposition module is used to perform double lithography layout decomposition or multiple lithography layout decomposition on the integrated circuit layout data before performing the lithography simulation, so as to obtain decomposed integrated circuit layout data.

Preferably, the simulation module also includes:

The correction module is used to perform optical proximity correction on the integrated circuit layout data before performing the lithography simulation.

Preferably, the process parameters of the integrated circuit include: resistivity of the physical wiring layer, thickness of the physical wiring layer, and thickness of the dielectric layer;

The extraction module includes:

The three-dimensional geometry building module is used to construct the front, back, left, and right surface topography, the top surface topography and the bottom surface topography of the three-dimensional geometry using the integrated circuit layout and simulation data of the connection segment on the same connection layer.

The resistance calculation module is used to calculate the parasitic resistance of the connection segment by using finite element or boundary element method on the three-dimensional geometric figure.

Preferably, the three-dimensional geometry building blocks include:

The front, back, left, and right surface topography building module is used to construct the front, back, left, and right surface topography by using the geometric figures of the physical connection on the X-Y plane on the basis of the integrated circuit layout and simulation data of the wiring segment on the same wiring layer , or use the geometric shape curve of the physical connection on the X-Y plane to construct the front, rear, left, and right surface topography, or use the geometry curve of the physical connection on the X-Y plane on the bottom surface and the shape curve of the top surface The topography of the surface before and after the construction of the topography curve.

The lower surface building module is used to construct a horizontal bottom surface as the lower surface on the basis of the integrated circuit layout and simulation data of the wiring segment on the same wiring layer, or use the upper surface of the dielectric layer below the area where the wiring segment layout graphics are located to correspond to The topographic surface in the Z direction is used as the lower surface.

The upper surface building module is used to create a horizontal upper surface at a position above the horizontal lower surface whose distance is the thickness value of the wiring layer on the basis of the integrated circuit layout and simulation data of the wiring segment on the same wiring layer , or use the topographic surface of the layout graph in the Z direction as the upper surface.

It can be seen that the present invention provides a method and system for extracting parasitic resistance. By first simulating the layout data of the integrated circuit, and then extracting the parasitic resistance, it can effectively solve the geometric deviation between the actual manufacturing and the integrated circuit design in the integrated circuit manufacturing process. As a result, the problem of inaccurate extraction of the parasitic resistance is caused, and the accuracy of extraction of the parasitic resistance is improved. The method and system are also suitable for extracting parasitic resistance of high-speed and high-frequency integrated circuit layout under advanced integrated circuit technology.

Description of drawings

In order to illustrate the specific embodiments of the present invention more clearly, the accompanying drawings used in the embodiments will be briefly introduced below.

Figure 1: It is a schematic diagram of a method for extracting parasitic resistance in the prior art;

Figure 2: is a flow chart of a method for extracting parasitic resistance provided by the present invention;

Fig. 3: Schematic diagram of the method for extracting parasitic resistance provided by the first embodiment of the present invention;

Figure 4: Schematic diagram of the method for extracting parasitic resistance provided by the second embodiment of the present invention;

Fig. 5: a schematic diagram of a method for extracting parasitic resistance provided by the third embodiment of the present invention;

Fig. 6: a schematic diagram of a method for extracting parasitic resistance provided by the fourth embodiment of the present invention;

Fig. 7 is a schematic structural diagram of a system for extracting parasitic resistance provided by the present invention.

detailed description

In order to enable those skilled in the art to better understand the solutions of the embodiments of the present invention, the embodiments of the present invention will be further described in detail below in conjunction with the drawings and implementations.

In the integrated circuit manufacturing process under advanced integrated circuit technology, there is a deviation between the geometric figures actually manufactured and the geometric figures in the layout data obtained by design, which directly affects the accuracy of extracting parasitic resistance, which may cause the performance of circuit optimization The result is inaccurate.

As shown in FIG. 2 , it is a flowchart of a method for extracting parasitic resistance provided by the present invention. Include the following steps:

S1: Simulate the layout data of the integrated circuit;

S2: Acquiring integrated circuit layout simulation data;

S3: Perform parasitic resistance extraction on the integrated circuit layout simulation data according to the integrated circuit process parameters.

Further, the integrated circuit layout data includes: data on the X-Y plane of the geometric figures on each physical layer, and data on the Z direction of the geometric figures on each physical layer.

Specifically, the integrated circuit layout data also includes: the geometric figure topography curve data of each physical layer circuit layout geometry on the X-Y plane, the geometric figure topography surface data of each physical layer layout geometry in the Z direction of each layer circuit layout . The data may include: the thickness of the dielectric layer, the thickness of the wiring layer, the length of the interconnection line, and the like.

As shown in FIG. 3 , it is a schematic diagram of a method for extracting parasitic resistance provided by the first embodiment of the present invention. In the method, simulating the integrated circuit layout data includes: performing lithography simulation on the integrated circuit layout data on the X-Y plane, so as to obtain the geometric shape curve of each geometric figure on the X-Y plane; Chemical-mechanical-grinding and polishing simulation is performed on the above-mentioned integrated circuit layout data in the Z direction, so as to obtain the geometric surface of each geometric figure in the Z direction.

Further, the simulating the layout data of the integrated circuit includes: performing chemical-mechanical-grinding and polishing simulation on the dielectric layer in the Z direction, so as to obtain the geometric surface of each dielectric layer in the Z direction.

Furthermore, said simulating the layout data of the integrated circuit includes: simulating the layout data of the integrated circuit according to the order of the process steps adopted in manufacturing.

In practical applications, there are various simulation methods for simulating the layout data of integrated circuits. What this embodiment adopts is: carry out lithography simulation on the X-Y plane, to obtain the geometric shape curve of each geometric figure on the X-Y plane, thereby obtain the data such as the length of the interconnection line, the width of the interconnection line; Chemical-mechanical-grinding and polishing simulation to obtain the geometric topographic surface of each geometric figure in the Z direction, and the data such as the thickness distribution of interconnection lines can be obtained from the geometric topography curve on the X-Y plane and the geometric topography surface in the Z direction . At the same time, the simulation can be: lithography simulation only on the X-Y plane, or chemical-mechanical-grinding and polishing simulation only on the Z direction, or lithography simulation on the X-Y plane and Z direction in sequence Simulation of chemical-mechanical-abrasive polishing.

As shown in FIG. 4 , it is a schematic diagram of a method for extracting parasitic resistance provided by the second embodiment of the present invention. In the method, simulating the integrated circuit layout data further includes: before performing the lithography simulation, performing double lithography layout decomposition or multiple lithography layout decomposition on the integrated circuit layout data to obtain the decomposition The final integrated circuit layout data.

Specifically, in order to perform lithography simulation on the integrated circuit layout data more accurately, it is a good way to firstly perform layout decomposition of double lithography or layout decomposition of multiple lithography on the layout data of integrated circuits. Use other methods. For the decomposed layout data, lithography simulation can be performed on the X-Y plane, or lithography simulation on the X-Y plane and chemical-mechanical-grinding and polishing simulation on the Z direction can be performed sequentially.

As shown in FIGS. 5 and 6 , they are schematic diagrams of methods for extracting parasitic resistance provided by the third and fourth embodiments of the present invention. In the method, simulating the layout data of the integrated circuit further includes: performing optical proximity correction on the layout data of the integrated circuit before performing the lithography simulation.

Specifically, to further improve the accuracy of lithography simulation, it may be to perform lithography simulation on the X-Y plane after optical proximity effect correction is performed on the integrated circuit layout data, or to perform lithography simulation on the X-Y plane and in sequence Carry out chemical-mechanical-grinding and polishing simulation in the Z direction; it is also possible to perform layout decomposition of double lithography or layout decomposition of multiple lithography on the layout data of the integrated circuit, and then perform optical proximity effect correction on the decomposed layout data , and finally perform lithography simulation on the X-Y plane or sequentially perform lithography simulation on the X-Y plane and chemical-mechanical-abrasive polishing simulation on the Z direction.

Further, the integrated circuit process parameters include: physical wiring layer resistivity, physical wiring layer thickness, dielectric layer thickness, etc.; said extracting parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters includes:

Construct the three-dimensional geometric figure of the connection segment on the same connection layer;

The finite element or boundary element method is used to calculate the parasitic resistance of the connection segment on the three-dimensional geometric figure.

The construction of the three-dimensional geometry of the connection segment on the same connection layer includes: using the integrated circuit layout and simulation data of the connection segment on the same connection layer to construct the front, rear, left, and right surface topography, construct the upper surface topography, and construct the lower surface shape.

Said constructing the front, rear, left, and right surface topography of the three-dimensional geometry of the physical connection segment includes: on the basis of the integrated circuit layout and simulation data of the connection segment on the same connection layer, using the physical connection on the X-Y plane The surface topography before and after the geometry is constructed, or the geometry curve of the physical connection on the X-Y plane is used to construct the surface topography of the front, back, left and right, or the geometry of the physical connection on the X-Y plane is used in the The topography curve of the bottom surface and the topography curve construct the surface topography of front, back, left and right.

The construction of the lower surface morphology of the three-dimensional geometry of the physical connection segment includes: on the basis of the integrated circuit layout and simulation data of the connection segment on the same connection layer, constructing a horizontal bottom surface as the lower surface, or using the connection segment The topographic curved surface in the Z direction corresponding to the upper surface of the dielectric layer under the region where the layout pattern is located is used as the lower surface.

The upper surface topography of constructing the three-dimensional geometric figure of the physical connection segment includes: on the basis of the integrated circuit layout and simulation data of the connection segment on the same connection layer, the distance above the horizontal lower surface is the distance of the connection layer. Create a horizontal upper surface at the position of the thickness value, or use the shape surface of the layout graph of the line segment in the Z direction as the upper surface.

Specifically, the basic formula that can be used to extract parasitic resistance is R=Rs*L/W, where R is the parasitic resistance value, Rs is the square resistance, L is the length of the block, W is the width of the block, Rs=ρ/t , where ρ is the resistivity of the block, and t is the thickness of the block.

It can be seen that the present invention provides a method for extracting parasitic resistance. By simulating the layout data of the integrated circuit, more accurate shape curves of geometric figures on the X-Y plane and geometric surface data of geometric figures in the Z direction are obtained, and then The extraction of the parasitic resistance can effectively solve the problem of inaccurate extraction of the parasitic resistance caused by the geometric deviation between the actual manufacturing and the design of the integrated circuit in the manufacturing process of the integrated circuit, and improve the accuracy of the extraction of the parasitic resistance.

The present invention also provides a system for extracting parasitic resistance, as shown in FIG. 7 , which is a schematic structural diagram of a system for extracting parasitic resistance provided by the present invention. The system includes: a simulation module for simulating integrated circuit layout data to obtain integrated circuit layout simulation data; an extraction module for extracting parasitic resistance from the integrated circuit layout simulation data according to integrated circuit process parameters.

In practical applications, the extraction module may use a parasitic resistance extraction engine, and the parasitic resistance extraction engine extracts parasitic resistances according to integrated circuit process parameters to generate a parasitic resistance netlist. Of course, other methods can also be used to report the parasitic resistance, which is determined according to specific operation requirements.

The simulation module includes: a first simulation unit and/or a second simulation unit. Wherein, the first simulation unit is used to perform lithography simulation on the X-Y plane of the integrated circuit layout data, so as to obtain the shape curve geometry of the geometric figure on the X-Y plane; the second simulation unit is used to perform the integrated circuit layout data on the X-Y plane. The layout data is subjected to chemical-mechanical-grinding and polishing simulation in the Z direction, so as to obtain the geometric topography surface graph of the geometric figure in the Z direction.

Further, the simulation module further includes: a third simulation unit, configured to perform chemical-mechanical-polishing simulation in the Z-direction of the integrated circuit layout data, so as to obtain the geometry of each dielectric layer in the Z-direction.

In another embodiment of the system of the present invention, the simulation module may further include: a layout decomposition module, configured to perform double lithography layout decomposition or layout decomposition on the integrated circuit layout data before performing the lithography simulation Layout decomposition of multiple lithography to obtain decomposed IC layout data.

Since the feature size of the integrated circuit process is continuously reduced, the spacing between the interconnection lines is also continuously reduced. In order to improve the accuracy of the lithography simulation, this embodiment performs double lithography on the integrated circuit layout data through the layout decomposition module. The layout decomposition of multiple lithography or the layout decomposition of multiple lithography makes the decomposed layout data more suitable for the process requirements of lithography simulation, so as to improve the accuracy of lithography simulation. In practical applications, the simulation module may also include a first simulation unit and a layout decomposition module, or may include a first simulation unit, a second simulation unit, and a layout decomposition module, or may include a first simulation unit, a second simulation unit, and a layout decomposition module. A simulation unit, a third simulation unit and a layout decomposition module. It is mainly based on the specific selection process to choose.

In another embodiment of the system of the present invention, the simulation module may further include: a correction module, configured to perform optical proximity effect correction on the integrated circuit layout data before performing the lithography simulation.

Due to the inconsistency of the optical proximity effect caused by the difference of adjacent graphics in the integrated circuit, the layout data may be inaccurate. Data Accuracy.

In practical applications, the simulation module may also include a first simulation unit and a correction module, or may include a first simulation unit, a second simulation unit and a correction module, or may include a first simulation unit, a second simulation unit , the third simulation unit and the correction module can also be the first simulation unit, the layout decomposition module and the correction module, or the first simulation unit, the second simulation unit, the layout decomposition module and the correction module, and of course it can also be the first simulation unit A simulation unit, a second simulation unit, a third simulation unit, a layout decomposition module and a correction module.

Further, the process parameters of the integrated circuit include: resistivity of the physical wiring layer, thickness of the physical wiring layer, and thickness of the dielectric layer.

The extraction module includes: a three-dimensional geometry building module and a resistance calculation module. The three-dimensional geometry building module is used to construct the front, back, left, and right surface topography, top surface topography, and bottom surface topography of the three-dimensional geometric figure by using the integrated circuit layout and simulation data of the connection segment on the same connection layer. The resistance calculation module is used to calculate the parasitic resistance of the connection segment by using finite element or boundary element method on the three-dimensional geometric figure.

Further, the three-dimensional geometry building blocks include: front, rear, left, and right surface topography building blocks, lower surface building blocks, and upper surface building blocks.

The front, rear, left, and right surface topography construction module is used to construct the front, rear, left, and right surfaces by using the geometric figures of the physical connection on the X-Y plane on the basis of the integrated circuit layout and simulation data of the line segment on the same line layer Topography, or use the geometry curve of the physical connection on the X-Y plane to construct the front, rear, left, and right surface topography, or use the geometry curve of the physical connection on the X-Y plane on the bottom surface and the topography curve Surface topography curves construct the front, back, left, and right surface topography.

The lower surface construction module is used to build a horizontal bottom surface as the lower surface on the basis of the integrated circuit layout and simulation data of the wiring segment on the same wiring layer, or use the dielectric layer below the area where the layout graphics of the wiring segment is located. The topographic surface corresponding to the surface in the Z direction is used as the lower surface.

The upper surface building module is used to create a horizontal horizontal at a position above the horizontal lower surface whose distance is the thickness value of the wiring layer on the basis of the integrated circuit layout and simulation data of the wiring segment on the same wiring layer. The upper surface, or use the topographic surface of the layout graph of the connecting line segment in the Z direction as the upper surface.

It can be seen that a system for extracting parasitic resistance provided by the present invention uses a simulation module and an extraction module to extract parasitic resistance of integrated circuit layout data according to integrated circuit process parameters, which can effectively solve the problem of actual manufacturing and integrated circuit in the integrated circuit manufacturing process. The geometric deviation of the design causes the problem of inaccurate extraction of parasitic resistance, and improves the accuracy of extraction of parasitic resistance.

The structure, features and effects of the present invention have been described in detail above based on the embodiments shown in the drawings. The above descriptions are only preferred embodiments of the present invention, but the present invention does not limit the scope of implementation as shown in the drawings. Changes made to the idea of the present invention, or modifications to equivalent embodiments that are equivalent changes, and still within the spirit covered by the description and illustrations, shall be within the protection scope of the present invention.

Claims (19)

1. it is a kind of extract dead resistance method, it is characterised in that comprise the following steps：

Integrated circuit layout data is emulated；

Obtain integrated circuit diagram emulation data；

Dead resistance is carried out according to integrated circuit process parameter to integrated circuit diagram emulation data to carry Take.

2. the method for extracting dead resistance according to claim 1, it is characterised in that described integrated Circuit layout data include：Geometric figure data, each thing on an x-y plane in each physical layer Geometric figure data in z-direction on reason layer.

3. the method for extracting dead resistance according to claim 1, it is characterised in that described pair of collection Carrying out emulation into circuit layout data includes：

Lithography simulation is carried out on an x-y plane to layout data in the integrated circuit each physical layer, To obtain each geometric figure geometrical morphology curve on an x-y plane；And/or

Carry out chemical-mechanical-grinding and polishing emulation in z-direction to the integrated circuit layout data, To obtain each geometric figure geometrical morphology curved surface in z-direction.

4. the method for extracting dead resistance according to claim 3, it is characterised in that described pair of collection Being emulated into circuit layout data also includes：

Chemical-mechanical-grinding and polishing emulation is carried out in z-direction to dielectric layer, to obtain each dielectric layer Geometrical morphology curved surface in z-direction.

5. the method that dead resistance is extracted according to claim 3 or 4, it is described to integrated circuit version Diagram data is emulated also to be included：

Integrated circuit layout data is emulated according to the order for manufacturing used processing step.

6. the method for extracting dead resistance according to claim 3, it is characterised in that described pair of collection Being emulated into circuit layout data also includes：

Before the lithography simulation is carried out, dual photoetching is first carried out to the integrated circuit layout data Domain decompose or multiple photoetching domain decompose, with the integrated circuit layout data after being decomposed.

7. the method that dead resistance is extracted according to claim 3 or 6, it is characterised in that described Integrated circuit layout data is emulated also to be included：

Before the lithography simulation is carried out, optics is first carried out to the integrated circuit layout data and is closed on Effect amendment.

8. the method for extracting dead resistance according to claim 1, it is characterised in that described integrated Circuit technology parameter includes：Physical connection layer resistivity, physical connection thickness degree, thickness of dielectric layers；

The integrated circuit diagram emulation data carry out dead resistance to be extracted includes：

Build the three-dimensional geometrical figure of line section on same connecting line layer；

The parasitism electricity of line section is calculated the three-dimensional geometrical figure using finite element or boundary element method Resistance.

9. the method for extracting dead resistance according to claim 8, it is characterised in that the structure The three-dimensional geometrical figure of line section includes on same connecting line layer：Using the collection of line section on same connecting line layer Into circuit layout and emulation data structure surface topography, structure upper surface topography, structure all around Lower surface pattern.

10. the method for extracting dead resistance according to claim 9, it is characterised in that the structure The surface topography all around for building physical connection section three-dimensional geometrical figure includes：On same connecting line layer It is flat in X-Y using this section of physical connection on the basis of the integrated circuit diagram and emulation data of line section Geometric figure on face builds surface topography all around, or flat in X-Y using this section of physical connection Geometric figure topography profile on face builds surface topography all around, or utilizes this section of physical connection Geometric figure on an x-y plane is left before and after the topography profile of bottom surface and the topography profile of top surface build Right surface topography.

11. methods for extracting dead resistance according to claim 9, it is characterised in that the structure The lower surface pattern for building physical connection section three-dimensional geometrical figure includes：The line section on same connecting line layer On the basis of integrated circuit diagram and emulation data, building horizontal bottom should as lower surface, or utilization The corresponding pattern curved surface in Z-direction in line section layout patterns region lower dielectric layer upper surface is made It is lower surface.

12. methods for extracting dead resistance according to claim 9, it is characterised in that the structure The upper surface topography for building physical connection section three-dimensional geometrical figure includes：The line section on same connecting line layer On the basis of integrated circuit diagram and emulation data, distance is the connecting line layer above the lower surface of level Thickness value position at create level upper surface, or using the line section layout patterns in Z-direction Pattern curved surface as upper surface.

A kind of 13. systems for extracting dead resistance, it is characterised in that including：

Emulation module, for being emulated to integrated circuit layout data, obtains integrated circuit diagram and imitates True data；

Extraction module, for emulating data to the integrated circuit diagram according to integrated circuit process parameter Carry out dead resistance extraction.

14. systems that dead resistance is extracted according to claim 13, it is characterised in that described imitative True module includes：

First simulation unit, for carrying out photoetching on an x-y plane to the integrated circuit layout data Emulation, to obtain each geometric figure geometrical morphology on an x-y plane；And/or

Second simulation unit, for the integrated circuit layout data is carried out in z-direction chemistry- Mechanical-polish is emulated, to obtain geometrical morphology of each geometric figure in Z-direction.

15. systems that dead resistance is extracted according to claim 14, it is characterised in that described imitative True module also includes：

3rd simulation unit, for carried out in the integrated circuit layout data Z-direction chemical-mechanical- Polishing emulation, to obtain geometrical morphology of each dielectric layer in Z-direction.

16. systems that dead resistance is extracted according to claim 14, it is characterised in that described imitative True module also includes：

Domain decomposing module, for before the lithography simulation is carried out, to the integrated circuit diagram The domain of domain decomposition or multiple photoetching that data first carry out dual photoetching is decomposed, after being decomposed Integrated circuit layout data.

17. systems that dead resistance is extracted according to claim 14 or 16, it is characterised in that The emulation module also includes：

Correcting module, for before the lithography simulation is carried out, to the integrated circuit layout data First carry out optical approach effect amendment.

18. systems that dead resistance is extracted according to claim 13, it is characterised in that the collection Include into circuit technology parameter：Physical connection layer resistivity, physical connection thickness degree, thickness of dielectric layers；

The extraction module includes：

Three-dimensional geometrical figure builds module, for the integrated circuit version using line section on same connecting line layer Figure and emulation data build three-dimensional geometrical figure surface topography all around, build upper surface topography, Build lower surface pattern.

Resistance calculations module, for being calculated using finite element or boundary element method the three-dimensional geometrical figure The dead resistance of line section.

19. systems that dead resistance is extracted according to claim 18, it is characterised in that described vertical Body geometric figure builds module to be included：

All around surface topography builds module, for the integrated circuit of the line section on same connecting line layer On the basis of domain and emulation data, using this section of physical connection geometric figure structure on an x-y plane Build surface topography all around, or the geometric figure shape using this section of physical connection on an x-y plane Looks curve builds surface topography all around, or using this section of physical connection on an x-y plane several What figure builds surface topography all around in the topography profile of bottom surface and the topography profile of top surface.

Lower surface builds module, for the integrated circuit diagram of line section and emulation on same connecting line layer On the basis of data, horizontal bottom is built as lower surface, or using where line section layout patterns The corresponding pattern curved surface in Z-direction in region lower dielectric layer upper surface is used as lower surface.

Upper surface builds module, for the integrated circuit diagram of line section and emulation on same connecting line layer On the basis of data, distance is to be created at the position of the thickness value of the connecting line layer above the lower surface of level Build horizontal upper surface, or by the use of line section layout patterns Z-direction pattern curved surface as upper table Face.