CN106814969A - Data buffer adjusting device and method thereof - Google Patents

Abstract

The invention discloses a data buffer adjustment device and a method thereof, which are applicable to a solid state disk, wherein the solid state disk comprises a power supply unit, a monitoring unit, a control unit, a quick access unit and a storage unit, the power supply unit provides access power from a first power source module or a second power source module, the access power provides the whole storage device when the power is off and the access data is written into the storage unit from the quick access unit, and the data buffer adjustment method comprises the following steps. And monitoring the magnitude of the charge capacity of the second power source module by using the monitoring unit. The size of the temporary storage space of the quick access unit is dynamically adjusted according to the size of the storage capacity. The data size of the access data is determined according to the size of the temporary storage space. By monitoring the electric quantity of the second power source module in real time, the control unit can adjust the size of the temporary storage space in the quick access unit along with the electric quantity, and the situation that data cannot be written back to the NAND flash memory from a quick access area due to insufficient electric power can be avoided.

Description

Data buffer adjustment device and method thereof

technical field

The present invention relates to a data buffer adjustment device, in particular to a data buffer adjustment device which can prevent data from being unable to be written back from a cache area to a NAND flash memory due to insufficient power, and an adjustment method using this technical feature.

Background technique

Solid-state drive (SSD, Solid-State Drive) is a storage device that has emerged in recent years, and its performance greatly surpasses that of traditional hard drives. Because the interior of SSD is composed of many Flash memories, the transmission speed is much better than the traditional hard disk with mechanical devices. Among the many electronic components inside an SSD are two that are key to its composition. The first is the NAND flash memory responsible for storing data, and the second is the controller that controls the solid-state drive. These two components are closely related and are responsible for the storage, transmission, and operation of the entire SSD.

In addition, in the solid-state hard disk, a dynamic random access memory can also be included as a cache. Before writing data into the NAND flash memory, the controller can first put the data into the fast memory planned by the dynamic random access memory. The access area is used to increase the access speed of a computer host to access the solid-state hard disk, and after a certain period of time, the data is written back to the NAND flash memory to maintain data consistency.

In order to solve the NAND Flash write data error caused by unexpected power outages, generally speaking, a backup power supply device (such as: lithium battery) will be placed in the solid-state hard drive. When the solid-state hard drive encounters abnormal power outages , so that the backup power supply device supplies power to the controller, ensuring that the controller can completely write the data in the cache area into the NAND flash memory. However, the following problems may exist in the above architecture.

(1) When the storage capacity of the backup power supply device is proportional to its remaining service life, taking a lithium battery as an example, if the remaining service life of the lithium battery is about to end, its low power will cause the controller to fail to completely The data in the cache area is written back to the NAND flash memory.

(2) If the solid-state hard disk uses a lithium battery as a backup power supply device and the frequency of abnormal power outages of the solid-state hard disk is too high, the lithium battery will be charged and discharged repeatedly, and its storage capacity may be damaged due to insufficient charging. The power is too low, so that the controller cannot completely write back the data in the cache area to the NAND flash memory.

In view of the foregoing, the inventor of the present invention conceived and designed a data buffer adjustment device and method thereof, in order to improve the deficiencies of the prior art, and further enhance industrial implementation and utilization.

Contents of the invention

The purpose of the present invention is to provide a data buffer adjustment device and its method to solve the problem in the prior art that the storage capacity is too low due to insufficient charging, so that the controller cannot completely write back the data in the cache area to problems in NAND flash memory.

The present invention provides a data buffer adjustment method, which is suitable for a solid-state hard disk. The solid-state hard disk includes a power supply unit, a monitoring unit, a control unit, a cache unit, and a storage unit. The power supply unit consists of a first The power source module or a second power source module provides access power, and the access power provides the required power for writing an access data from the cache unit to the storage unit. The data buffer adjustment method includes the following steps. The storage capacity of the second power source module is monitored by the monitoring unit. The size of the temporary storage space of the cache unit is dynamically adjusted according to the storage capacity. The amount of data to be accessed is determined according to the size of the temporary storage space.

Preferably, the data buffer adjustment method of the present invention further includes charging the second power source module by the power supply unit.

Preferably, the data buffer adjustment method of the present invention further includes providing access power by the second power source module when the first power source module stops providing access power.

Preferably, the first power source module can be a power supply, and the second power source module can be a lithium battery, a capacitor or an energy storage battery.

Preferably, the monitoring unit can be a battery capacity calculation chip.

Preferably, the cache unit can be a dynamic random access memory, and the storage unit can be a NAND flash memory.

Based on the above purpose, the present invention further provides a data buffer adjustment device, which includes a storage unit, a cache unit, a control unit, a power supply unit and a monitoring unit. The storage unit can be used to store an access data. The cache unit may include a temporary storage space for temporarily storing an access data. The control unit can write access data from the cache unit to the storage unit, or write access data from the storage unit to the cache unit. The power supply unit provides access power required for the control unit to operate, and the access power is provided by the first power source module or the second power source module. The monitoring unit monitors a storage capacity of the second power source module and transmits the storage capacity to the control unit. The control unit dynamically adjusts the size of the temporary storage space according to the storage capacity, and adjusts the data volume for writing and accessing data according to the size of the temporary storage space.

Preferably, the first power source module can be a power supply, and the second power source module can be a lithium battery, a capacitor or an energy storage battery.

Preferably, the monitoring unit can be a battery capacity calculation chip.

Preferably, the cache unit can be a dynamic random access memory, and the storage unit can be a NAND flash memory.

Preferably, when the first power source module stops providing access power, the access power is provided by the second power source module.

Based on the above, the data buffer adjustment device and method thereof according to the present invention can have the following advantages:

By monitoring the power of the second power source module in real time, the control unit can adjust the size of the temporary storage space in the cache unit according to the power. In this way, no matter whether the power is accessed by the first power source module or the second power source module Provided by the two power source modules, the controller can write the access data in the cache unit to the storage unit. That is to say, the controller can write back the access data stored in the cache to the NAND flash memory under any circumstances to ensure data consistency.

Description of drawings

FIG. 1 is a block diagram of a data buffer adjustment device of the present invention.

FIG. 2A is a first schematic diagram of the first embodiment of the data buffer adjustment device of the present invention.

FIG. 2B is a second schematic diagram of the first embodiment of the data buffer adjustment device of the present invention.

FIG. 3 is a flow chart of the steps of the data buffer adjustment method of the present invention.

detailed description

In order to facilitate the understanding of the technical features, content and advantages of the present invention and the effects that can be realized, the present invention is combined with the accompanying drawings, and is described in detail in the form of embodiments as follows, and the accompanying drawings used herein are only intended to The purpose of illustration and auxiliary instructions is not necessarily the true proportion and precise configuration of the present invention after implementation, so the scale and configuration relationship of the attached drawings should not be interpreted or limited to the scope of rights of the present invention in actual implementation. Bright.

Please refer to FIG. 1 , which is a block diagram of the data buffer adjustment device of the present invention. As shown in the figure, the data buffer adjustment device 100 may include a storage unit 10 , a cache unit 20 , a control unit 30 , a power supply unit 40 and a monitoring unit 50 . The storage unit 10 can be a plurality of NAND flash memories, the fast access unit 20 can be a quick access divided in a dynamic random access memory, the monitoring unit 50 can be a battery capacity calculation chip, and the control unit 30 can be a control device, and the control unit 30 is electrically connected to the storage unit 10 , the cache unit 20 , the power supply unit 40 and the monitoring unit 50 .

Preferably, the data buffer adjustment device 100 can be implemented as an example of a solid-state hard disk, which can be connected to a computer host through a data transmission line, and the computer host sends and writes an access data 11 to the data buffer Adjustment device 100 .

In detail, the cache unit 20 may include a temporary storage space 21 to temporarily store the access data 11, and after a normal time, the control unit 30 may write the access data 11 from the cache unit 20 to the storage unit 10 , and thus the storage unit 10 stores the access data 11 . Or, on the other hand, the control unit 30 can also write the access data 11 from the storage unit 10 to the cache unit 20 , so that the host computer can directly access the access data 11 on the cache unit 20 .

The power supply unit 40 provides an access power 41 required for the operation of the control unit 30. This operation includes the storage, transmission, operation, etc. of the entire data buffer adjustment device 100. For example, the control unit 30 controls the access data 11 In the transfer operation between the storage unit 10 and the cache unit 20 , the access power 41 is used to ensure that the control unit 30 completes each transfer operation of the access data 11 . In addition, the access power 41 is provided by the first power source module 42 or the second power source module 43, wherein the first power source module 42 can be a power supply on the computer host, and the second power source module 43 can be It is a backup power source, such as a lithium battery, a capacitor or an energy storage battery.

In detail, the first power source module 42 and the second power source module 43 are respectively the main power source and the secondary power source of the data buffer adjustment device 100 . Under normal circumstances, the first power source module 42 provides access power 41 to the control unit 30 and also provides power to the second power source module 43 for charging. And when the first power source module 42 stops providing the access power 41 , the access power 41 is provided by the second power source module 43 .

The monitoring unit 50 regularly monitors a storage capacity 51 of the second power source module 43 , and transmits information of the storage capacity 51 to the control unit 30 . The control unit 30 can dynamically adjust the size of the temporary storage space 21 of the cache unit 20 according to the value of the storage amount 51 , and adjust the amount of data written into the access data 11 according to the size of the temporary storage space 21 .

Please refer to FIG. 2A and FIG. 2B , which are the first schematic diagram and the second schematic diagram of the first embodiment of the data buffer adjustment device of the present invention, and please refer to the text and symbol description in FIG. 1 . In this embodiment, the data buffer adjustment device 100 is implemented by taking a solid-state hard disk 101 as an example. The memory, the controller and the battery capacity calculation chip are taken as examples, wherein the control unit 30 is electrically connected to the storage unit 10 , the cache unit 20 , the monitoring unit 50 and the power supply unit 40 . In addition, in this embodiment, the data buffer adjustment device 100 also includes a lithium battery 431 as the second power source module 43, and also includes a charging and discharging control unit 61 to control the second power source module 43 and the power supply unit 40 Between the charge and discharge management mechanism.

When the solid state disk 101 is electrically connected to a computer host, the power source of the power supply unit 40 is provided by the first power source module 42. In this embodiment, the power supply of the computer host is used as an example, and the power The source is transmitted to the power supply unit 40 through a power flat cable 421 . The control unit 30 can use the power source for data storage, transmission, and operation. At the same time, the power supply unit 40 can also charge the lithium battery 431 through the charge and discharge control unit 61 .

In this embodiment, the monitoring unit 50 will regularly monitor the storage capacity 51 of the lithium battery 431. It is worth mentioning that the storage capacity 51 of the lithium battery 431 may be different due to its service life or repeated charging and discharging. The storage capacity percentage, and the monitoring unit 50 can report or notify the storage capacity percentage to the control unit 30, and then the control unit 30 adjusts the size of the temporary storage space 21 of the cache unit 20 according to the storage capacity percentage.

For example, the default size of the temporary storage space 21 of the cache unit 20 in the solid state disk 101 is 16MB, and the control unit 30 can adjust the size of the temporary storage space 21 according to a ratio. As shown in Figure 2B, when the monitoring unit 50 monitors that the storage capacity 51 is 80%, the control unit 30 can change the temporary storage space 21 to 8MB, and when the storage capacity 51 is 40%, the temporary storage space 21 It can be changed to 2MB. The above-mentioned ratio is only an example and is not limited thereto, as long as the storage capacity 51 is enough for the control unit 30 to completely move the access data 11 stored in the temporary storage space 21 to the storage unit within 10.

Explain in detail, the control unit 30 adjusts the size of the temporary storage space 21 and the actions of moving and accessing the data 11 can be taken care of by a firmware on the control unit 30. Meanwhile, this firmware also includes efficiently allowing the page (Page ) are written evenly to prevent the same page from being frequently read and written and shorten the lifespan of the SSD. Here, the implementation of the firmware may be different due to different manufacturers, and the technology of the firmware is also an existing technology well known to those skilled in the field of computer software, so it will not be repeated here.

Please refer to FIG. 3 , which is a flow chart of the steps of the data buffer adjustment method of the present invention. This data buffer adjustment method is suitable for a solid state hard disk, wherein the solid state hard disk includes a power supply unit, a monitoring unit, a control unit, a cache unit and a storage unit, and the control unit is electrically connected to the power supply unit, the monitoring unit Unit, cache unit and storage unit, the power supply unit is provided with access power by a first power source module or a second power source module, and the control unit can write an access data from the cache unit to the storage unit , and the access power can provide a power required for the control unit to operate. The data buffer adjustment method includes the following steps.

Step S11 utilizes the monitoring unit to monitor a storage capacity of a second power source module.

Step S12 dynamically adjusts the size of a temporary storage space of the cache unit according to the storage capacity.

Step S13 determines the amount of data to be accessed according to the size of the temporary storage space.

The data buffer adjustment method in this embodiment further includes charging the second power source module by the power supply unit, and when the first power source module stops providing access power, the second power source module provides access power, The first power source module can be a power supply, and the second power source module can be a lithium battery, a capacitor or an energy storage battery. Since the size of the temporary storage space is adjusted according to the storage capacity, the access power provided by the second power source module can ensure that the control unit writes back the access data on the cache unit to the storage unit.

Preferably, the monitoring unit can be a battery capacity calculation chip. The cache unit can be a dynamic random access memory, and the storage unit can be a NAND flash memory.

It can be known from the above that the data buffer adjustment device and method thereof of the present invention can adjust the size of the temporary storage space in the cache unit according to a storage capacity of the second power source module, so as to ensure that the control unit can The access data in the temporary storage space is written back to the storage unit, which can effectively prevent the inconsistency of the access data on the storage unit.

The above descriptions are illustrative only, not restrictive. Any equivalent modifications or changes made without departing from the spirit and scope of the present invention shall be included in the appended claims.

Claims (11)

1. a kind of data buffering method of adjustment, suitable for solid state hard disc, the solid state hard disc includes electric power supply unit, monitoring unit, control unit, cache and storage element, wherein described electric power supply unit provides access electric power by the first power source module or the second power source module, the access electric power provides and access data is write to the required electric power of the storage element from the cache, characterized in that, comprising：

The charge capacity of the second power source module is monitored using the monitoring unit；

Size according to the charge capacity is with the size of the temporarily providing room of the dynamic adjustment cache；And

Size according to the temporarily providing room is determining the data volume of the access data.

2. data buffering method of adjustment as claimed in claim 1, it is characterised in that also comprising being charged to the second power source module by the electric power supply unit.

3. data buffering method of adjustment as claimed in claim 1, it is characterised in that also comprising when the first power source module stops providing the access electric power, the access electric power is provided by the second power source module.

4. data buffering method of adjustment as claimed in claim 1, it is characterised in that the first power source module is power supply unit, and the second power source module is lithium battery, electric capacity or energy-storage battery.

5. data buffering method of adjustment as claimed in claim 1, it is characterised in that the monitoring unit is that battery capacity calculates chip.

6. data buffering method of adjustment as claimed in claim 1, it is characterised in that the cache is DRAM, the storage element is nand flash memory.

7. a kind of data buffering adjusting apparatus, it is characterised in that include：

Storage element, is used to store access data；

Cache, comprising temporarily providing room with the temporary access data；

Control unit, the access data are write to the storage element from the cache, or the access data are write to the cache from storage element；

Electric power supply unit, there is provided the access electric power needed for described control unit start, wherein the access electric power is provided by the first power source module or the second power source module；And

Monitoring unit, monitors the charge capacity of the second power source module and transmits the big as low as described control unit of the charge capacity；

Wherein described control unit adjusts the size of the temporarily providing room according to the size of the charge capacity with dynamic, and writes the data volume of the access data to adjust according to the size of the temporarily providing room.

8. data buffering adjusting apparatus as claimed in claim 7, it is characterised in that the first power source module is power supply unit, and the second power source module is lithium battery, electric capacity or energy-storage battery.

9. data buffering adjusting apparatus as claimed in claim 7, it is characterised in that the monitoring unit is that battery capacity calculates chip.

10. data buffering adjusting apparatus as claimed in claim 7, it is characterised in that the cache is DRAM, the storage element is nand flash memory.

11. data buffering adjusting apparatus as claimed in claim 7, it is characterised in that when the first power source module stops providing the access electric power, the access electric power is provided by the second power source module.